firesim: productive, scalable, fpga-accelerated cycle

FireSim: Productive, Scalable, FPGA-Accelerated Cycle-Accurate Hardware

Simulation using Cloud FPGAsSagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Borivoje Nikolic, Randy Katz, Jonathan Bachrach, Krste Asanovic.

Dept. of Electrical Engineering and Computer Sciences, UC Berkeley. Contact: sagark@eecs.berkeley.edu

The information, data, or work presented herein was funded in part by the AdvancedResearch Projects Agency-Energy (ARPA-E), U.S. Department of Energy, under Award NumberDE-AR0000849, DARPA Award Number HR0011-12-2-0016, RISE Lab sponsor Amazon WebServices, and ADEPT/ASPIRE Lab industrial sponsors and affiliates Intel, HP, Huawei, NVIDIA,and SK Hynix. The views and opinions of authors expressed herein do not necessarily state orreflect those of the United States Government, any agency thereof, or of the industrialsponsors.

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Why build a scalable FPGA-accelerated HW simulator?

Reproducing end-to-end application latency effects from real clusters

1024-Node Datacenter Simulation

Latest Updates

Mapping a simulation to EC2 F1

Example Datacenter Target Design

Rack-scale (32-node) simulation metrics

FireSim Features