verilog through designing real circuits. 3 - verilog... · 1 this and the next lectures are about...

ThisandthenextlecturesareaboutVerilogHDL,which,togetherwithanotherlanguageVHDL,arethemostpopularhardwarelanguagesusedinindustry.

Verilogisonlyatool;thiscourseisaboutdigitalelectronics.Therefore,IwillNOTbegoingthroughVerilogasinaprogrammingcourse- itwouldhavebeenextremelyboringforbothyouandmeifIdid.Instead,youwilllearnaboutVerilogthroughexamples.Iwillthenpointoutvariouslanguagefeaturesalongtheway.WhatitmeansisthatthetreatmentofVerilogisNOTgoingtobesystematic– therewillbelotsoffeaturesyouwon’tknowaboutVerilog.However,youwilllearnenoughtospecifyreasonablysophisticateddigitalcircuits,andyoushouldgainenoughconfidencetolearntherestbyyourself.

TherearemanyusefulonlineresourcesavailableonthedetailsofVerilogsyntaxetc..LookitupasyouneedtoandyouwilllearnhowtodesigndigitalcircuitusingVerilogthroughdesigningrealcircuits.

Theproblemsheetsaremostlyaboutcircuitsandconcepts,withoccasionalVerilogexercises.YouwillbedoinglotsofVerilogcodingduringthefourweeksofLabExperimentinthesecondhalfoftheterm.

Hereisalistoflectureobjectives.Theyareprovidedforyoutoreflectonwhatyouaresupposedtolearn,ratherthananintroductiontothislecture.Iwant,bytheendofthislecture,togiveyousomeideaaboutthebasicstructure andsyntax ofVerilog.IwanttoconvinceyouthatschematiccaptureisNOTagoodwaytodesigndigitalcircuits.Finally,IwantyoutoappreciatehowtouseVerilogtospecifyapieceofhardwareatdifferentlevelsofabstraction.

Youareveryfamiliarwithschematiccapture.HowevermoderndigitaldesignmethodsingeneralDONOTuseschematics.Insteadanengineerwouldspecifythedesignrequirementorthealgorithmtobeimplementedinsomeformofcomputerlanguagespeciallydesignedtodescribehardware.Thesearecalled“HardwareDescriptionLanguages” (HDLs).

ThemostimportantadvantagesofHDLasameansofspecifyingyourdigitaldesignare:1)Youcanmakethedesigntakeonparameters(suchasnumberofbitsinanadder);2)itismucheasiertousecompilationandsynthesistoolswithatextfilethanwithschematic;3)itisverydifficulttoexpressanalgorithmindiagramform,butitisveryeasywithacomputerlanguage;4)youcanusevariousdatapathoperatorssuchas+,*etc.;5)youcaneasilyedit,storeandtransmitatextfile,andmuchhardwarewithaschematicdiagram.

Fordigitaldesigns,schematicisNOTanoption.AlwaysuseHDL.Inthislecture,Iwilldemonstratetoyouwhywithanexample.

IhavechosentouseVerilogHDLasthehardwaredescriptionlanguageforthismodule.VerilogisverysimilartotheClanguage,whichyoushouldalreadyknowfromlastyear.However,youmustalwaysrememberthatYOUAREUSINGITTODESCRIBEHARDWAREANDNOTASACOMPUTERPROGRAMME.

YoucanuseVerilogtodescribeyourdigitalhardwareinthreedifferentlevelofabstraction:1) BehaviouralLevel – youonlydescribehowthehardwareshouldbehavewithoutANYreferencetodigitalhardware.2) Register-Transfer-Level(RTL)– Herethedescriptionassumestheexistenceofregistersandtheseareclockedbyaclocksignal.Thereforedigitaldataistransferredfromoneregistertothenextonsuccessiveclockcycles.Timing(intermsofclockcycles)isthereforeexplicitlydefinedintheVerilogcode.Thisisthelevelofdesignweusemostfrequentlyinthiscourse.3) GateLevel– thisisthelowestleveldescriptionwhereeachgateanditsinterconnectionareexplicitlyspecified.VerilogisnotonlyaspecificationlanguagewhichtellstheCADsystemwhathardwareissupposetodo,italsoincludesacompletesimulationenvironment.AVerilogcompilerdoesmorethanmappingyourcodetohardware,italsocansimulate (orexecute)yourdesigntopredictthebehaviourofyourcircuit.Itisthepredominantlanguageusedforchipdesign.YouwilllearnVerilogthroughexamplesandexercises,notthroughlecture.However,IwillspendjusttwolecturestocoverthebasicsofVerilog.

ThisisaVerilogmodulethatspecifiesa2-to-1multiplexer.ItisrathersimilartoaCfunction(exceptforthemodule keyword).

ItisimportanttorememberthebasicstructureofaVerilogmodule.Thereisamodulename:mux2to1.Thereisalistofinterfaceports:3inputsa,b andsel,and2outputsout andoutbar.Alwaysusemeaningfulnamesforbothmodulenameandvariablenames.

Youmustspecifywhichportisinputandwhichportisoutput,similartothedatatypedeclarationinaCprogramme.

Finally,the2-to-1multiplexingfunctionisspecifiedintheassign statementwithaconstructthatisfoundinC.Thisisabehaviouraldescriptionofthemultiplexer– nogatesareinvolved.

Thelaststatementspecifiestherelationshipbetweenout andoutbar.ItisimportanttorememberthatVerilogdescribesHARDWAREnotinstructioncode.Thetwoassign statementsspecifyhardwarethat“execute” orperformthetwohardwarefunctionsinparallel.Thereforetheirorderdoesnotmatter.

Continuousassignmentspecifiescombinationalcircuits– outputiscontinuouslyreflectingtheoperationsappliedtotheinput,justlikehardware.Rememberthatunlikeaprogramminglanguage,thetwocontinuousassignmentstatementshereAREspecifyinghardwareinPARALLEL,notinseries.HerewealsoseetheconditionalstatementthatisfoundinC.Thismapsperfectlytothefunctionofa2-to-1multiplexerinhardwareandiswidelyusedinVerilog.Furthermore,therearemanyotherBooleanandarithmeticoperatorsdefinedinVerilog(asinC).HereisaquicksummaryofalltheVerilogoperators(usedinanexpression).(Whatis“reductionand&”?Iwantyoutofindthisyourselfonline.)

WhilethepreviousVerilogcodeforthe2-to-1muxonlyspecifies“behaviour”,hereisonethatspecifiesagateimplementationofthesamecircuit.Threetypesofgatesareused:and,or andnot gates.Thereareinternalnets(declaredaswire)whichmustalsobedeclaredandareusedtoconnectgatestogether.

Keywordssuchasand,or andxor arespecial– theyspecifyactuallogicgates.Theyarealsospecialinthatthenumberofinputstotheand-gatecanbe2,3,4,…..Anylength!

NotethatthismoduleusesTWOANDgates,andtheyhavedifferentnames:a1anda2.TheseareTWOseparate instances oftheANDgate.Insoftware,“calling” afunctionsimpleexecutethesamepieceofprogrammecode.Herethetwostatements”anda1(out1,…” and“anda2(out2…” producetwoseparatepieceofhardware.Wesaythateachlineis“instantiating” anANDgate.

Wiringupthegatesisthroughtheuseofportsandwires,anddependsonthepositionsofthese“nets”.Forexample,out1 istheoutputnetoftheANDgatea1,anditisconnectedtotheinputoftheOR gateitbyvirtualofitslocationinthegateportlist.

SofarwehaveusedVeriloginveryhardwarespecificway.“assign” andusinggatespecificationarespecialtoVerilog.YoudonotfindtheseinC.

HereissomethingthatismorelikeC– anditiscalled“proceduralassignment”.Typicallyweusesomethingcalled“always” blocktospecifya“procedure”,i.e.acollectionofsequentialstatementswhicharesandwichedbetweenthebegin-endconstruct.

Thealways blockneedsasensitivitylist– alistofsignalswhich,ifANYofthesesignalschanges,thealways blockwillbeinvoked.Youmayreadthisblockas:

“alwaysatanychangesinnetsa,b orsel,dothebitsbetweenbeginand end”.Actually,ifyouaredefiningacombinationalcircuitmodule,anevenbetterwaytodefinethealwaysblockistouse:

…..always@*....//alwaysatanychangewithanyinputsignal

Insidethebegin-endblock,youareallowedtouseC-likestatements.Inthiscase,weusetheif-elsestatement.Allstatementsinsidethebegin-endblockareexecuted sequentially.

NotethatVerilogkeywordreg doesnotimpliesthatthereisaregistercreatedinthehardware.Itismuchmorelikedeclaringavariablethatholdsavalue.ItisaruleinVerilogthatifyouperformanassignmenttoavariableINSIDEanalwaysblock,thatvariableMUSTbedeclaredreg,andNOTanet(wire).ThisisoneofthefewpeculiaritiesofVerilogthatcanbeconfusingtostudents.

ThisslideshowshowtheproceduralstatementismappedtothebasicMUXcircuit.ThecontinuousassignmentstatementcorrespondstotheNOTgate.

ThisisyetanotherwaytospecifytheMUXcircuit.Itisstillaproceduralassignmentwiththealways block.However,wereplacetheif-elsestatementwitha“case”statement.Thecasevariableissel.Sincesel isa1-bitsignal(ornet),itcanonlytakeon0or1.

Notethatthevariouscasevaluescanbeexpressedindifferentnumberformatsasshownintheslide.Forexample,consider2’b10.The2isthenumberofbitsinthisnumber.‘bmeansitisspecifiedinbinaryformat.Thevalueofthisnumberis10 inbinary.

Thisslidedemonstrateswhylanguagespecificationofhardwareissomuchbetterthanschematicdiagram.Bysimplydeclaringthesignalsasamulti-bitbus(8bits[7:0]),wechangethismoduletoonethatspecifies8separate2-to-1multiplexers.

Anotherusefulwaytospecifyabusisusingtheconcatenationoperator:{….}asshownabove.

Theconcatenationoperatorisparticularlyusefulinconvertingdigitalsignalsfromonewordlength(i.e.numberofbitsinaword)toanother.Forexample,toconvertan8-bitunsignednumbera[7:0]toa13-bitunsignednumberb[12:0],youcansimpledothis:

assign b[12:0] = {5’b0, a[7:0]};

Hereisasimpleexample:thedesign ofa4-bithexcodeto7segmentdecoder.Youcanexpressthefunctionofthis7-segmentdecoderinthreeforms:1)asatruthtable(notethatthesegmentsarelowactive);2)as7separateK-maps(shownhereisforout[6] segmentonly);3)asBooleanequations.ThisisprobablythelasttimeyouseeK-maps.Inpracticaldigitaldesign,youwouldrelyheavilyonCADtools.Inwhichcase,logicsimplificationsaredoneforyouautomatically– youneverneedtouseK-mapstodoBooleansimplificationmanually!

Hereisatediousimplementationintheformofschematicdiagramofthe7segmentdecoderasinterconnectedgates.Veryhardtodoandverypronetoerrors.

OnecouldtakeagroupofgatesandspecifythegatesinVeriloggateprimitivessuchasand,or etc.Stillverytedious.Hereistheimplementationfortheout[6] output.

Insteadofspecifyingeachgateseparately,hereisusingcontinuousassignmentstatement,mappingtheBooleanequationdirectiontoasingleVerilogstatement.Thisisbetter.

Hereisthecompletespecificationofthehex_to_7segmoduleusingcontinuousassignment statements.ItshowshowoneshouldwriteVerilogcodewithgoodcommentsandcleardocumentationofinputandoutputports.

Finallythe4th methodisthebest.Weusethecase constructtospecifythebehaviourofthedecoder.Hereonedirectlymapsthetruthtabletothecasestatement – easyandelegant.

Insteadofusing:always@(in),youcouldalsousealways@*

HowisaVerilogdescriptionofahardwaremoduleturnedintoFPGAconfiguration?ThisflowdiagramshowsthevariousstepstakeninsidetheQuartusPrimeCADsystem.

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