analog-to-digital converter
DESCRIPTION
Analog-to-Digital Converter. Chapter 9 MC9S12DP256. Method of Successive Approximation. Implementing Successive Approximation. \ 9S12DP256 Analog-to-Digital Converter -- File: ATD256.WHP HEX 0082 CONSTANT ATD0CTL2 \ ATD Control Register 2 - PowerPoint PPT PresentationTRANSCRIPT
Analog-to-Digital Converter
Chapter 9
MC9S12DP256
Method of Successive Approximation
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 00000V
5V
2.5V
3.75V
3.125V3.4375V Vin = 3.5V
step 1 step 2 step 3 step 4
voltage
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 00000V
5V
2.5V
3.75V
3.125V3.4375V Vin = 3.5V
step 1 step 2 step 3 step 4
voltage
Control
D/A Converter
V
V
in
DA
Binary OutputC+
-
Implementing Successive Approximation
Table 9.2 A/D Converter Registers in the 9S12DP256 Name Register Addr Description
ATD0CTL2 0082 ATD Control Register 2 ATD0CTL3 0083 ATD Control Register 3 ATD0CTL4 0084 ATD Control Register 4 ATD0CTL5 0085 ATD Control Register 5 ATD0STAT 0086 ATD Status Register (H) ATD0STATL 0087 ATD Status Register (L) ADR00H 0090 A/D Result Register 0 ADR01H 0092 A/D Result Register 1 ADR02H 0094 A/D Result Register 2 ADR03H 0096 A/D Result Register 3 ADR04H 0098 A/D Result Register 4 ADR05H 009A A/D Result Register 5 ADR06H 009C A/D Result Register 6 ADR07H 009E A/D Result Register 7
Table 9.2A A/D Converter Registers in the 9S12DP256 Name Register Addr Description
ATD1CTL2 0122 ATD Control Register 2 ATD1CTL3 0123 ATD Control Register 3 ATD1CTL4 0124 ATD Control Register 4 ATD1CTL5 0125 ATD Control Register 5 ATD1STAT 0126 ATD Status Register (H) ATD1STATL 0127 ATD Status Register (L) ADR10H 0130 A/D Result Register 0 ADR11H 0132 A/D Result Register 1 ADR12H 0134 A/D Result Register 2 ADR13H 0136 A/D Result Register 3 ADR14H 0138 A/D Result Register 4 ADR15H 013A A/D Result Register 5 ADR16H 013C A/D Result Register 6 ADR17H 013E A/D Result Register 7
\ 9S12DP256 Analog-to-Digital Converter -- File: ATD256.WHPHEX 0082 CONSTANT ATD0CTL2 \ ATD Control Register 20084 CONSTANT ATD0CTL4 \ ATD Control Register 40085 CONSTANT ATD0CTL5 \ ATD Control Register 50086 CONSTANT ATD0STAT \ ATD Status Register 0090 CONSTANT ADR00H \ A/D Result Register 0 : ADCONV.ON ( -- )
85 ATD0CTL4 C! \ 8-bit resol, /8 clockC0 ATD0CTL2 C! ; \ Set ADPU and AFFC
: ADCONV.OFF ( -- )
0 ATDCTL2 C! ; \ Clear ADPU : WAIT.FOR.CONV ( -- )
BEGIN 7 ATD0STAT ?HIUNTIL ;
: AVG4 ( -- n ) \ Average 4 values in ADR0 - ADR3
0 ADR00H 2-4 FOR \ sum addr DUP R@ 2* + C@ \ sum addr val ROT + SWAP \ sum addr NEXTDROP 4 / ;
: ADCONV ( ch# -- val ) \ Avg 4 readings from channel ch#
ADCONV.ON8 MOD 80 OR ATDCTL5 C! \ ch# < 8; SCAN=0 MULT=0 WAIT.FOR.CONVAVG4 ADCONV.OFF ;
: GET.4VALUES ( -- val4 val3 val2 val1 ) \ read 4 a/d regs
ADR0H 2-4 FOR \ addr1 DUP R@ 2* + C@ SWAP \ valn addr1 NEXTDROP ;
: ADCONV03 ( -- val3 val2 val1 val0 ) \ Convert 1st 4 channels
ADCONV.ON10 ATDCTL5 C! WAIT.FOR.CONVGET.4VALUES ;
: ADCONV47 ( -- val3 val2 val1 val0 ) \ Convert 2nd 4 channels
ADCONV.ON14 ATDCTL5 C! WAIT.FOR.CONVGET.4VALUES ;
DECIMAL