ancillary detectors working group agata week/gsi, 23 feb. 2005 integration of ancillaries with daq...
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Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Integration of ancillaries with DAQ
• Goal• Context• Specifications, modes• Design• Schedule & cost
Ch. Theisen for the [email protected]
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Goal
Integration of ancillary detectors electronics with Agata
Provide an interface
As many ancillary detectors as possible !
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
ContextWhen: for the demonstrator phase (2007)
Where: Ganil, GSI, JYFL, Köln, LNL
Who: Existing and/or identified ancillariesADWG meeting 22/06/2004LUSIA, FRS, RFD, Neutron Wall, CUP,
VAMOS, PRISMA, GREAT,…, γ arrays
List to finalize a.s.a.p…
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Ge-Cluster
CATE
Primary Beam
~500 A MeV
Production target
Dipole
SCISCI
MW
DegraderMusic
HECTOR Reaction Target
ToFToF
A/q=(B).e/c.u
S4 AREA
Ge-Cluster
CATE
Primary Beam
~500 A MeV
Production target
Dipole
SCISCI
MW
DegraderMusic
HECTOR Reaction Target
ToFToF
A/q=(B).e/c.u
Production target
Dipole
SCISCI
MW
DegraderMusic
HECTOR Reaction Target
ToFToF
A/q=(B).e/c.u
S4 AREA
LUSIA
FRS
RFD Neutron Wall
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
CUP
VAMOS
PRISMA RITU/GREAT
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Specifications
Correlate ancillaries with Agata(event number and/or clock counter)
Event filteringKeep relevant Agata and ancillary det. events• “Slow-down” Agata• Reduce ancillary det. dead-time
Interaction with AGATA GTS
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
How– LUSIA VME– FRS VME– RFD VME– Neutron Wall VME– CUP VME– VAMOS VME– PRISMA VME– GREAT VME – γ arrays VME
VME INTERFACE
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Interface with GTS
GTSAncillary
Trigger Request
Val/Rej, Clock
Val/Rej : combination of ancillary/Agata :“master”, “slave”, “mixed” modes
Latency times NOT A TRIGGER MODULE !
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Latency times
Val/Rej : latency > 7μs
Too late for most converters Dead time ! Need prompt pre-trigger Request to ADP : Agata prompt signal
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Global scheme
Ancillary Front-end
Ancillary Readout
VME interface
TriggerRequest
Val/RejClock counterEvent Number
GTS supervisor
Agata Merge/Ancillary post-merge
Agataflow
Agata promptsignal
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Three modes
• “Slow” conversion mode (common dead time)
• “Fast” conversion mode (parallel-like)• Trigger-less (TDR)
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Slow conversion modeTrigger_Request
Local_Trigger
Local_Trigger_Tag
Busy
ADC conversion
Validation_Rejection_Tag
Interface VME Cycle
Event_Number
TR
LT
TAG
Busy
Val/Rej
Val/Rej TAG
Trigger_Validation orTrigger_Reject
Only if trigger validated
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Busy2
“Fast” conversion mode”: parallel like
Trigger_Request
Local_Trigger
Local_Trigger_Tag
Busy
ADC conversion
Validation_Rejection_Tag
Interface VME Cycle
Event_Number
TR1
LT1
TAG1
Busy1
Val/Rej1
Val/Rej TAG1
TAG2
LT2
TR2
Val/Rej2
Val/Rej TAG2
Trigger_Validation orTrigger_Reject
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
TDR (JYFL) mode
• Correlated data (DSSD, Gas) : Trigger request• Uncorrelated data (Tunnel, Focal plane Ge…)
No events: only data Time Stamping
Clock countercorrelation !
TDRclock
counter
GTSclock
counter
Embedded TDR data source
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Design: layout
Mezzanine
FPGA
Optical fiber
Ethernet
I/OJtag Bus
Backplane
memory
Ethernet
Shark
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
VIRTEX - II
PROXC2V7 FF672
(396 I/O)
VIRTEX - II
PROXC2V7 FF672
(396 I/O)
BANK_4
BANK_1 BANK_0
BA
NK
_6B
AN
K_7
BANK_5
BA
NK
_3B
AN
K_2 .
CR_CON1CR_CON1
CR_CON2CR_CON2 GTS_JTAG
LSA_Trace_GTS CPU_TraceGTS
LSA_Trace_VME CPU_TraceVME
P1_VMEP2_VME
Data Bus – [32]
Address Bus - [31]
Address Modifier – [6]
Adr_, Data_Str – [3]
LWORD, WRITE – [2]
DTACK, BERR – [2]
IRQ – [4]
IACK,IN,OUT –[3]
SYSRESET – [1]
VXI -- [36] ? [3]
TOTAL: [120]
Front Panel
Drive/Conv
FRONTTrigger RequestLocal TriggerVetoRejectValidateBackpreasureLEDsCCLK [2]Inspection [4]ESTIMATE [20]
SDRAM
Ethernet
POWER
Shark-link [7]
Metronome [4]
Trigger_Req [1]
Local_Trigger – [1]
Trigger_Val/_Rej – [2]
Local_Trig_Tag – [8]
Clock_deskew – [6]
GTS_Clock – [2]
Val/Rej_Tag – [8]
LLP_Status – [8]
GTS_Status – [8]
MSG_Out(Str) – [8(+1)]
FPGA_Progr – [6]
TOTAL: [75]
LSA_Trace - [36]
CPU_Trace – [16]
Clock_IN – [2]
Bcast_in(Str) – [8(+1)]
TOTAL: [73]
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Schedule
Main task: Krakow+ Ganil (tests, real time soft.), Padova (GTS), Daresbury (TDR)
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Cost
• 2 prototypes : 6 k€• Production : 2.5 k€ /cards *6 = 15 k€• Prototypes + Production = 21 k€• + GTS Mezzanines 2.3 k€/board
Total = 34.8 k€ with 6 mezzanines = 29.4 k€ with 4 mezzanines
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Common dead-time vs. Agata
Losses !Ancillary:Common dead-time
Agata:Full
parallel
Future (post-demonstrator): switch to parallel read-out
Ancillary Detectors Working GroupAgata Week/GSI, 23 Feb. 2005
Conclusions
• Preliminary specifications ready
• We need feedback; contact us !
• Mailing list: please register !
• Web site ( GSI official site)