ant20 - ber tester setup

10
Case Study Page 1 of 10 ANT 20 – BER tester setup MOHD AMEEN DIMITY ([email protected]) Optical Network Product Department. Figure 1 EMS ODU1 IDU NE1 ODU2 ODU3 ODU4 NE2 IDU Space attenuation Space attenuation BER tester (ANT20) 1. Connect the test circuit as shown in Figure 1 2. Configure services as required by test environment. For SDH, create cross connect as shown in Figure 2. Make the hardware loopback at far end using LC-LC cable at the SDH port on SLI board.

Upload: khalid-anjum

Post on 31-Mar-2015

163 views

Category:

Documents


3 download

TRANSCRIPT

Page 1: ANT20 - BER tester setup

Case Study

Page 1 of 10

ANT 20 – BER tester setup MOHD AMEEN DIMITY ([email protected])

Optical Network Product Department.

Figure 1

EMS

ODU1

IDU NE1

ODU2

ODU3

ODU4

NE2

IDU

Space attenuation

Space attenuation

BER tester (ANT20)

1. Connect the test circuit as shown in Figure 1 2. Configure services as required by test environment. For SDH, create cross connect as shown in Figure 2. Make the hardware loopback at far end using LC-LC cable at the SDH port on SLI board.

Page 2: ANT20 - BER tester setup

Case Study

Page 2 of 10

Figure 2

While for PDH, create cross-connect as shown in Figure 3. Make the hardware loopback at NE 2 (using BNC male jumper cable in that case) at desired port at E1 panel

Figure 3

Page 3: ANT20 - BER tester setup

Case Study

Page 3 of 10

RX

TX

TXRX

RX

TX

Figure 4 3. Connect the Tx port of Ant 20 to Rx port of E1 interface as shown in Figure 4 at NE1.

Note that normally for PDH we use the copper cable while SDH we use the fiber cable.

Figure 5

4. Click the Ant-20 icon on the desktop (Figure 5)

Page 4: ANT20 - BER tester setup

Case Study

Page 4 of 10

Figure 6

5. There are 3 instruments to be selected normally from the list as follows (Figure 6) :-

Signal structure Performance Analysis Anomaly / Defect Analyzer

Figure 7

6. Refer to Figure 7 at Signal structure window, click to Signal Structure>Edit to setup for either SDH or PDH.

Page 5: ANT20 - BER tester setup

Case Study

Page 5 of 10

Figure 8

7. Figure 8 shows the setup for PDH signal structure. Click the button from left to right. Edit : ITU-T Mode : Normal Interface : Electrical PDH : 2M PDH mode : Unfrm. Test Pattern : PRBS15 After click this entire buttons, don’t forget to click Tx Rx button to ensure the same signal go through the system and come back.

Page 6: ANT20 - BER tester setup

Case Study

Page 6 of 10

Figure 9

To run the test for 15 minutes, at ANT-20 windows click to Measurement>Setting and set the time to 15 minutes (Figure 9)

Page 7: ANT20 - BER tester setup

Case Study

Page 7 of 10

Change to PRBS23

Figure 10

8. Figure 10 shows the setup for SDH signal structure. Edit : ITU-T Mode : Normal Interface : Optical SDH : STM 1 and AU4 Mapping : VC12 PDH : 2M PDH mode : Unfrm. Test Pattern : PRBS23 After click this entire buttons, don’t forget to click Tx Rx button to ensure the same signal go through the system and come back.

Page 8: ANT20 - BER tester setup

Case Study

Page 8 of 10

From Figure 11, we can see the difference from PDH setup.

Figure 11

9. Then, perform the BER test for 24 hours. Observe the result for a moment before

leave the test gear running a day. Make sure that the EFS (Error Free Seconds) are counting every seconds as Figure 12 and the others are not counting.

Figure 12

Page 9: ANT20 - BER tester setup

Case Study

Page 9 of 10

10. After a day, if no bit error generated, the EFS = 86400 (24hr x 60 min x 60 sec), and the tester stops automatically. Then, go to the tool bar click to Print… to print the result by using a floppy disc.

Page 10: ANT20 - BER tester setup

Case Study

Page 10 of 10

10. Here is the example of Passed testing result.

ANT-20 - Performance Analysis 1

Start of measurement: 06/23/08 15:40:18.0

End of measurement : 06/24/08 15:40:18.0

Allocation: 18.50000 %

SES Threshold: 2400 B/s

UAS Limit: 0

G.826: OOS;NEAR END: TSE;

EB;0;;

BBE;0;0.00000 %;

ES;0;0.00000 %;

EFS;86400;100.00000 %;

SES;0;0.00000 %;

UAS;0;;

VERDICT;Accepted;;

PATH ALLOCATION;18.50000 %;;

PATH UAS;0;;