Designing an ATCACompliant M-LVDS ClockDistribution Network

National SemiconductorApplication Note 1503Davor GlisicNovember 20, 2007

1.0 IntroductionMany telecommunication systems including those designedbased on the Advanced Telecommunications Computing Ar-chitecture (ATCA)specifications require synchronization oftheir internal interfaces and the external networks. To enableimplementation of such systems the ATCA or PICMG 3.0specification defines a synchronization clock interface in thearchitecture. Per this specification, the task of sourcing clocksignals has been assigned to integrated circuits (ICs) con-forming to TIA/EIA-899 (Multipoint Low Voltage DifferentialSignaling or M-LVDS) standard.

This application note provides a guide to designing ATCAcompliant clock distribution networks using M-LVDS devicesfrom National Semiconductor. The guide consists of a quickdescription of an ATCA synchronization clock interface, anoverview of M-LVDS standard, an extensive discussion onperformance of National Semiconductor M-LVDS devices inan ATCA backplane and a set of design recommendationsand rules that will assist you in building a bullet proof clockdistribution network.

2.0 Synchronization Clock Interface

in an ATCA BackplaneIn an AdvancedTCA backplane (Figure 1), there are threeconnector zones:

• Zone 1 for Power Connection and Shelf management

• Zone 2 for Data Transport Interfaces

• Zone 3 for User-defined I/O Interconnect

The Data Transport Interfaces are Base Interface, Fabric In-terface, Update Channel Interface, and SynchronizationClock Interface. These interfaces provide connectivity be-tween up to 16 slots. As Figure 1 illustrates, each slot canhave up to 5 Advanced Differential Fabric (ADF) or zone 2connectors. Examples of the ADF connectors are Tyco HM-Zd and ERNI ERmetZD.

20198601

FIGURE 1. Location of Clock Pins in an ATCA Backplane

© 2007 National Semiconductor Corporation 201986 www.national.com

Desig

nin

g a

n A

TC

A C

om

plia

nt M

-LV

DS

Clo

ck D

istrib

utio

n N

etw

ork

AN

-1503

The clock synchronization interface enables exchange of tim-ing information between all slots in the backplane. It consistsof 3 pairs of redundant clock busses: CLK1A, CLK1B, CLK2A,CLK2B, CLK3A and CLK3B. The PICMG 3.0 specificationdefines usage, frequency, and quality of each clock group:

• CLK1A and CLK1B are for redundant 8 kHz standarddigital telephony transmission system clocks.

• CLK2A and CLK2B are for 19.44 MHz clocks forsynchronization of the SONET/SDH networks.

• CLK3A and CLK3B are for user-defined signals (clock ordata).

The first two rows of pins of each P20 ADF connector connectto the 6 clock busses. The busses are essentially 130-ohmdifferential PCB traces terminated with 80-ohm resistors onboth sides. Figure 2 shows how M-LVDS drivers and re-ceivers create a multipoint clock distribution network whenthree or more line cards are installed in the backplane.

20198602

FIGURE 2. M-LVDS Drivers / Receivers Connect to Clock Busses

www.national.com 2

AN

-1503

3.0 M-LVDS OverviewThe multipoint low voltage differential signaling, or M-LVDS(TIA/EIA-899) standard specifies the electrical characteristicsof line drivers and receivers intended for general data trans-port within a multipoint bus where up to 32 nodes may beconnected. More specifically, it defines driver output charac-teristics, and input characteristics of two receiver types.

Per TIA/EIA-899 standard, a M-LVDS driver generates a dif-ferential signal with a 480 – 650 mV amplitude and an offsetwithin the 0.3 –2.1 V range. The signal must have 10% - 90%transition times (rise and fall) of 1 ns or greater and up to onehalf of a unit interval (tUI) to alleviate the effects of stubs thatare the “artifacts” of multipoint architectures. Table 1 summa-rizes key characteristics of LVDS (popular interface for pointto point topologies) and M-LVDS drivers:

The key M-LVDS receiver specifications are input voltagethreshold and input common mode range. The input thresholdlevels differentiate the two types of M-LVDS receivers as il-lustrated in Figure 3. Type 1 receivers have threshold levelscentered at 0 V and provide higher noise margin than type 2receivers. Type 2 receivers have lower positive noise marginbut provide fail-safe provisions for control signals (See Figure5 and Figure 6).

The receiver input common mode range of –1.4 to 3.8 Vmakes M-LVDS a robust interface for connecting sub-sys-tems that may have potential difference between their groundreferences of up to ±1 volts.

TABLE 1. Comparison of Key Driver Parameters

Parameter LVDS M-LVDS

VOD [mV] 250 - 450 480 - 650

VOS [V] 1.125 0.3 - 2.1

IOD [mA] 2.5 - 4.5 9 - 13

IOS [mA] < 24 < 43

tRISE / tFALL Min [ns] N / A 1

tRISE / tFALL Max [s] 0.3 tUI 0.5 tUI

20198603

FIGURE 3. M-LVDS Standard Defines Two Receiver Types

3 www.national.com

AN

-1503

4.0 M-LVDS Performance in an

ATCA BackplaneCurrently, National Semiconductor’s family of M-LVDS de-vices consists of four single channel devices:

• DS91D176 – A Half Duplex with Type 1 M-LVDS Inputs

• DS91C176 – A Half Duplex with Type 2 M-LVDS Inputs

• DS91D180 – A Full Duplex with Type 1 M-LVDS Inputs

• DS91C180 – A Full Duplex with Type 2 M-LVDS Inputs

This section of the application note reports on the perfor-mance of the DS91D176, a representative of the family, in anAdvancedTCA backplane. The following subsections de-scribe setup, experiment method and findings in detail.

4.1 SETUP DESCRIPTION

A 14-slot dual-star AdvancedTCA compliant backplane de-veloped by ELMA Bustronic (www.bustronic.com) and four-teen line cards (P/N: DS91D176EVK) developed by NationalSemiconductor enabled testing of various multi-point clock

distribution networks. Each line card features six DS91D176devices whose M-LVDS I/O pins connect to an ADF connec-tor. By installing the line card in the backplane, each of the sixdevices on the card connects to each of the six clock busseson the backplane. Installation of all fourteen line cards createssix multi-drop networks. Each line card can be setup as adriver card (all six devices configured as M-LVDS drivers) ora receiver card (all six devices on the card configured as M-LVDS receivers). Figure 4 shows a picture of the backplanefully loaded with the M-LVDS line cards.

On the M-LVDS line card, the un-terminated short PCB tracks(stubs) that connect M-LVDS I/O pins to the bus have differentgeometries for each device. The stub lengths range from 0.25to 2 inches (1 inch ≈ 2.54 cm) and differential stubimpedances range from 80 to 130 ohms. Table 2 shows char-acteristics of the stubs found on the line card

For the M-LVDS line card schematic files, gerbers, boardstack up and other information about the line card check itslatest user manual at lvds.national.com.

20198604

FIGURE 4. 14-Slot ATCA Backplane Fully Loaded with M-LVDS Line Cards

TABLE 2. M-LVDS Line Card Stub Characteristics and Pin Mapping

Device M-LVDS Pins ADF Connector Pins Stub Length Stub Diff. Impedance

U1 A1, B1 B1, A1 0.25" 100 ohms

U2 A2, B2 D1, C1 0.50" 100 ohms

U3 A3, B3 F1, E1 1.00" 130 ohms

U4 A4, B4 H1, G1 1.00" 100 ohms

U5 A5, B5 D2, C2 1.00" 80 ohms

U6 A6, B6 B2, B1 2.00" 100 ohms

www.national.com 4

AN

-1503

4.2 EXPERIMENT METHOD

When it comes to performance of M-LVDS clock distributionnetworks, it is mainly the noise margin that differentiates agood design from one that is marginal. Stubs are the majordetriment to noise margin in a multi-drop environment. Theyreduce noise margin in two ways: first, stubs load the bus andas a result reduce the amplitude of the driver output signal.

Second, stubs create impedance discontinuities that causereflections and, as a result, further reduce available noisemargin.

In this experiment, evaluation method consists of looking atthe available noise margin (Figure 5 and Figure 6) at the inputof each receiver and examining effects of clock driver positionand stub characteristics on the noise margin.

20198605

FIGURE 5. Available Noise Margin to a Type 1 Receiver

20198615

FIGURE 6. Available Noise Margin to a Type 2 Receiver

5 www.national.com

AN

-1503

4.3 EXPERIMENT FINDINGS

Extensive experimentation with various multi-drop configura-tions, stub lengths, stub impedances and frequencies has ledto the following set of conclusions:

• Noise margin on the receivers’ inputs is higher if thelocation of the driver card is closer to one of the terminationresistors. In other words, the first and the last slot in abackplane are the best driver card locations; slots in themiddle are the worst.

• Noise margin is the lowest for the receivers in the slotadjacent to the slot with the driver card; it is the highest forthe receivers on the furthest card. Table 3 shows availablenoise margin for the receivers in the slot adjacent to andfurthest from the slot with the driver card. The backplaneis fully loaded and the clock frequency is 19.44 MHz.

• Noise margin is higher with shorter and narrower stubs.Once a stub starts to behave as an un-terminatedtransmission line, at the point where it connects to the bus,it lowers the impedance of that section of the bus. Theseimpedance variations or discontinuities along the buscause reflections that lower noise margin. Figure 7 showseffects of the stub length on the available noise margin forthe receivers in slot #8 while the driver card is in slot #7and driving a 19.44 MHz clock to all thirteen receivercards.In Figure 7, the four waveforms are measured at the inputof the adjacent receivers from the four networks with 0.25-,

0.5-, 1- and 2-inch stubs. It is clear that the receiver fromthe network with 2-inch stubs has the lowest noise margin.Table 4 presents measured noise margin for the receiversin the slot #8 while the driver card is in the slot #7 anddriving clock signals to all thirteen receiver cards at somecommon frequencies. As data in Table 4 indicates, theworst noise margin for the given configuration is when theclock signals have a frequency around 60 MHz. At 100MHz, the maximum frequency allowed for AdvancedTCAsystems, signals have the most attenuation and becomesine-wave shaped waveforms without any majorreflections at the receiver. As a result, noise margin is thehighest at that frequency.Figure 8 shows effects of the stub impedance on theavailable noise margin for the receivers in slot #8 when thedriver card is in slot #7 and drives a 19.44 MHz clock to allthirteen receiver cards.In Figure 8, the three waveforms are measured at the inputof the adjacent receivers from the three networks with 80-,100- and 130-ohm stubs. The receiver from the networkwith 130-ohm stubs has the highest noise margin. Table5 presents measured noise margin for the receivers in slot#8 when the driver card is in slot #7 and drives clocksignals to all thirteen receiver cards at some commonfrequencies.

TABLE 3. Noise Margin Depends on Driver and Receiver Cards Locations and Stub Length

Driver Location Receiver Location Available Noise Margin [mV]

0.25" Stubs 0.50" Stubs 1.00" Stubs 2.00" Stubs

Slot #1 Slot #2 350 310 230 230

Slot #1 Slot #14 >350 >350 >350 >350

Slot #7 Slot #8 230 230 150 70

Slot #7 Slot #14 310 310 230 230

TABLE 4. Noise Margin is Higher with Shorter Stubs

Frequency

[MHz]

Driver Location Receiver

Location

Available Noise Margin [mV]

0.25" Stubs 0.50" Stubs 1.00" Stubs 2.00" Stubs

19.44 Slot #7 Slot #8 230 230 150 70

30.72 Slot #7 Slot #8 230 230 115 105

61.44 Slot #7 Slot #8 180 160 140 0

100.0 Slot #7 Slot #8 >350 >350 >350 >350

TABLE 5. Higher Impedance Stubs Have a Lesser Impact on Noise Margin

Frequency [MHz] Driver Location Receiver Location Available Noise Margin [mV]

80 ohm Stubs 100 ohm Stubs 130 ohm Stubs

19.44 Slot #7 Slot #8 130 150 170

30.72 Slot #7 Slot #8 105 115 130

61.44 Slot #7 Slot #8 130 140 160

100.0 Slot #7 Slot #8 >350 >350 >350

www.national.com 6

AN

-1503

20198606

FIGURE 7. Noise Margin is Higher with Shorter Stubs

20198607

FIGURE 8. Higher Impedance Stubs Have a Lesser Impact on Noise Margin

5.0 Designing an M-LVDS Clock

Distribution Network - Tips and

TricksDesigning an ATCA compliant M-LVDS clock distribution net-work is a not as straightforward a task as it may appear if one

only relies on the recommendations given in the PCIMG 3.0standard. The following set of design recommendations andtips derived from experimentation with an ATCA compliantbackplane and M-LVDS products from National Semiconduc-tor will help you to build a reliable clock distribution networkwith the highest noise margin possible.

7 www.national.com

AN

-1503

• Select M-LVDS drivers with the slowest transition time thatwill satisfy the bandwidth requirements of your clocksystem. TIA/EIA-899 standard specifies 1 ns as theminimum transition time for output of an M-LVDS driver.In an ATCA backplane with 1-inch stubs, 1 ns transitiontime is too fast for certain configurations. M-LVDS driversfrom National Semiconductor have typical 10%-90%transition times of 1.7 ns and can operate at frequenciesof up to 100 MHz.

• Place your clock drivers on line cards located in slotscloser to the ends of the backplane provided other systemrequirements allow it. This arrangement creates longersignal paths. The longer signal paths are lossier and laydown the signal edges. Again, slower transition times aremore “forgiving” when they encounter impedancediscontinuities.

• Minimize the stub length as much as possible. The PCIMG3.0 specifies 1 inch (excluding the ADF connector) as the

maximum stub length for M-LVDS devices. Anythinglonger than that may cause your system to fail. Shorteningthe stubs from 1 inch to ½ inch may increase your noisemargin by 50%.

• When noise margin is at a premium, one should considermaximizing the stub impedance. This can beaccomplished by either increasing the dielectric thicknessbetween the stub and the copper plane(s) or by makingthe stubs as narrow as PCB manufacturers can make it (inaddition to minimizing the stub length) or both.

• Any power supply noise can reduce available noisemargin. Ensure that M-LVDS devices are properlydecoupled. Use two vias for VDD and GND pins and placedecoupling capacitors close to the device VDD pin. Figure9 shows how to place decoupling capacitors and connectDS91D176 to the power and ground planes.

20198608

FIGURE 9. Decoupling DS91D176

6.0 ConclusionShort, narrow stubs coupled with signal drivers (i.e. M-LVDSline drivers) that have controlled output edge-rates are the keyto increased noise margin and improved overall performanceof any multipoint network including M-LVDS clock distributionnetworks in ATCA backplanes. By keeping this in mind andfollowing PCB design recommendations given in this note,reliable clock distribution networks can be designed withease.

7.0 References

1. DS91D176/DS91C176 Data Sheet, NationalSemiconductor. April 2006

2. PICMG 3.0 Revision 2.0, ATCA Base Specification.March 18, 2000

3. TIA/EIA-899-A, Electrical Characteristics of MultipointLow Voltage Differential Signaling (M-LVDS) InterfaceCircuits, Telecommunications Industry Association.March 2002

4. TIA/EIA-644-A, Electrical Characteristics of Low VoltageDifferential Signaling (LVDS) Interface Circuits,Telecommunications Industry Association. February2001

www.national.com 8

AN

-1503

Notes

9 www.national.com

AN

-1503

NotesA

N-1

503

Desig

nin

g a

n A

TC

A C

om

plian

t M

-LV

DS

Clo

ck D

istr

ibu

tio

n N

etw

ork

For more National Semiconductor product information and proven design tools, visit the following Web sites at:

Products Design Support

Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench

Audio www.national.com/audio Analog University www.national.com/AU

Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes

Data Converters www.national.com/adc Distributors www.national.com/contacts

Displays www.national.com/displays Green Compliance www.national.com/quality/green

Ethernet www.national.com/ethernet Packaging www.national.com/packaging

Interface www.national.com/interface Quality and Reliability www.national.com/quality

LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns

Power Management www.national.com/power Feedback www.national.com/feedback

Switching Regulators www.national.com/switchers

LDOs www.national.com/ldo

LED Lighting www.national.com/led

PowerWise www.national.com/powerwise

Serial Digital Interface (SDI) www.national.com/sdi

Temperature Sensors www.national.com/tempsensors

Wireless (PLL/VCO) www.national.com/wireless

THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACYOR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TOSPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THISDOCUMENT.

TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORTNATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALLPARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FORAPPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS ANDAPPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDENATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.

EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NOLIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALEAND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULARPURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTYRIGHT.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES ORSYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life andwhose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expectedto result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to performcan be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All otherbrand or product names may be trademarks or registered trademarks of their respective holders.

Copyright© 2007 National Semiconductor Corporation

For the most current product information visit us at www.national.com

National SemiconductorAmericas CustomerSupport CenterEmail:new.feedback@nsc.comTel: 1-800-272-9959

National Semiconductor EuropeCustomer Support CenterFax: +49 (0) 180-530-85-86Email: europe.support@nsc.comDeutsch Tel: +49 (0) 69 9508 6208English Tel: +49 (0) 870 24 0 2171Français Tel: +33 (0) 1 41 91 8790

National Semiconductor AsiaPacific Customer Support CenterEmail: ap.support@nsc.com

National Semiconductor JapanCustomer Support CenterFax: 81-3-5639-7507Email: jpn.feedback@nsc.comTel: 81-3-5639-7560

www.national.com

Designing an ATCA Compliant M-LVDS Clock Distribution Network1.0 Introduction2.0 Synchronization Clock Interface in an ATCA BackplaneFIGURE 1. Location of Clock Pins in an ATCA BackplaneFIGURE 2. M-LVDS Drivers / Receivers Connect to Clock Busses

3.0 M-LVDS OverviewTABLE 1. Comparison of Key Driver ParametersFIGURE 3. M-LVDS Standard Defines Two Receiver Types

4.0 M-LVDS Performance in an ATCA Backplane4.1 SETUP DESCRIPTIONFIGURE 4. 14-Slot ATCA Backplane Fully Loaded with M-LVDS Line CardsTABLE 2. M-LVDS Line Card Stub Characteristics and Pin Mapping

4.2 EXPERIMENT METHODFIGURE 5. Available Noise Margin to a Type 1 ReceiverFIGURE 6. Available Noise Margin to a Type 2 Receiver

4.3 EXPERIMENT FINDINGSTABLE 3. Noise Margin Depends on Driver and Receiver Cards Locations and Stub LengthTABLE 4. Noise Margin is Higher with Shorter StubsTABLE 5. Higher Impedance Stubs Have a Lesser Impact on Noise MarginFIGURE 7. Noise Margin is Higher with Shorter StubsFIGURE 8. Higher Impedance Stubs Have a Lesser Impact on Noise Margin

5.0 Designing an M-LVDS Clock Distribution Network - Tips and TricksFIGURE 9. Decoupling DS91D176

6.0 Conclusion7.0 References