RECONFIGURATION BASED VLSI DESIGN FOR SECURITY

RECONFIGURATION BASED VLSI DESIGN FOR SECURITYSubmitted By,ASHA SATHEESCONTENTSINTRODUCTION.

VLSI ENCRIPTION/LOCKING & UNLOCKING.

RECONFIGURATION BASED VLSI DESIGN FOR SECURITY.

LEON2 PROCESSOR

CONCLUSION

INTRODUCTIONA critical challenge for nanoelectronic system is to achieve yield and reliability.Reconfiguration and reconfigurable computing.Hardware root of trust of any security system.Nowadays s/w based security solution changed to h/w based.Such systems ranges from smart cards to specialized secure co-processing boxes.Hardware security threats- information leakage.Recently released comprehensive national cyber security initiative has identified SUPPLY CHAIN RISK MAGEMENT PROBLEM as a top national priority Reconfigurable computing technologies.Supply chain risk attack model.VLSI encryption/locking.Combinational logic locking.Finite state machine locking.Obfuscation & access control based VLSI obfuscation.

CONT

VLSI ENCRIPTION/LOCKING & UNLOCKING

XOR /XNOR basedMUX basedPermutation basedReconfigurable logic barrier based

Key propagationPath analysisGraph isomorphism

RECONFIGURATION BASED VLSI DESIGN FOR SECURITYReconfiguration Based VLSI Obfuscation. Theorem : A reconfigurable implementation of a logic function f or a sequential module is an obfuscated implementation for any supply chain adversary.

Reconfiguration Based VLSI Moving Target Defense.Theorem: Reconfiguration for different logic functions or sequential modules achieves VLSI moving target defense.A n-type reconfigurable double gate carbon nanotube field effect transistor(RDG-CNFET).

Reconfiguration Based Security Aware VLSI Design In Emerging TechnologiesCONTReconfigurable reversible computing(RRC) based cryptography.

Obfuscation Based VLSI Design For Security Methodology:Obfuscate minimum part of h/w system while ensuring all the required security properties.Identify and evaluate each possible attack scheme.Develop and evaluate each potential defense scheme.Choose a defense scheme

LEON2 PROCESSORLEON2 is an open source SPARC V8 architecture processor based on a simple 5-stage ( Fetch (FE), Decode(DE) , Execute(EX), Memory(MEM), Write(WR)) instruction pipeline.

DEEXMEMRFDMD QWRFEIMD QD QD QCONTPossible attack and defense schemes: On computational integrity.Hardware Trojans that compromise computational integrity.

Code injection hardware Trojan (shaded in red) including a Trojan ROM, a group of multiplexers, and a trigger logic module.CONTReconfigurable instruction decoder for instruction set randomization.Evaluation

CONTOn data confidentiality.Memory access Trojans

Attack targets of five unauthorized memory access hardware Trojans in a LEON2 processor.CONT1) injecting a memory access instruction;2) injecting memory access request signals including a memory address and an Address Space Identifier ;3) injecting memory access request signals including a memory address while tampering the supervisor signal;4) injecting memory access request signals including a memory address after tampering the Process State Register;5) injecting memory access request signals including a memory address after tampering the PSR directly.CONTReconfigurable memory access module against illegal memory access

Obfuscated memory access logic (shaded in blue) including memory access instruction decoding logic, WRPSR decoding logic, PSR, supervisor signal logic and ASI logic.CONTEvaluation.

CONCLUSIONProposed system includes a reconfigurable instruction decoder for ISR against code injection attack.A reconfigurable memory access module for memory access signal encoding against unauthorized memory access in open source leon2 processorPrevent program monitoring Trojan attacks and increase minimum code injection Trojan with a 1KB ROM by 2.38% for every 1%area increase .Encrypting instructions by simple reconfigurable logic module prevent CIA at a cost of 0.72%area increase, negligible power consumption increase, and no performance degradation .

CONTAchieve a memory access Trojan-resistant LEON2 processor at the cost of 4.42% area increase, negligible power consumption increase, and 11.30%critical path delay increase. Emerging technologies such as carbon nanotube crossbar-based reconfigurable computing provide further cost reduction for the proposed methodology.THANK YOU