„throughsiliconviafor 3dintegraon“ · 2014-10-24 · „throughsiliconviafor 3dintegraon“!!...
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„Through Silicon Via for 3D integra5on“
Myth or reality ?
08.02.13 Solience Ngansso 1
Solience Ngansso Department of Circuit Design University of Heidelberg
Supervisor: Prof. Dr. Peter Fischer
Advanced Seminar „Computer Engineering“
WS 2012/2013
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Outline
1) Basic Definitions 2) 3D IC process flow with the different steps
3) TSV Process fabrication
4) Summary and Discussion
08.02.13 Solience Ngansso 2
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3D BACKGROUND TECHNOLOGY
08.02.13 Solience Ngansso 3
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Some Basic DefiniKons
Ø TSV Through Silicon Via. A via that goes through the silicon substrate that enables connecKon from top to boPom Ø 3D-‐IC
MulKple dies are stacked and TSV is used for the inter-‐die interconnecKon
08.02.13 Solience Ngansso 4
[2] hPp://www.ee.ncu.edu.tw/~jfli/vlsi2/lecture/ch07.pdf
[3] hPp://asia.stanford.edu/events/Spring05/slides/051205-‐Koyanagi.pdf
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Some Basic DefiniKons
Ø FEOL TSV Front-‐end-‐of-‐line TSVs are fabricated before the IC wiring processes occur.
Ø BEOL TSV
Back-‐end-‐of-‐line (BEOL) TSVs are made at the IC foundry during the metal wiring processes
08.02.13 Solience Ngansso 5
[4]hPp://jsa.ece.uiuc.edu/tsv/Yokohama_paper.pdf
[5]hPp://jsa.ece.uiuc.edu/tsv/Yokohama_paper.pdf
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3D Real estate analogy
08.02.13 Solience Ngansso 6
2D: Side-‐by-‐side placement (horizontal)
3D: verKcal integraKon
[7] hPp://www.aspdac.com/aspdac2009/archive/pdf/4D-‐1.pdf
[6] hPp://www.aspdac.com/aspdac2009/archive/pdf/4D-‐1.pdf
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3D IC PROCESS FLOW WITH THE DIFFERENT STEPS
08.02.13 Solience Ngansso 7
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3D IC process variaKons
Ø Three majors process technologies:
08.02.13 Solience Ngansso 8
TSV FabricaKon Wafer thinning Die bonding
Via First Via Last
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TSV fabricaKon process variaKons.
No TSV Via First
Via First „FEOL“
Via First „BEOL“
Via Last „copper liner“
„FEOL“
„BEOL“
„Thinning“
„Bonding“
08.02.13 Solience Ngansso 9
TSV
TSV
TSV
TSV
Ø TSVs can be categorized by when they are fabricated relaKve to the IC fabricaKon process.
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AnimaKon (technology steps)
Ø A short animaKon for the chip-‐level 3D integraKon process, illustrated the technology steps:
08.02.13 Solience Ngansso 10
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TSV PROCESS FABRICATION
08.02.13 Solience Ngansso 11
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TSV Processing
08.02.13 Solience Ngansso 12
Via formaKon -‐Deep reacKve-‐ion etching -‐Laser -‐Other (e.g. wet chemical etch)
Wafer Stacking Cu diffusion, adhesive or fusion bonding Micro-‐bumping
+ Via Filling Material: Copper, Tungsten, polysilicon Different Materials require different deposiKon
processes (electroplaKng, CVD, LPCVD) Cu is the most widely used material today
[8]M. Young, The Technical Writer’s Handbook. Mill Valley, CA: University Science, 1989.
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TSV(Typical Design Values)
08.02.13 Solience Ngansso 13
TSV diameter 75 µm
TSV height 90 µm
TSV-‐to-‐TSV pitch 150 µm
SiO2 thickness 0.1 µm
Number of stacked dies 8
Junc5on depth 1 µm
ResisKvity of Silicon 10 Ω.cm
Contact Width 22.5 µm
Ohmic Contact informa5on
TSV dimension
[9]M. Young, The Technical Writer’s Handbook. Mill Valley, CA: University Science, 1989.
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TSV Size Today and in the future
08.02.13 Solience Ngansso 14
Intermediate Level, W2W 3D-‐stacking 2009-‐1012 2013-‐2015 Minimum TSV diameter 1-‐2 µm 0.8-‐ 1.5 µm Minimum TSV pitch 2-‐4 µm 1.6-‐3.0 µm Minimum TSV depth 6-‐10 µm 6-‐10 µm Maximum TSV aspect raKo 5:1 – 10:1 10:1 – 20:1 Bonding overlay accuracy 1.0-‐ 1.5 µm 0.5 – 1.0 µm Minimum contact pitch 2-‐3 µm 2-‐3 µm Number of Kers 2-‐3 8-‐16 (DRAM)
[11] hPp://www.ee.ncu.edu.tw/~jfli/vlsi2/lecture/ch07.pdf
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TSV Barrier
08.02.13 Solience Ngansso 15
Ø TSV IsolaKon Liner Process: In order to electrically isolate the TSV connecKons from the SI substrate, an isolaKon layer is required
Ø Prevalent barrier materials used are Ta and TiN
[13]hPp://www.sematech.org/meeKngs/archives/3d/8334/pres/Fukushima.pdf
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VIA FORMATION METHODE
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DRIE Method (Bosch Process)
Ø Deep reacKve-‐ion etch (DRIE) Ø Where passivaKon and etching steps are alternaKng in Kme
-‐ allows for high aspect raKon etching DRIE : AR ◊ 17 to 33 Etch depths (30-‐100 µm)
Ø The prevalent technique used is the ´Bosch´ Process
Bosch Process advantages § Can be conducted at room temperature § Low temperature sensiKvity
08.02.13 Solience Ngansso 17
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DRIE vs Laser Drilling
08.02.13 Solience Ngansso 18
Deep reacKve-‐ion etch (DRIE) DRIE Bosch Method highly anisotropic etch process used to create deep penetraKon Based on the literatures >95 % vias
Laser Drilling Method Single-‐point operaKon a process in which a laser is used to make holes, instead of convenKonal drilling.
[14]hPp://asia.stanford.edu/events/Spring05/slides/051205-‐Koyanagi.pdf [15]hPp://asia.stanford.edu/events/Spring05/slides/051205-‐Koyanagi.pdf
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TSV Processes
08.02.13 Solience Ngansso 19
Via forming Bosch DRIE Laser
Dielectric deposiKon SiO2 Polymer
Barrier/seed layers deposiKon
Ti (or Ta)/ Cu W/W
Via filling Cu ConducKve polymer, CNT, solder, etc.
TSV revealing Wet etch
TSV process TSV before bonding, TSV auer bonding
Via last (front-‐or back-‐side)
Stacking C2C W2W
Micro interconnect Solder bump
Processes Methods/Op5ons
Ø 3D IntegraKon Processes, Methods, and OpKons
[12]hPp://iopscience.iop.org/1748-‐0221/4/03/P03009/pdf/1748-‐0221_4_03_P03009.pdf
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VIA FIRST
08.02.13 Solience Ngansso 20
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TSV for bonding
08.02.13 Solience Ngansso 21
VIA-‐FIRST
Ø Vias created early in the device manufacturing process Ø Issues with temperature compaKbility of subsequent CMOS steps Ø Materials must be CMOS compaKble
Targetresistance: < 1 Ω Only known good wafers are used
Lower cost than via-‐last
[16]Image Courtesy of Amkor
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VIA LAST
08.02.13 Solience Ngansso 22
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Via auer Bonding
08.02.13 Solience Ngansso 23
Ø No thermal stress issues Ø Via locaKon must be considered during design phase Ø Large via feature (Ø up to bond pad size), Ø low via density via pitch ~100-‐150μm
– Wafer thickness <200μm -‐via area has to be reserved designing the chip -‐area for vias introduces dead area in CMOS chip complicated process flow
[17]Image Courtesy of Amkor
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Video (3D IC Process descripKon)
08.02.13 Solience Ngansso 24
Source: Projektgruppe ASSID (All Silicon System IntegraKon Dresden) des Fraunhofer IZM.
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3D IntegraKon Drivers
08.02.13 Solience Ngansso 25
+ Image sensors and memory stacking (for mobile applicaKons) are two mass volume applicaKons for TSVs with short Kme-‐to-‐market
[18]14. L. Bernstein, H. Bartolomew, Trans. Met. Soc. AIME 236, 404 (1966).
These are all potenKal 3D drivers:
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3D-‐IC Advantages
08.02.13 Solience Ngansso 26
ü Performance: Higher bandwidth Shorter wire length Shorter criKcal paths
ü Lower Power Reduced wire L and C Shorter interconnect paths
ü Mixed die technologies Heterogeneous technologies Mixed technology generaKons
ü Smaller form factor Reduced area and thickness
[19]hPp://www.sematech.org/meeKngs/archives/3d/8334/pres/Fukushima.pdf
[20]hPp://www.sematech.org/meeKngs/archives/3d/8334/pres/Fukushima.pdf
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TSV APPLICABILITY
08.02.13 Solience Ngansso 27
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CMOS image sensor package
08.02.13 Solience Ngansso 28
Device Side Back Side
Wafer-level package of CMOS image sensor
[21]hPp://iopscience.iop.org/1748-‐0221/4/03/P03009/pdf/1748-‐0221_4_03_P03009.pdf
The schemaKc diagram of a CSP for image sensors. TSVs connect the bond pad and the backside bump.
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3-‐D arKficial reKna chip
08.02.13 Solience Ngansso 29
Photomicrograph of 3-‐D arKficial reKna chip.
1) RecepKon cell 2) ReKna cell 3) Bipolar cell 4) Amacrine cell 5) Ganglion cell
[22]hPp://www.sematech.org/meeKngs/archives/3d/8334/pres/Fukushima.pdf
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3D µprocessor Chip
08.02.13 Solience Ngansso 30
ü CPUs are connected to the respecKve memory layers of the 3D shared memory
ü 14x increase in memory density
ü 4x Logic Cost ReducKon
ü 29x à100x memory cost reducKon
[23]hPp://www.sematech.org/meeKngs/archives/3d/8334/pres/Fukushima.pdf
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CONCLUSIONS, AND FUTURE PROJECTIONS
08.02.13 Solience Ngansso 31
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Conclusion
08.02.13 Solience Ngansso 32
Ø 3D TSV packages outgrow semiconductor industry by 10X.
Cost Analysis for 3D Integra5on with TSV Ø Although the technical challenges
for 3D ICs are close to be overcome, the cost of the technology is still a major hurdle.
Annealing Ø The greatest technological
challenge is heat control
[24]hPp://www.aspdac.com/aspdac2009/archive/pdf/4D-‐1.pdf
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Future ProjecKons
08.02.13 Solience Ngansso 33
The boPom line is: 3D through silicon via (TSV) chips will represent 9% of the total semiconductors value in 2017
[25]hPp://www.csmantech.org/Digests/2007/2007%20Papers/02d.pdf
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Thank you for your aPenKon
08.02.13 Solience Ngansso 34
QuesKons?
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References
08.02.13 Solience Ngansso 35
[1] hPp://www.ee.ncu.edu.tw/~jfli/vlsi2/lecture/ch07.pdf [2] hPp://ecadigitallibrary.com/pdf/58thECTC/s13p5p43.pdf [3] hPp://jsa.ece.uiuc.edu/tsv/High_density_Paper.pdf [4] hPp://en.wikipedia.org/wiki/Through-‐silicon_via [5] hPp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4550029 [6] hPp://www.ae.utexas.edu/~ruihuang/talks/TSV_April2010.pdf [7] P.Garrou, „wafer Level 3D integraKon,“ presented at peaks in packaging Whitefish Montana, Sept. 5-‐7, 2007 [8] P. Garrou and C. Bower, "Overview of 3D IntegraKon Process Technology", Chapter 3 in Handbook of 3D IC IntegraKon: Technology and ApplicaKons, P. Garrou, C. Bower and P. Ramm Eds. , Wiley VCH, 2008 [9] P. Enquist, "3D IntegraKon at Ziptronix", chapter 25 in Handbook of 3D IC IntegraKon: Technology and ApplicaKons, P. Garrou, C. Bower and P. Ramm Eds., Wiley VCH, 2008.