Logic SynthesisImproving XOR-Dominated Circuits by

Exploiting Dependencies between Operands

Zhongkai Chen

Electrical and Computer Engineering

Outline

Background

Motivation

Implementation

Conclusion

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Unlike FPGA, XOR Gate in ASIC Design has more delay and more area than other gates.

We should reduce the number of XOR.

Background

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# of XOR ↑ # of XOR ↓

Computer Arithmetic

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Background

Which is the last area where people still manually optimize circuits, even though logic synthesis has made enormous progress.

AdderIs domination of a good arithmetic, however it contains a LARGE number of XORs.

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But…Synthesizer seldom rewrites XORs…

Automatically rewriting XORs is necessary for synthesizer! It is time to find a solution!

Background

MotivationWhy not rewrite all XORs?

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1. Increase size of input expression exponentially. Only being used when number of XORs is small.

MotivationWhy not rewrite all XORs?

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2. Not all XORs are suitable for expansion:

Before: D: 0.37ns A: 138.2um2

After: D:0.26ns A: 146.9um2

30% Faster! A Small Area Cost.

Before: D: 0.22ns A: 58.8um2

After: D:0.27ns A: 221.2um2

Both Delay and Area Increases!

Implementation

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Selective ExpansionLocal Correlation

Global Correlation

Implementation

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Local Correlation

Two Extreme Cases:AB=0 => A B=A+B⊕A+B=1 => A B=AB⊕So we consider AB and (A+B) as two important factors. We evaluate the delay and area of these two factors.

Implementation

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Local Correlation

Implementation

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Global Correlation

Implementation

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Global Correlation

Much FasterLess Area

Optimized Result

Conclusion

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2 Correlations MergedOptimisation results for all benchmarks

Conclusion

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2 Correlations MergedComparison of bitwise delays of the multiplier

Less Delay

Thank You

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