basic two stage cmos opamp - cppsim · basic two-stage cmos opamp is a workhorse for many - - -we...

M.H. Perrott

Analysis and Design of Analog Integrated CircuitsLecture 17

Basic Two Stage CMOS Opamp

Michael H. PerrottApril 4, 2012

Copyright © 2012 by Michael H. PerrottAll rights reserved.

M.H. Perrott

Opamps Are Basic Analog Building Blocks

Enable active filters- Can achieve arbitrary pole/zero placement using only

capacitor/resistor networks around the opamp Allow accurate voltage to current translation Provide accurate charge transfer between capacitors

- Extremely useful for switched capacitor circuits used in analog-to-digital converters and discrete-time analog filters

2

C1

R1Vin

Vref

Vout

C2

Vin

Vref

VoutC1

Vref

Rref

Iref

Analog Filters Current References Switched Capacitor Circuits

M.H. Perrott 3

Key Specifications of Opamps (Open Loop)

DC small signal gain: K Unity gain frequency: w0

Dominant pole frequency: wdom

Parasitic pole frequencies: wp (and higher order poles) Output swing (max output range for DC gain > Kmin)

Vin

Vout

Vdd

Vss

Rhuge

Chuge

Vin

Vout

Vdd

Vss

Vout/Vin

w (rad/s)wdom

20log

20log(K)

wp

Zout

0dB

w0

CL

CL

Set Rhuge >> |Zout|

and 1/(RhugeChuge) << wdom

For Open Loop Characterization

M.H. Perrott

Key Specifications of Opamps (Closed Loop)

Offset voltage Settling time (closed loop bandwidth) Input common mode range Equivalent Input-Referred Noise Common-Mode Rejection Ratio (CMRR)

Power Supply Rejection Ratio (PSRR)

4

Vin

VoutVoffset

Vdd

Vss CL

CMRR =

ÃδVoffset

δVin

!−1

PSRR+ =

ÃδVoffset

δVdd

!−1PSRR− =

ÃδVoffset

δVss

!−1

M.H. Perrott

Slew Rate Issues for Opamps

Output currents of practical opamps have max limits- Impacts maximum rate of charging or discharging load

capacitance, CL- For large step response, this leads to the output lagging behind the ideal response based on linear modeling We refer to this condition as being slew-rate limited

Where slew-rate is of concern, the output stage of the opamp can be designed to help mitigate this issue- Will lead to extra complexity and perhaps other issues

5

Vin

Vout

Vdd

Vss

Vin

Vout

ideal

slew-rate limitedCL

M.H. Perrott

Basic Two Stage CMOS Op Amp

This is a common “workhorse” opamp for medium performance applications

Provides a nice starting point to discuss various CMOS opamp design issues

Starting assumptions: W1/L1 = W2/L2, W3/L3 = W4/L4

6

M7

M6

IrefM1 M2

M3

M8

Vout

CL

CcRc

M4

M5

Vin+Vin-

M.H. Perrott

First Stage Analysis

Derive two port model assuming differential input:

7

Ibias1

vout1

-vid/2

Rout1

vid/2

Rout1Gm1V1ZinV1 Zin2vid vout1

First Stage Two-Port Model

M1 M2

M3 M4

M5

Gm1 = gm1 = gm2

Rout1 = ro2||ro4

Zin1 =1

s(Cgs1/2)=

1

s(Cgs2/2)

M.H. Perrott

Derivation of Rout1 (Incorrect Approach)

Application of Thevenin analysis seems to imply that

- Why is this incorrect?

8

-vid/2

ro4

vid/2M1 M2

M4gm3

1

ro5

ro2(1+gm2 )gm11 2ro2

Rout1 = 2ro2||ro4

M.H. Perrott

Derivation of Rout1 (Correct Approach)

Correct approach includes the impact of the current mirror feedback

9

ro4

M1 M2

M4gm3

1

2ro2i1=

vtest

itest = i1 + i2vtest2ro2

i1

i1i2

i2 i1 +vtestro4

ro5

⇒ Rout1 = ro2||ro4

itest = i1 + i2 = i1 + i1 +vtest

ro4= 2

vtest

2ro2+vtest

ro4

M.H. Perrott

Derivation of Gm1

For differential input, we can approximate the source of M1 and M2 as being at incremental ground

10

-vid/2 vid/2M1 M2

M4gm3

1

iout = i1 + i2i1 i2

incremental ground

i1

⇒ iout = gm1vid ⇒ Gm1 = gm1 = gm2

i1 = −gm1(−vid/2) =gm12vid

i2 = gm2(vid/2) =gm22vid =

gm12vid

M.H. Perrott

-vid/2 vid/2M1 M2

M4gm3

1

incremental groundCgs2Cgs1

-vid/2 vid/2Cgs2Cgs1

-vid/2 vid/2Cgs2Cgs1

-vid/2 vid/2Cgs1/2

vid

Cgs1/2

Derivation of Zin

For differential input, we can simplify the input capacitance calculation through the steps shown at the right

11

⇒ Zin1 =1

sCgs1/2=

1

sCgs2/2

M.H. Perrott

Second Stage Analysis

Two port model derivation is straightforward- This is a common source amplifier

12

Ibias2

Rout2Gm2V2Zin2V2vin2 vout

Second Stage Two-Port ModelM7

M6

Vout

CL

Vin2

CL

Gm2 = gm6

Rout2 = ro6||ro7

Zin2 =1

sCgs6

M.H. Perrott

Overall Opamp Model

Overall transfer function

- DC gain

- Poles

In general, wp2 << wp1 since CL >> Cgs6

13

CLV2gm1V1V1vid

First Stage Two-Port Model

Cgs1

2ro2||ro4 voutgm6V2

Second Stage Two-Port Model

Cgs6 ro6||ro7

K = gm1(ro2||ro4)gm6(ro6||ro7)

H(s) =vout(s)

vid(s)=

K

(1 + s/wp1)(1 + s/wp2)

wp1 =1

(ro2||ro4)Cgs6wp2 =

1

(ro6||ro7)CL

M.H. Perrott

Consider The Dominant Pole To Be wp2

At frequencies >> wp2

14

Vout/Vid

w (rad/s)1

20log

0dB

w0

20log(gm1(ro2||ro4)gm6(ro6||ro7))

(ro6||ro7)CLwp2 =

H(s) =K

1+ s/wp2=gm1(ro2||ro4)gm6(ro6||ro7)

1 + s(ro6||ro7)CL

H(s) ≈ gm1(ro2||ro4)gm6sCL

⇒ wo ≈gm1(ro2||ro4)gm6

CL

We want wp1 > w0 for good phase margin with unity gain feedback

M.H. Perrott

Key Issue for Achieving Adequate Phase Margin

To achieve wp1 > w0

- We need a very large value of CL relative to Cgs6

This will generally be impractical!15

Vout/Vid

w (rad/s)1

20log

0dB


(ro6||ro7)CLwp2 =

1(ro2||ro4)Cgs6

wp1 =w0

wp1 =1

(ro2||ro4)Cgs6> wo ⇒ CL > gm1gm6(ro2||ro4)2Cgs6

wo ≈gm1(ro2||ro4)gm6

CL

M.H. Perrott

Pole Splitting Using a Compensation Capacitor

Consider placing capacitor Cc across the second stage- Load capacitance seen by stage 1 becomes roughly

This large Miller capacitance now causes wp1 to become dramatically lower such that it forms the dominant pole

We will see that wp2 actually increases in frequency!16

CLV2gm1V1V1vidCgs1

2ro2||ro4 voutgm6V2Cgs6 ro6||ro7

CcCM

CM = (1+ gm6(ro6||ro7))Cc ≈ gm6(ro6||ro7)Cc

wp1 ≈1

(ro2||ro4)CM≈ 1

(ro2||ro4)gm6(ro6||ro7)Cc

M.H. Perrott

Pole Splitting Using a Compensation Capacitor (Part 2)

Assuming wp1 forms the dominant pole, we can approximate Cc as a short when calculating wp2

- Note: we must have Cc >> Cgs6 for this to be accurate The inclusion of capacitor Cc has led to wp2

increasing in frequency17

CLV2gm1V1V1vidCgs1


Cc Rth_CLCM

Rth CL≈ 1

gm6

⇒ wp2 ≈1

(1/gm6)(Cgs6 + CL)=

gm6Cgs6 + CL

M.H. Perrott

Impact of Pole Splitting using Compensation Cap

Pole splitting allows the dominant pole frequency to be dramatically decreased and the main parasitic pole to be dramatically increased- We can achieve higher unity gain frequency with

improved phase margin and with reasonable area18

Vout/Vid

w (rad/s)

1

20log


(ro6||ro7)CLwp2 =

1(ro2||ro4)Cgs6

wp1 =

1(ro2||ro4)gm6(ro6||ro7)Cc

wp1 = wp2 = Cgs6+CL

gm6

M.H. Perrott

Unity Gain Frequency with Compensation Cap

At frequencies >> wp1

19

Vout/Vid

w (rad/s)

20log



wp1 = Cgs6+CLwp2 =

gm6

0dB

w0

H(s) =K

1+ s/wp1=

gm1(ro2||ro4)gm6(ro6||ro7)1 + s(ro2||ro4)gm6(ro6||ro7)Cc

⇒ wo ≈gm1Cc

We want wp2 > w0 for good phase margin with unity gain feedback

H(s) ≈ gm1(ro2||ro4)gm6(ro6||ro7)s(ro2||ro4)gm6(ro6||ro7)Cc

M.H. Perrott

Key Constraints for Achieving Adequate Phase Margin

To achieve wp2 > w0

- Note: we must have Cc >> Cgs6 for this to be accurate20

Vout/Vid

w (rad/s)

20log



wp1 = Cgs6+CLwp2 =

gm6

0dB

w0

wo ≈gm1Cc

wp2 =gm6

Cgs6 + CL> wo ⇒ Cc >

gm1gm6

(Cgs6+CL)

M.H. Perrott

More Accurate Calculations Related to Phase Margin

To achieve wp2 > w0

21

Vout/Vid

w (rad/s)

20log



wp1 = Cgs6CL+Cc(Cgs6+CL) wp2 =gm6Cc

0dB

w0

wo ≈gm1Cc

wp2 > wo ⇒ Cc >gm1gm6

ÃCgs6CL

Cc+ Cgs6 + CL

!

M.H. Perrott

A More Accurate Transfer Function Model

22

CLV2gm1V1V1vidCgs1


Cc


H(s) =vout(s)

vid(s)=

K(1 + s/wz)

(1 + s/wp1)(1 + s/wp2)

wp1 =1


wp2 =gm6Cc

Cgs6CL+ Cc(Cgs6 +CL)

wz = −µgm6Cc

¶ Right half plane (RHP) zero causes potential stability issues

M.H. Perrott

Plotting the Magnitude of a RHP Zero

Plot the magnitude response of right half plane wz

- For w << |wz|:

- For w >> |wz|:

23

20 log |Az(w)| = 20 log |1− jw/wz |

20 log |Az(w)| ≈ 20 log |1| = 0

20 log |Az(w)| ≈ 20 log |w/wz |

ω

20log|Az(ω)|

0 dB

20 dB/decade

ωz

Magnitude response is the same as for left half plane zero

M.H. Perrott

Plotting the Phase of a RHP Zero

Plot the phase response of right half plane wz

- For w << |wz|:

- For w = |wz|:

- For w >> |wz|:

24

6 Az(w) ≈ arctan (0) = 0◦

ω0o ωzωz/10 ωz∗10

-45o

-90o

Az(ω)

6 Az(w) = 6 (1− jw/wz) = arctan (−w/wz)

6 Az(w) ≈ arctan (−1) = −45◦

6 Az(w) ≈ arctan (−∞) = −90◦

Phase response is negative rather than positive (similar to pole)

M.H. Perrott

Phase Margin Degradation Due to RHP Zero

Since the RHP zero adds negative phase (similar to pole), it reduces phase margin- We want:

This is not a desirable constraint25

Vout/Vid

w (rad/s)

20log

Cgs6+CLwp2 =

gm6

0dB

Ccw0 =

gm1

Cc|wz| =

gm6

|wz| À wo ⇒ gm6À gm1

M.H. Perrott

Adding a Compensation Resistor

26

CLV2gm1V1V1vidCgs1


CcRc


H(s) =vout(s)

vid(s)=

K(1 + s/wz)

(1 + s/wp1)(1 + s/wp2)

wp1 =1


wp2 =gm6Cc

Cgs6CL+ Cc(Cgs6 +CL)

wz = −µgm6Cc

¶1

1− gm6Rc

RHP zero effectively removed if Rc = 1/gm6

Improved phase margin possible with Rc > 1/gm6- See Johns&Martin,

pp. 242-244

M.H. Perrott

Implementing Rc with a Triode Device

More compact implementation than a poly resistor Triode channel resistance can somewhat track 1/gm6

across process and temperature variations Key issue: supply sensitivity

- See pp. 246-248 of Johns&Martin for solutions to this issue 27

M7

M6

IrefM1 M2

M3

M8

Vout

CL

CcM9

M4

M5

Vin+Vin-

M.H. Perrott

Calculations for Triode Compensation Resistor

Triode resistance calculated as

28

M6

CcM9

M4

Vdd

Rc =1

μnCox(W9/L9)(Vgs9 − VTH)=

1

μnCox(W9/L9)(Vdd − Vgs6 − VTH)

1

gm6=

1

μnCox(W6/L6)(Vgs6 − VTH)

Depending on Vdd, Rc can track 1/gm6 across process/temp

Assuming square law, 1/gm6 is calculated as

M.H. Perrott 29

Summary

Basic two-stage CMOS opamp is a workhorse for many moderate performance analog applications- Relatively simple structure with reasonable performance

Key issue: two-stages lead to two poles that are relatively close to each other- This leads to very poor phase margin unless very large

CL is used Inclusion of a compensation capacitor across the

second stage leads to pole splitting such that stable performance can be achieved with reasonable area- A compensation resistor is also desirable to help

eliminate the impact of a RHP zero that occurs due to compensation

We will use the basic two stage CMOS opamp structureto explore various opamp specifications in the next lecture

basic two stage cmos opamp - cppsim · basic two-stage cmos opamp is a workhorse for many - - -we...

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