bel 12 logic gate

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Transistors (BJT) are widely used in digital logic circuits and switchingapplications. The fundamental transistor circuit used in switching

applications is called an inverter.

BJT Inverter (Transistor Switch)

The transistor is in CE configuration and no biasvoltage is connected to the base through a resistor,but a resistor RB is connected in series with the

base and then directly to a pulse-type wave thatserves as the inverters input. In the circuit, V

CCand

the high level of input are both +5V. The output isthe voltage between collector and emitter (V

CE= vout)

.

S. Kal, IIT-Kharagpur


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When the input is high ( + 5V), the B-E jn.When the input is high ( + 5V), the B-E jn.is forward biased and current flowsis forward biased and current flowsthrough Rthrough R

BBin to the base. The values ofin to the base. The values of

RRBB and Rand RCC are chosen such that the Iare chosen such that the IBB isisenough to saturate the transistor. Noteenough to saturate the transistor. Notethat the value of Vthat the value of V

CECEin saturation is nearlyin saturation is nearly

0 ( typically V0 ( typically VCE(sat)CE(sat)

0.2 V ). When the0.2 V ). When the

transistor is saturated, it is said to be ONtransistor is saturated, it is said to be ON

and the high input to the inverter (+ 5 V)and the high input to the inverter (+ 5 V)results in a low output (results in a low output ( 0 V).0 V).

When the input to the transistor is low, ie,When the input to the transistor is low, ie,0 V, the B-E jn. is not forward biased, so0 V, the B-E jn. is not forward biased, sono base current, and hence no collectorno base current, and hence no collector

current flows. There is no voltage dropcurrent flows. There is no voltage dropacross Racross R

CCand it follows that Vand it follows that V

CECE= V= V

CCCC..

The transistor is in cut off region and isThe transistor is in cut off region and issaid to be OFF. A low input to the invertersaid to be OFF. A low input to the inverterresults in a high output andresults in a high output and thus the circuithus the circuiis called an Inverter.is called an Inverter.



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In designing inverter, it is assumed that IC(sat)

= VCC

/RC

and

VCE(sat) = 0

Since the transistor is cut off when the input is low, regardlessof the values of R

Band R

C, the equations to be used are those

that apply when input is high.

VCC = VCE + IC RC

IC

= IC(sat)

= VCC

/ RC

IB

= IC(sat)

/ = VCC

/ RC

and IB

= ( VH

VBE

) / RB

where VH

is high level of the input

voltage.

To design a transistor inverter we must have criteria forspecifying the values of R

Band R

C. Typically, one of the values

is chosen, and the value of the other is derived. Therelationship of R

Band R

Care

Inverter Design



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B

=H

BE B

=H

BE

C

CC

RC

= VCC

/ IB

= VCC

RB

/ (VH

VBE

)

Since these equations are valid for a specific values of , they arenot entirely practical. varies over a wide range. If the actualvalue of is smaller than the one used in the design equations,the transistor will not saturate. So in design eqn. must besmallest possible value that might occur in a given application. Sothe R

Band R

Care expressed in the form of inequalities,

RB

(VH

VBE

)/IB

= ( VH

VBE

) RC

/ VCC

RC

VCC

/ IB

= VCC

RB

/ (VH

VBE

)

Inverter Design



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A = low, B= low, both diodes D1

and D2

are non-conducting, so

output, y= 0

A = high, B= low, D1

conducts, D2

is non-conducting, so output, y =

(5 0.7) V = 4.3 V ( high)

A = low, B= high, D2

conducts, D1

is non-conducting. Therefore,output, y = (5 0.7) V = 4.3 V

( high)

Diode Logic (OR gate)

A = high, B = high, both diodes D1

and D2

are conducting.

Therefore, output y= (5 0.7) V = 4.3 V ( high)S. Kal, IIT-Kharagpur


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If any of the input is 0, that

particular diode is forwardbiased and the outputvoltage (y) will be diode drop,i.e. y= 0.7 V (logic 0)

When A = high, B= high, i.e.

both inputs are at 5 V, boththe diodes (D

1, D

2) are not

conducting because thevoltage across the diodes is0. Since no current flows

through RL, the output ispulled on to the supplyvoltage (V

CC= 5 V). Therefore,

y = high.

Diode Logic (AND gate)



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If any of the inputs (A, B) becomes high (= 5 V), that particular

transistor goes into saturation and the output is almost 0 V (=V

CE (sat)).

If both the inputs (A, B) are at logic low level (logic 0 = 0 V), thenswitches are cut off and no current flows through R

L. So the

output y= + 5 V (logic high).

Resister Transistor Logic (RTL) NOR gate



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If any input A or B or both A &B are low, Diode D1 / D2conducts and point X will beat 0.7 volts

T1Off & y = High If A and B are high (5V),

diodes D1, D2 will not conduct,

but D3, D4 conducts and so T1 on (saturation) as thevoltage at point X is more than

2.1 V y = VCE(SAT) and output of T1= Low

Diode Transistor Logic (DTL) NAND gate

Thus the circuit is a NAND gate



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TTL introduced by Texas

Instruments in 1964 is a widelyused logic family of digital circuits.

In TTL, base of T2 is connected to

collector of T1 whose emitter is used

as input terminal. The emitter of T2 is

grounded and its base voltage andhence the collector of T1 will not rise

above 0.75 V[ VBE(sat)]. If vin is high(~

5V), the B-E Jn of T1 is reverse bised

and its C-B jn is forward biased. Thus,the transistor T1 is in inverse mode of

operation.Then IC1 drives T2 and it will be ON.

Transistor Transistor Logic (TTL) Inverter

1. vin= high, T1 is in inverse mode, T2 = ON, vout = VCE(sat) = low

2. vin = low, T1 is in normal mode, T2 = cut off, vout = Vcc = high



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If any of the inputs is at logiclevel 0, T1, is in normal mode

of operation, T3 cut off.

output is at level 1

If all the inputs are at logic 1,

T3 is in saturation and theoutput is at logic 0. Emitter ofT1 5V, Base of T1 < 5V, B-E

jn R.B. Base of T3 0.75

(maxm). C-B jn of T1F.B. T1

works in inverse mode IC1 IB2T3 drives into saturation, Y =

VCE(sat) of T3

TTL NAND gate



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TTL NAND Gate with Totem-Pole output

Integrated circuit TTL is fabrica-ted with a totem-pole pairoutput circuit to allow highspeed swit-ching and a largefan out.

In an IC TTL NAND gate, T1and T2 are integrated into a

single transistor with twoemitters. If necessary, moreemitters can be fabricated onthe same base and multiple

input TTL gates may beobtained. Each emitter acts like a diode; therefore, T1 with 4-k

resistor (RB) acts like two-input AND gate. The rest of the circuit

inverts the signal and the overall circuit acts like a two-input NANDgate



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The input voltages A and B are either low (grounded) or

high (5V). If A or B is low, T1 saturates. This reduces thebase voltage of T2 to almost zero. Therefore, T2 cuts off,

forcing T4 to cut off. Under these conditions, T3 acts likean emitter follower and couples a high voltage to theoutput.

On the other hand, when both A and B are high, thecollector-base junction of T1 becomes forward biased and

its collector diode goes into forward condition; this forcesT2 and T4 into saturation, producing a low output.

Incidentally, without diode D1 in the circuit, T3 wouldconduct slightly when the output is low. The voltage dropby the diode keeps base-emitter diode of T3, reverse-

biased. So only T4 conducts when the output is low. Thus,the circuit behaves as a NAND gate.



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The output transistors (T3 and T4) form a totem-pole

connection. Either transistor T3 or transistor T4 is on. Theoutput is high when T3 is on and it acts like an emitter

follower. The output is low when T4 is on and no current

flows through RC. This is important because it keeps the

circuit power dissipation down.

The advantage of a totem-pole connection is its low-output impedance, which reduces the switching time. Theadvantage of this arrangement occurs in the output highstate. Here T3 is acting as emitter follower with its

associated low output impedance (typically, 10 ). This

low-output impedance provides a short time constant (RC)for charging up any capacitive load (C) on the output. Thisaction is known as active pull-up and provides very fastrise-time waveforms at TTL outputs.

A standard TTL gate has a power dissipation of about 10

mW and a propagation delay time of nearly 10 ns.



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1. MOSFETs can act both as amplifier /driver and as a load resistor,eliminating the need for ordinary loadresistors, which consume large area insilicon ICs.

2. MOSFETs take up very little area

compared to Si-BJTs so that morecircuits can be formed on a wafer.

3. Circuits using MOSFETs have higheryield.

4. Enhancement type MOSFETs are

preferred over depletion type becausethe former can be switched ON or OFFwith the supply and also a singlepolarity supply is sufficient.

N-MOS Inverter and Logic Gates



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In abasic N-MOS inverter circuit, two N-channel MOSFETs (M1 and M2)

are used in this circuit. Instead of passive resistive load, M1 is used asan active load while M2 is used as a switching/driver transistor. M1 is

always in ON state, as it is permanently connected to +5 V andessentially R

ONwill be the load resistance. In response to the input gate-

source voltage (Vin), M2 will switch from ON to OFF state. M1 is

designed to have a narrower channel than M2 so that ON state

resistance (RON) of M1 is greater than that of M2. Typically, RON of M1and M2 are 100 k and 1 k , respectively. ROFF of M2 is around 10

10

.

We many analyze this circuit considering each MOSFET channel as a

resistance so that output voltage is taken from a voltage divider formedby two resistances. With Vin = 0 V, M2 is off, with a very large channel

resistance of 1010 . Since M1 has RON 100 k , the voltage divider

output will be essentially 5 V. On other hand, with V in = 5 V, M2 is on,

with RON

1 k . The voltage divider output is now nearly 0.05 V. Thus,

the circuit functions as an inverter since a low input produces a high

output, and vice versa.

N-MOS Inverter



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(a) MOS NAND gate (b) MOS NOR gate



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CMOS inverter utilizes two matched enhancement typeMOSFETs: one M2, with n-channel and the other M1, with a p-

channel. The body of each device is connected to its sourceand thus no body effect arises.

In a CMOS switch, n-MOS and p-MOS are joined at theirdrains and the series combination is connected across thesupply voltage (V

SS). +V

ssis connected with source p-MOS

and Vss

is connected to the source of n-MOS and grounded.

The output is taken at common drain and the input is appliedin common to both gates. Both p-MOS and n-MOS transistors

operate in E-mode. Vi swings from ground voltage (~0V) to+V

SS.

CMOS Inverter



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When Vi

ground ~ 0 V, M2

will

be OFF, because VGS

(QN

){ ~ 0} VT . V0

= VSS

.

When Vi V

SS, (logic high) M2

will be ON, because VGS

(QN

)

{~VSS

} >VT

and M1 will be OFF,

because, VGS

(M1) { ~ 0} < VT

. V0 = 0. High gm of M2 willhave small drop w.r.t. ground.Gate of M1 is at zero volts with

respect to source

CMOS Inverter



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In CMOS, V0

= full supply voltage, when Vi

= 0.

When Vi V

SS, V

0approaches a very low value ( 10 mV)

Transition between two levels ( 0 and VSS

) much sharp

When switch is at one or the other limit of its range, itspower dissipation is normally zero. Because in High or Lowcase one or the other FET is cut off. The current suppliedby the supply voltage is nominally zero ( except leakagecurrent 10 nA).

Impedance looking into the gate of FET is 109 , so inthe quiescent condition, there is no power dissipation.

Advantages of CMOS Inverter



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CMOS NAND gate CMOS NOR gateS. Kal, IIT-Kharagpur

bel 12 logic gate

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