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THE ISLAMIC UNIVERSITY OF GAZA
ENGINEERING FACULTY DEPARTMENT OF
COMPUTER ENGINEERING DIGITAL LOGIC
DESIGN LAB – ECOM 2112
Binary Addition and Subtraction
Eng. Mai Z. Alyazji
October, 2016
DIGITAL LOGIC DESIGN LAB ECOM 2112 ENG. Mai Z. Alyazji
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Objectives: To be familiar with adder and subtractor circuits.
Background:
Adders
Digital computers perform a variety of information-processing tasks. Among
the functions encountered are the various arithmetic operations. The most
basic arithmetic operation is the addition of two binary digits. This simple
addition consists of four possible elementary operations: 0 + 0 = 0, 0 + 1 = 1, 1
+ 0 = 1, and 1 + 1 = 10. The first three operations produce a sum of one digit,
but when both augend and addend bits are equal to 1, the binary sum consists
of two digits. The higher significant bit of this result is called a carry. When the
augend and addend numbers contain more significant digits, the carry
obtained from the addition of two bits is added to the next higher order pair of
significant bits. A combinational circuit that performs the addition of two bits
is called a half adder. One that performs the addition of three bits (two
significant bits and a previous carry) is a full adder. The names of the circuits
stem from the fact that two half adders can be employed to implement a full
adder.
Half Adder
From the verbal explanation of a half adder, we find that this circuit needs two
binary inputs and two binary outputs. The input variables designate the
augend and addend bits; the output variables produce the sum and carry. We
assign symbols x and y to the two inputs and S (for sum) and C (for carry) to
the outputs. The truth table for the half adder is listed in Table 1.
DIGITAL LOGIC DESIGN LAB ECOM 2112 ENG. Mai Z. Alyazji
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Inputs Outputs x y s c 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
Table 1: Half adder
The C output is 1 only when both inputs are 1. The S output represents the
least significant bit of the sum. The simplified Boolean functions for the two
outputs can be obtained directly from the truth table. The simplified sum-of-
products expressions are
s = xy’ + x’y = x ⊕ y
c = xy
The logic diagram of the half adder implemented with an exclusive-OR and an
AND gate is shown in Figure 1.
Figure 1 Implementation of Half adder with XOR and AND gate
DIGITAL LOGIC DESIGN LAB ECOM 2112 ENG. Mai Z. Alyazji
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Full Adder
Addition of n-bit binary numbers requires the use of a full adder, and the
process of addition proceeds on a bit-by-bit basis, right to left, beginning with
the least significant bit. After the least significant bit, addition at each position
adds not only the respective bits of the words, but must also consider a
possible carry bit from addition at the previous position. A full adder is a
combinational circuit that forms the arithmetic sum of three bits. It consists of
three inputs and two outputs. Two of the input variables, denoted by x and y,
represent the two significant bits to be added. The third input, z, represents
the carry from the previous lower significant position. Two outputs are
necessary because the arithmetic sum of three binary digits ranges in value
from 0 to 3, and binary representation of 2 or 3 needs two bits. The two
outputs are designated by the symbols S for sum and C for carry. The binary
variable S gives the value of the least significant bit of the sum. The binary
variable C gives the output carry formed by adding the input carry and the bits
of the words. The truth table of the full adder is listed in Table 2.
Inputs Outputs x y z s c 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
S = x’y’z + x’yz’ + xy’z’ + xyz
C = xy + xz + yz
Table 2: Full adder
The logic diagram for the full adder implemented in sum-of-products form is
shown in Figure 2.
DIGITAL LOGIC DESIGN LAB ECOM 2112 ENG. Mai Z. Alyazji
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Figure 2 Implementation of Full Adder in sum-of-products form
We also can implement a Full adder using two Half Adders as shown in Figure
3.
Figure 3 Implementation of Full Adder using two Half Adders
S = xy’z’ + x’yz’ + xyz + x’y’z
= x ⊕ y ⊕ z
C = xy’z + x’yz + xyz’ + xyz
= z(xy’ + x’y) + xy(z+z’) = z(x⊕y) + xy
DIGITAL LOGIC DESIGN LAB ECOM 2112 ENG. Mai Z. Alyazji
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Half Subtractor
The Half Subtractor is a combinational circuit which is used to perform
subtraction of two bits. It has two inputs, the minuend X and subtrahend Y
and two outputs the difference D and borrow out Bout. The borrow out signal
is set when the Subtractor needs to borrow from the next digit in a multi-digit
subtraction. That is, Bout = 1 when X < Y. Since X and Y are bits, Bout = 1 if and
only if X = 0 and Y = 1. An important point worth mentioning is that the half
Subtractor diagram aside implements Y - X and not X - Y since Bout on the
diagram is given by
Bout = X Y’.
This is an important distinction to make since subtraction itself is not
commutative, but the difference bit D is calculated using an XOR gate which is
commutative.
The truth table for the Half Subtractor is listed in Table 3.
Inputs Outputs x y d b 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0
Table 3: Half Subtractor
d = xy’ + x’y = x ⊕ y
b = x’y
The logic diagram of the half subtractor implemented with an exclusive-OR
and an AND gate is shown in Figure 4.
DIGITAL LOGIC DESIGN LAB ECOM 2112 ENG. HUDA M. DAWOUD
Inputs Outputs x y bin d bout
0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1
Figure 4 Implementation of Half Subtractor with XOR and AND gate
Full Subtractor
The full Subtractor is a combinational circuit which is used to perform
subtraction of three input bits: the minuend X, subtrahend Y, and borrow in
Bin. The full Subtractor generates two output bits: the difference D and borrow
out Bout. Bin is set when the previous digit borrowed from X. Thus, Bin is also
subtracted from X as well as the subtrahend Y. Or in symbols: X - Y – Bin. Like
the half subtractor, the full subtractor generates a borrow out when it needs
to borrow from the next digit. Since we are subtracting X by Y and Bin, a
borrow out needs to be generated when X < Y + Bin. When a borrow out is
generated, 2 is added in the current digit. (This is similar to the subtraction
algorithm in decimal. Instead of adding 2, we add 10 when we borrow.)
Therefore, D = X - Y - Bin + 2Bout
The truth table of the full subtractor is listed in Table 4.
7 Table 4: Full subtractor
DIGITAL LOGIC DESIGN LAB ECOM 2112 ENG. HUDA M. DAWOUD
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As Full Adder we can implement it using sum-of-products form and using two
half subtractors. Figure 5 show the implementation of Full subtractor using
two Half subtractors.
Figure 5 Implementation of Full subtractor using two Half subtractors
D = x’y’bin + x’yb’in + xy’bin + xybin = x ⊕ y ⊕ bin
Bout = x’y’bin + x’yb’in + x’ybin + xybin
= bin (x’y’ + xy) + x’y(bin + b’in)
= bin (x ⊕ y)’ + x’y
DIGITAL LOGIC DESIGN LAB ECOM 2112 ENG. HUDA M. DAWOUD
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Parallel Addition
Multiple full adder circuits can be cascaded in parallel to add an N-bit number.
For an N- bit parallel adder, there must be N numbers of full adder circuits. A
ripple carry adder is a logic circuit in which the carry-out of each full adder is
the carry in of the succeeding next most significant full adder. It is called a
ripple carry adder because each carry bit gets rippled into the next stage. In a
ripple carry adder the sum and carry out bits of any half adder stage is not
valid until the carry in of that stage occurs.
Note that the first (and only the first) full adder may be replaced by a half
adder. Figure 6 shows the implementation of 4-bit binary adder using 4 full
adders.
Figure 6 The implementation of 4-bit binary adder using 4 full adders.
Adder – Subtractor
The subtraction A - B can be done by taking the 2’s complement of B and
adding it to A . The 2’s complement can be obtained by taking the 1’s
complement and adding 1 to the least significant pair of bits. The 1’s
complement can be implemented with inverters, and a 1 can be added to the
sum through the input carry.
DIGITAL LOGIC DESIGN LAB ECOM 2112 ENG. HUDA M. DAWOUD
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Figure 7 Four-bit adder–subtractor (with overflow detection)
The addition and subtraction operations can be combined into one circuit
with one common binary adder by including an exclusive-OR gate with each
full adder. A four-bit adder–subtractor circuit is shown in Figure 7. The mode
input M controls the operation. When M = 0, the circuit is an adder, and when
M = 1, the circuit becomes a subtractor. Each exclusive-OR gate receives input
M and one of the inputs of B. When M = 0, we have B ⊕ 0 = B. The full adders
receive the value of B, the input carry is 0, and the circuit performs A plus B .
When M = 1, we have B⊕1 = B’ and C0 = 1. The B inputs are all complemented
and a 1 is added through the input carry. The circuit performs the operation A
plus the 2’s complement of B. (The exclusive-OR with output V is for detecting
an overflow.)
DIGITAL LOGIC DESIGN LAB ECOM 2112 ENG. HUDA M. DAWOUD
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Lab work:
Equipment’s required:
IC's 74LS04 (Hex Inverter), 74LS08 (Quad 2 input AND), 74LS32 (Quad
2 input OR), 74LS86 (Quad 2 input Exclusive OR), 74LS83 (4-bit binary
adder)
Module KL-33004.
The Datasheets of the IC’s.
Part I: Half Adder and Full Adder
Construct the circuit of Half Adder using XOR gate and AND gate.
Construct Full Adder using the previous circuit with another Half Adder.
Part II: Half Subtractor and Full Subtractor
Construct the circuit of Half Subtractor using XOR gate and AND gate.
Construct Full Subtractor using the previous circuit with another Half
Subtractor.
Part III: 4-bit binary adder
Construct a 4-bit binary adder using 74LS83 IC.
Part IV: Adder-Subtractor
Use module KL-33004 to construct a circuit that is similar to the one in
Figure 7.
DIGITAL LOGIC DESIGN LAB ECOM 2112 ENG. HUDA M. DAWOUD
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Exercises: Implement the 4-bit Borrow Ripple Subtractor using Full Subtractor.
Implement the 4-bit Borrow Ripple Subtractor using Full Adder.
Using four half-adders design a four bit combinational circuit
incrementer (a circuit that adds 1 to a four bit binary number).
Using full-adders design a circuit that implements a multiplication of 4
bits like (1011 × 1100).
Hint: the multiplication operation is an addition operation,
Ex: 5*3 is 5+5+5, and so on.