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The RC Delay Model for Gates

Recall that the RC Delay model for NMOS/PMOS from Harris (k is the width of the gate)

kg

s

d

g

s

d

kCkC

kCR/k

kg

s

d

g

s

d

kC

kC

kC

2R/k

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General RC Inverter Model

Inverter Model

in

CinRdi

Rui

Cpi Cout

out

Rui : pullup resistance

Rdi : pulldown resistance

Cpi: parasitic cap of gate from drain capacitances

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Inverter RC Delay Model

Tplh (pullup delay) = Rui * ( Cpi + Cout)

= Rui * Cpi + Rui * Cout

= parasitic delay PU + load delay PU

Tphl (pulldown delay) = Rdi * ( Cpi + Cout)

= Rdi * Cpi + Rui * Cout

= parasitic delay PD + load delay PD

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Parasitic Delay versus Load Delay

Parasitic delay is fairly constant with increasing gate width because the channel resistance goes down with increasing Width, but the drain capacitance goes up, so the total R*C is about constant.

Load delay is proportional to Cout/Cin because wider transistors (increasing Cin) can drive a fixed output load faster, while an increasing load causes a larger gate delay for a fixed driving transistor width.

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Measuring Delay, Ri, Cpi

a. If you measure delay for NO-LOAD, then you get the no-load delay.

b. Add a fixed load, then measure the delay. Subtract the no-load delay, and you get the load delay.

c. The load capacitance can be measured since it is a static value. Once the load capacitance is known, you can calculate the Ri value. Once the Ri value is known, you can calculate the Cpi value.

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Delay MeasurementWe will use 30% to 70% points for delay measurement, but 50%-50% can also be used.

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Improving Average Delay†

A question: Should the DC switching point of a static CMOS gate always be set at Vdd/2? Recall the DC switching characteristic of a static Inverter

Vin

Vout

Vdd/2

Vdd/2

Increasing P/N ratios

High Skew (4/1) favors rising outputs,decreased Tplh

low Skew (1/1) favors falling outputs, decreased Tphl

Normal Skew, balanced Tplh, Tphl

†Harris ’97 Notes for these slides

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Gate Sizes and Skew

2/1 2/2 4/1Normal Skew

4/1 4/2 8/1High Skew

1/1 1/2 2/1Low Skew

Use skewed gates when trying to speed up a particular output transition along a critical path.

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Minimum Average Delay

What should the skew be to minimize average delay in a string of inverters driving a load?

(width)

1

Consider one inverter driving a fanout f load.

(Cin of inverter

= 1 + )

f*(1+ )

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Minimum Average Delay (cont)

Average delay = (Tplh + Tphl)/2

Recall RC model time model:

Tp = Tnoload + K*Cload

where is K is inversely proportional to channel width (represents channel resistance).

We can ignore Tnoload for this analysis.

Tphl (falling delay) proportional to 1*f (1 + )

Tplh (rising delay) proportional to k/ *f (1 + ) where ‘k = B’ for the case of Tplh = Tphl. ‘k’ accounts for differences in P/N mobility.

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Minimum Average Delay (cont)

Average delay = (Tplh + Tphl)/2

= (k/ *f (1 + ) + f (1 + ) )/2

= f (1 + ) (k/ + 1)/2

To find best value for , take derivative and set to 0:

d delay/d = f/2 (1 - k/ 2) = 0

= sq_root(k ) !!!

1.4/1 Minimum average delay

Trades off some Tplh time for overall decreased loading. Saves power as well!

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Minimum Average Delay

1.4/1 2/2 2/1Min average delay

These gates sized for minimum average delay.

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Topology Selection

Which is better? We have seen that logical effort may be able to help us make this choice, but usually simulation is needed. Right choice is technology dependent!!!!

Cin=C

Option #18C

Option #2

8C

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Critical Inputs

In general, late arriving inputs should drive inputs that are close to the output, early arriving inputs should drive inputs that are close to the rail. For example – in a full adder cell, carry input should be close to output (Fig 11-6 pg 567, Rabaey).

A B

S

CiCo

A B

S

CiCo

A B

S

CiCo

A B

S

CiCo Cin

A(0)

Cout

B(0)A(1) B(1)A(2) B(2)A(3) B(3)

C(0)C(1)C(2)C(3)C(4)

Sum(0)Sum(1)Sum(2)Sum(3)

4-bit ripple adder.

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If Arrival times are unknown....

If arrival times are unknown, and you need to fold the transistors anyway, can use the following trick:

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Stack Tapering

Increasing width of transistors near rail can improve delay. Benefits at sub-micron geometries are somewhat marginal.

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Summary of Static CMOS Features

• Very robust – i.e, “almost idiotproof” (Harris quote!)

• Very low DC leakage (nearly zero)

• Low AC power

• Scales well to low voltage

• Handled well by synthesis tools and simulators

• Well understood

Should be the default case for logic implementation unless special needs dictate some other family.