4.Draw the circuit for 3-to-8 line decoder.3-to-8 Decoder

A 3 to 8 decoder consists of three inputs and eight outputs, truth table and symbols of which is shown below.

Truth Table

X Y Z F0 F1 F2 F3 F4 F5 F6 F70 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

Symbol

From the truth table we can draw the circuit diagram as shown in figure below.

Circuit for 3 to 8 line decoder.

4.Explain the working of the modems?

As we know that the computers can’t understand our language. Computers understand the language of 0’s and 1’s i.e. digital form. The modem will modulate the signal into a sine wave. So, this modulated digital signal can easily run over the telephone lines. Then the signal will reach the IP hub. After this the demodulation of the signal will take place into digital form. Then you will be connected to the internet. All these processes are performed by modem at extremely high speeds. The speed of the modem depends upon the number of the available access lines and the technology of the modem.

Today’s the modems are of very high speeds. But some people are still using the slow speed modems having speed nearly 56kbps.The features of modem are discussed below:

1. The speed of the modem is measured in bps means bits per second. Data transfer speed can be increased by using the technique of data compression.

2. If we are using a modem having auto answering facility. Then our modem will be able to attend calls even in our absence.

3. Modems work basically in two modes. One is voice mode and other is data mode. In voice mode modem acts like a simple telephone. But in data mode modem acts as a Simple modem. These types of modems have a switch which is helpful in changing the mode i.e. from voice mode to data mode and from data mode to voice mode. For voice communication, loudspeaker and a microphone is implemented in the modem.

4. Some modems have the ability to compress data. These modems compress data before sending to improve the data transfer rates. But there must be a similar technology modem to decompress the data at the receiver end.

5. There are basically three types of modems. All the three types are discussed in detail below:a) External Modemsb) Internal Modemsc) PCMCIA Modem

External Modems: A serial cable connection is needed to connect an external modem to a PC. These modems use their own power supplies. These modems have their independent controls.

Internal Modems: Internal modems are basically integrated on a chip. These are put up into the PCI slots of the computer. There is no need of any external power supply for internal modems. These modems use the power supply of the PC. Their installation in PC is quite very simple.

3.Write a short note on ADC.

Ans:An analog-to-digital converter is an electronic integrated circuit, which converterscontinuous signals to discrete digital numbers. The reverse operation is performed by a digital-to-analog converter.Typically, an adc is an electronic device that converter an input analog voltage to a digital number. The digital output may be using different coding schemes, such as binary, gray code or two’s complement binary. However, some non electronic or only partially electronic devices, such as rotary encoders, can also be considered ADCs. Resolution can also be defined electrically, and expressed in volts. The voltage resolution ofan ADC is equal to it’s over all voltage measurement range divided by the number of discrete intervals as in the formula:

Where:Q is resolution in volts per step (volts per output code).EFSR is the fu scale voltage = VRefHi – Vreflo and M is the ADC’s resolution in bits.The number of intervals is given by the number of available levels (output code),Which is: N = 2M.

Some example may help:Example 1:Full scale measurement range = 0 to 10 volts.ADC resolution is 12 bits: 212 = 4096 quantization level (codes)ADC voltage resolution is: (10V – 0V) / 4096 codes = 10V / 4096 codes 0.00244 volts/code2.44 mV/code.

9. Write a short note on Digital Versatile Disk.

DVD is also known as Digital Versatile Disk or Digital video disc, is an optical

disc storage media format, invented and developed by Philips, Sony, Toshiba,

and Panasonic in 1995. DVDs offer higher storage capacity than compact discs while

having the same dimensions.

Pre-recorded DVDs are mass-produced using molding machines that physically stamp

data onto the DVD. Such discs are known as DVD-ROM, because data can only be read

and not written nor erased. Blank recordable DVDs (DVD-R and DVD+R) can be

recorded once using a DVD recorderand then function as a DVD-ROM. Rewritable

DVDs (DVD-RW, DVD+RW, and DVD-RAM) can be recorded and erased multiple times.

DVDs are used in DVD-Video consumer digital video format and in DVD-

Audio consumer digital audio format, as well as for authoring AVCHD discs. DVDs

containing other types of information may be referred to as DVD data discs.

In 1993, two optical disc storage formats were being developed. One was the

Multimedia Compact Disc (MMCD), backed by Philips and Sony, and the other was the

Super Density (SD) disc, supported by Toshiba, Time Warner, Matsushita

Electric, Hitachi, Mitsubishi Electric, Pioneer, Thomson, and JVC.

Representatives of the SD camp approached IBM, asking for advice on the file system to

use for their disc as well as seeking support for their format for storing computer

data. Alan E. Bell, a researcher from IBM's Almaden Research Center got that request

and also learned of the MMCD development project. Wary of being caught in a repeat of

the costly videotape format war between VHSand Betamax in the 1980s, he convened a

group of computer industry experts, including representatives

from Apple, Microsoft, Sun, Dell, and many others. This group was referred to as the

Technical Working Group, or TWG.

The TWG voted to boycott both formats unless the two camps agreed on a single,

converged standard.[4] Lou Gerstner, president of IBM, was recruited to apply pressure

on the executives of the warring factions. Eventually, the computer companies won the

day, and a single format, now called DVD, was agreed upon. The TWG also

collaborated with the Optical Storage Technology Association(OSTA) on the use of their

implementation of the ISO-13346 file system (known as Universal Disc Format) for use

on the new DVDs.

Philips and Sony decided it was in their best interest to avoid another format war over

their Multimedia Compact Disc, and agreed to unify with companies backing the Super

Density Disc to release a single format with technologies from both. The specification

was mostly similar to Toshiba and Matsushita's Super Density Disc, except for the dual-

layer option (MMCD was single-sided and optionally dual-layer, whereas SD was single-

layer but optionally double-sided) and EFMPlus modulation.

EFMPlus was chosen because of its great resilience to disc damage, such as scratches

and fingerprints. EFMPlus, created by Kees Immink (who also designed EFM), is 6%

less efficient than the modulation technique originally used by Toshiba, which resulted in

a capacity of 4.7 GB, as opposed to the original 5 GB. The result was the DVD

specification, finalized for the DVD movie player and DVD-ROM computer applications in

December 1995.

The DVD Video format was first introduced by Toshiba in Japan in November 1996, in

the United States in March 1997 (test marketed),[5] in Europe in October 1998, and in

Australia in February 1999.

In May 1997, the DVD Consortium was replaced by the DVD Forum, which is open to all

other companies

10.Write a note on DAC types.

In electronics, a digital-to-analog converter (DAC or D-to-A) is a device that converts a digital (usually binary) code to an analog signal (current, voltage, orelectric charge). An analog-to-digital converter (ADC) performs the reverse operation.

DAC types

The most common types of electronic DACs are:

The pulse-width modulator, the simplest DAC type. A stable current or voltage is switched into a low-pass analog filter with a duration determined by the digital input code. This technique is often used for electric motor speed control, but has many other applications as well.

Oversampling DACs or interpolating DACs such as the delta-sigma DAC, use a pulse density conversion technique. The oversampling technique allows for the use of a lower resolution DAC internally. A simple 1-bit DAC is often chosen because the oversampled result is inherently linear. The DAC is driven with a pulse-density modulated signal, created with the use of a low-pass filter,step nonlinearity (the actual 1-bit DAC), and negative feedback loop, in a technique called delta-sigma modulation. This results in an effective high-pass filter acting on the quantization (signal processing) noise, thus steering this noise out of the low frequencies of interest into the megahertz frequencies of little interest, which is called noise shaping. The quantization noise at these high frequencies is removed or greatly attenuated by use of an analog low-pass filter at the output (sometimes a simple RC low-pass circuit is sufficient). Most very high resolution DACs (greater than 16 bits) are of this type due to its high linearity and low cost. Higher oversampling rates can relax the specifications of the output low-pass filter and enable further suppression of quantization noise. Speeds of greater than 100 thousand samples per second (for example, 192 kHz) and resolutions of 24 bits are attainable with delta-sigma DACs. A short comparison with pulse-width modulationshows that a 1-bit DAC with a simple first-order integrator would have to run at 3 THz (which is physically unrealizable) to achieve 24 meaningful bits of resolution, requiring a higher-order low-pass filter in the noise-shaping loop. A single integrator is a low-pass filter with a frequency response inversely proportional to frequency and using one such integrator in the noise-shaping loop is a first order delta-sigma modulator. Multiple higher order topologies (such as MASH) are used to achieve higher degrees of noise-shaping with a stable topology.

The binary-weighted DAC, which contains one resistor or current source for each bit of the DAC connected to a summing point. These precise voltages or currents sum to the correct output value. This is one of the fastest conversion methods but suffers from poor accuracy because of the high precision required for each individual voltage or current. Such high-precision resistors and current sources are expensive, so this type of converter is usually limited to 8-bit resolution or less.

The R-2R ladder DAC which is a binary-weighted DAC that uses a repeating cascaded structure of resistor values R and 2R. This improves the precision due to the relative ease of producing equal valued-matched resistors (or current sources). However, wide converters perform slowly due to increasingly large RC-constants for each added R-2R link.

The thermometer-coded DAC, which contains an equal resistor or current-source segment for each possible value of DAC output. An 8-bit thermometer DAC would have 255 segments, and a 16-bit thermometer DAC would have 65,535 segments. This is perhaps the fastest and highest precision DAC architecture but at the expense of high cost. Conversion speeds of >1 billion samples per second have been reached with this type of DAC.

Hybrid DACs, which use a combination of the above techniques in a single converter. Most DAC integrated circuits are of this type due to the difficulty of getting low cost, high speed and high precision in one device.

The segmented DAC, which combines the thermometer-coded principle for the most significant bits and the binary-weighted principle for the least significant bits. In this way, a compromise is obtained between precision (by the use of the thermometer-coded principle) and number of

resistors or current sources (by the use of the binary-weighted principle). The full binary-weighted design means 0% segmentation, the full thermometer-coded design means 100% segmentation.

3.Explain temperature and weather forecast system with a neat circuit diagram.

Assumptions/Design Criteria:

♦ The barometer will be operated indoors. This will minimize output variations caused

by temperature and will lengthen the calibration intervals. It also means the circuit

board will not have to be weatherproofed.

♦ Will be easy to calibrate. This means there will be a maximum of 1 calibration

adjustment.

♦ The operating range will be from 28.00 inHg to 32.00 inHg

♦ Resolution will be greater than .01 inHg from sea level to 10,000 feet.

♦ The interface will be standard Dallas Semiconductor 1-wire.

♦ Because the unit will be designed for indoor operation, it can be externally powered.

♦ Will utilize the Motorola MPX4115A pressure transducer.

Based on these assumptions, table 1 was generated. This table calculates the station

pressure for both the minimum (28.00) and the maximum (32.00) pressures for altitudes

from sea level to 10,000 feet in 1000 foot increments. The station pressure is then

converted to MPX4115A pressure sensor volts. Looking at the table, I discovered the

predominant change in altitude in the offset voltage of the pressure sensor. I decided

that this will be the adjustable parameter, and that the circuit gain would be fixed.

The OA Offset column is the op amp offset voltage that compensates for altitude. This

will be the only calibration variable. Since the instrumentation amplifier is a rail-to-rail

device, in theory it will operate down to 0 volts. However, to provide some margin, the

offsets were chosen to allow a minimum of .2 volts at the lowest pressure. The gain of

10 was chosen to allow maximum output voltage swing for all altitudes. The resulting op

amp output voltages are listed in OA Output c column. This is the voltage applied to the

DS2438 Vad input.

Circuit Design:

The following circuit design satisfies these requirements. I selected the INA122

instrumentation amp for several reasons: it eliminated several external resistors and it

provides a very stable gain over a wide temperature. It also provides excellent rail-to-rail

operation allowing full use of the 10 volt input range of the DS2438. The 40.2K ohm

resistor sets the gain to 10. The variable resistor allows adjustment of the offset voltage

from 2.0v to 4.0v. All parts are available from Digikey except the

pressure sensor, which is available from Newark.

Calibration:

Hardware calibration is simply a matter of setting the offset voltage to the value listed in

table 1 for your altitude. A jumper on the input of the DS2438 allows the use of the

DS2438 to measure the offset. Put the jumper in the A-C position and using the iButton

Viewer for the DS2438, set the voltage to the table value using the 25-turn pot. Once it’s

set, put the jumper in the A-B position to read pressure.For altitudes in between the values listed in the table, simple interpolation will give

accurate results. An Excel spreadsheet will be also available online to calculate

intermediate values.

Software:

Routines currently exist to measure the DS2438s Vad voltage. Once this voltage is

measured, the pressure is calculated using:

Press = slope * Vad + intercept

Where the slope and intercept are the values listed in table 1 for your altitude. The

prototype code I used had an external text file to store the slope and intercept values.

This allows the user to edit the file to fine-tune the calibration if desired.

Fine-tuning can be accomplished by monitoring the pressure and comparing it with a

known reference source, such as a nearby airport or NOAA weather. Start by adjusting

the intercept. When the reference station indicates a pressure near mid-scale (30.00

inHg), adjust the software intercept value until your weather station matches. Now

monitor the pressure extremes to determine if the slope needs adjustment. An Excel

spreadsheet will be available as an aid.

Future Options:

A fixed resistor could replace the variable resistor. This would eliminate any hardware

adjustments. The value would have to be calculated for a given altitude. Another

possibility is to use several DS2406 1-wire switches or a programmable potentiometer

to set the offset programmatically

10. Draw and explain the working of JK, S-R, and D flip flops.

Answer:- Each flip-flop stores a single bit of data, which is emitted through the Q output on the east side. Normally, the value can be controlled via the inputs to the west side. In particular, the value changes when the clock input, marked by a triangle on each flip-flop, rises from 0 to1; on this rising edge, the value changes according to the corresponding table below.

D Flip-Flop J-K Flip-Flop S-R Flip-Flop

Another way of describing the different behavior of the flip-flops is in English text.

• D Flip-Flop: When the clock rises from 0 to 1, the value remembered by the flip-flop becomes the value of the D input (Data) at that instant.

• J-K Flip-Flop: When the clock rises from 0 to 1, the value remembered by the flip-flop toggles if the J and K inputs are both 1, remains the same if they are both 0, and changes to the K input value if J and K are not equal. (The names J and K do not stand for anything.)

• R-S Flip-Flop: When the clock rises from 0 to 1, the value remembered by the flip-flop remains unchanged if R and S are both 0, becomes 0 if the R input (Reset) is 1, and becomes 1 if the S input (Set) is 1. The behavior in unspecified if both inputs are 1. (In Logisim, the value in the flip-flop remains unchanged.)

6. Draw and explain the operation of parallel-in-parallel-out shift register.

The purpose of the parallel-in/ parallel-out shift register is to take in parallel data, shift it, then output it as shown below. A universal shift register is a do-everything device in addition to the parallel-in/ parallel-out function.

Above we apply four bit of data to a parallel-in/ parallel-out shift register at DA DB DC DD. The mode control, which may be multiple inputs, controls parallel loading vs shifting. The mode control may also control the direction of shifting in some real devices. The data will be shifted one bit position for each clock pulse. The shifted data is available at the outputs QA QB QC QD . The "data in" and "data out" are provided for cascading of multiple stages. Though, above, we can only cascade data for right shifting. We could accommodate cascading of left-shift data by adding a pair of left pointing signals, "data in" and "data out", above.

The internal details of a right shifting parallel-in/ parallel-out shift register are shown below. The tri-state buffers are not strictly necessary to the parallel-in/ parallel-out shift register, but are part of the real-world device shown below.

The 74LS395 so closely matches our concept of a hypothetical right shifting parallel-in/ parallel-out shift register that we use an overly simplified version of the data sheet details above. See the link to the full data sheet more more details, later in this chapter.

LD/SH' controls the AND-OR multiplexer at the data input to the FF's. If LD/SH'=1, the upper four AND gates are enabled allowing application of parallel inputs DA DB DC DD to the four FF data inputs. Note the inverter bubble at the clock input of the four FFs. This indicates that the 74LS395 clocks data on the negative going clock, which is the high to low transition. The four bits of data will be clocked in parallel from DA DB DC DD to QA QB QC QD at the next negative going clock. In this "real part", OC' must be low if the data needs to be available at the actual output pins as opposed to only on the internal FFs.The previously loaded data may be shifted right by one bit position if LD/SH'=0 for the succeeding negative going clock edges. Four clocks would shift the data entirely out of our 4-bit shift register. The data would be lost unless our device was cascaded from QD' to SER of another device.

Above, a data pattern is presented to inputs DA DB DC DD. The pattern is loaded to QA QB QC QD . Then it is shifted one bit to the right. The incoming data is indicated by X, meaning the we do no know what it is. If the input (SER) were grounded, for example, we would know what data (0) was shifted in. Also shown, is right shifting by two positions, requiring two clocks.

The above figure serves as a reference for the hardware involved in right shifting of data. It is too simple to even bother with this figure, except for comparison to more complex figures to follow.

Right shifting of data is provided above for reference to the previous right shifter.

If we need to shift left, the FFs need to be rewired. Compare to the previous right shifter. Also, SI and SO have been reversed. SI shifts to QC. QC shifts toQB. QB shifts to QA. QA leaves on the SO connection, where it could cascade to another shifter SI. This left shift sequence is backwards from the right shift sequence.

Above we shift the same data pattern left by one bit.

There is one problem with the "shift left" figure above. There is no market for it. Nobody manufactures a shift-left part. A "real device" which shifts one direction can be wired externally to shift the other direction. Or, should we say there is no left or right in the context of a device which shifts in only one direction. However, there is a market for a device which will shift left or right

on command by a control line. Of course, left and right are valid in that context.

What we have above is a hypothetical shift register capable of shifting either direction under the control of L'/R. It is setup with L'/R=1 to shift the normal direction, right. L'/R=1 enables the multiplexer AND gates labeled R. This allows data to follow the path illustrated by the arrows, when a clock is applied. The connection path is the same as the"too simple" "shift right" figure above.Data shifts in at SR, to QA, to QB, to QC, where it leaves at SR cascade. This pin could drive SR of another device to the right.

5. Write a short note on J-K Master Slave Flip-Flop.

The Master-Slave JK Flip-Flop

The input signals J and K are connected to the gated "master" SR flip-flop which "locks" the input condition while the clock (Clk) input is "HIGH" at logic level "1". As the clock input of the "slave" flip-flop is the inverse (complement) of the "master" clock input, the "slave" SR flip-flop does not toggle. The outputs from the "master" flip-flop are only "seen" by the gated "slave" flip-flop when the clock input goes "LOW" to logic level "0". When the clock is "LOW", the outputs from the "master" flip-flop are latched and any additional changes to its inputs are ignored. The gated "slave" flip-flop now responds to the state of its inputs passed over by the "master" section. Then on the "Low-to-High" transition of the clock pulse the inputs of the "master" flip-flop are fed through to the gated inputs of the "slave" flip-flop and on the "High-to-Low" transition the same inputs are reflected on the output of the "slave" making this type of flip-flop edge or pulse-triggered.

Then, the circuit accepts input data when the clock signal is "HIGH", and passes the data to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip-flop is a "Synchronous" device as it only passes data with the timing of the clock signal.

7. List the fundamental logical gates.

Ans:The seven fundamental logic gates are:1. NOT (Inverter)2. AND3. NAND4. OR5. NOR6. XOR7. XNOR

8. Explain two way switches.

Ans: A switch is a mechanical device used to connect and disconnect a circuit at will. Switches cover a wide range of types, from subminiature up to industrial plant switching megawatts of power on high voltage distribution lines.

In applications where multiple switching options are required (e.g., a telephone service), mechanical switches have long been replaced by electronic switching devices which can be automated and intelligently controlled.

The switch is referred to as a "gate" when abstracted to mathematical form. In the philosophy of logic, operational arguments are represented as logic gates.The use of electronic gates to function as a system of logical gates is the fundamental basis for the computer –i.e A computer is a system of electronic switches which function as logic gates.There are tactical switches.major scale is inches.A railroad switch is not electrical, but a mechanical device to divert a train from one track to another.

In the simplest case, a switch has two pieces of metal called contacts that touch to make

a circuit, and separate to break the circuit. The contact material is chosen for its

resistance to corrosion, because most metals form insulating oxides that would prevent

the switch from working. Contact materials are also chosen on the basis of electrical

conductivity, hardness (resistance to abrasive wear), mechanical strength, low cost and

low toxicity.[1]

Sometimes the contacts are plated with noble metals. They may be designed to wipe

against each other to clean off any contamination. Nonmetallic conductors, such as

conductive plastic, are sometimes used.

Actuator

The moving part that applies the operating force to the contacts is called

the actuator, and may be a toggle or dolly, a rocker, a push-button, or any type of

mechanical linkage.

Contact arrangements

Triple Pole Single Throw (TPST or 3PST) knife switch used to short the windings of a 3 phase wind turbine for braking purposes. Here the switch is shown in the open position.

A pair of contacts is said to be "closed" when there is no space between them,

allowing electricity to flow from one to the other. When the contacts are separated by an

insulating air gap, an air space, they are said to be "open," and no electricity can flow at

typical voltages.

Switches can be and are classified according to the arrangement of their contacts in

electronics fields—but electricians in the electrical wiring service business and their

electrical supplier industries use different nomenclature, such as "one-way," "two-way,"

"three-way," and "four-way" switches—which have different meanings in North American

and British cultural regions as is delineated in the table below.

Some contacts are normally open (Abbreviated "n.o." or "no") until closed by operation

of the switch, while others are normally closed ("n.c." or "nc") and opened by the switch

action, where the abbreviations given are commonly used on electronics diagrams for

clarity of operation in assembly, analysis, or troubleshooting. The serve to synchronize

meaning with possible mistakes in wiring assembly, where wiring part of switch one way

and part another (usually opposite) way will pretty much guarantee things won't work as

designed.

A switch with both types of contact is called a changeover switch or "make-before-break"

switch contact, whereas most switches have a spring-loaded action that momentarily

disconnect the load and so are "break-before-make" types. The type of switch used

could be important, if for example, the switch selects two different power sources instead

of switching circuit loads, or the circuit load will not and cannot tolerate any interruption

in applied power.

The terms pole and throw are also used to describe switch contact variations. A pole is a

set of contacts, the switch's electrical terminals that are connected to and belong to a

single circuit, usually a load. A throw is one of two or more positions (the nomenclature

is also applied to rotary switches, which can have many 'throw' positions) that the switch

can adopt, which normally, but not always correspond to the number positions the switch

handle or rotor can take when connecting between the common lead of the switch and a

pole or poles. A throw position which connects no terminals (poles), has a mismatch

between positions and positions which connect terminals, but are quite useful to turn

things "Off" or for example, alternatively select between two scaled modes of operation.

(For example, Bright illumination, moderate illumination, no illumination.)

Switching a load on or off from two locations (for instance, turning a light on or off from

either end of a flight of stairs) requires two SPDT switches. There are two basic methods

of wiring to achieve this, and another not recommended.

In the first method, mains is fed into the common terminal of one of the switches; the

switches are then connected through the L1 and L2 terminals (swapping the L1 and L2

terminals will just make the switches work the other way round), and finally a feed to the

light is taken from the common of the second switch. A connects to B or C, D connects

to B or C; the light is on if A connects to D, that is, if A and D both connect to B or both

connect to C.

The second method is to join the three terminals of one switch to the corresponding

terminals on the other switch and take the incoming supply and the wire out to the light

to the L1 and L2 terminals. Through one switch A connects to B or C, through the other

also to B or C; the light is on if B connects to C; that is, if A connects to B with one switch

and to C with the other.

Wiring needed in addition to the mains network (not including protective earths):

First method:

Double wire between both switches

Single wire from one switch to the mains

Single wire from the other switch to the load

Single wire from the load to the mains

Second method:

Triple wire between both switches

Single wire from any position between the two switches, to the mains

Single wire from any position between the two switches, to the load

Single wire from the load to the mains

If the mains and the load are connected to the system of switches at one of them, then in

both methods we need three wires between the two switches. In the first method one of

the three wires just has to pass through the switch, which tends to be less convenient

than being connected. When multiple wires come to a terminal they can often all be put

directly in the terminal. When wires need to be joined without going to a terminal a

crimped joint, piece of terminal block, wire nut or similar device must be used and the

bulk of this may require use of a deeper back box.

7. Design the counter that goes through states 0,1,2,4,0…using D flip-flops.

6. Convert the following decimal numbers to base 2:

A.122

Ans: 1111010

B.98

Ans: 1100010

1. Convert the following binary numbers to base 10.

a. 10101101

Ans:173

b. 110110.1

Ans:54.5