c u s t o m e r rdb - community.nxp.com

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Table of Contents01 TITLE AND NOTES

RevisionsRev Description

X1

ApprovedDate

C U S T O M E R RDB

This schematic is provided for referencepurposes only. As such, NXP does not make anywarranty, implied or otherwise, as to thesuitability of circuit design or componentselection (type or value) used in theseschematics for hardware design using the NXPS32K family of Microprocessors. Customers usingany part of these schematics as a basis forhardware design, do so at their own risk andFreescale does not assume any liability for sucha hardware design.

User notes are given throughtout the schematics.

Specific PCB LAYOUT notes are detailed in ITALICS

- All components and board processes are to be ROHS compliant- All connectors and headers are denoted Jx/Px and are 2.54mm pitch unless otherwise stated- Jumper default positions are shown in the schematics. For 3 way jumpers, default is alwaysposn 1-2. - All switches are denoted SWx- All test points are denoted TPx

Notes:

C A U T I O N :

X-S32K148AVB-RDB

04 S32K148 MCU

03 POWER/CANFD/LIN02 BLOCK DIAGRAM

05 FLASH/DEBUG

07 SAI AUDIO

06 ETHERNET

Designer

Jeremy He

08 USER PERIPHERAL

Draft Jun Qiao 2020/3

A Release

AX1 2020/7Update nets and add two 4pin connector

REF DES JUMPER(DEFAULT) PAGE NAMEJ1,J9,J3,J4,J6 1-2 03. POWER/CANFD/LINJ10 2-3 03. POWER/CANFD/LINJ7 OPEN 03. POWER/CANFD/LINJ20 OPEN 07. SAI AUDIO

REF DES ASSY_OPT PAGE NAMEFL1 DNP 03. POWER/CANFD/LINC40,C33,C41,R44 DNP 04. S32K148 MCUR55,C54,R50,U4,QZ1,R69,R70,R71,R67,R53

DNP 05. FLASH/DEBUG

TPH1,R108,R110,R102,R78 DNP 06. ETHERNETR120,R122,R123,R163,R121 DNP 07. SAI AUDIO

REF DES SWITCH(DEFAULT) PAGE NAMESW1 OFF 03. POWER/CANFD/LINSW4 ON 08. USER PERIPHERAL

B Release

Drawing Title:

Size Document Number Rev

Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:

Automotive Product Group6501 William Cannon Drive WestAustin, TX 78735-8598

This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

ICAP Classification: CP: IUO: PUBI:

SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C

Tuesday, July 28, 2020

TITLE/NOTE

Jun Qiao

Jeremy He

Jun Qiao

1 8

____X____Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:




SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


TITLE/NOTE

Jun Qiao

Jeremy He

Jun Qiao

1 8

____X____Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:




SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


TITLE/NOTE

Jun Qiao

Jeremy He

Jun Qiao

1 8

____X____

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Drawing Title:


Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


BLOCK DIAGRAM

2 8

___ ___XDrawing Title:


Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


BLOCK DIAGRAM

2 8



Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


BLOCK DIAGRAM

2 8

___ ___X

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LPSPI1_SCKLPSPI1_PCS3

LPSPI1_SINLPSPI1_SOUT

LPUART1_TXLPUART1_RX

ISO 11898-2:201x (upcoming merged ISO11898-2/5/6) compliant 1 Mbit/s high-speedCAN transceiver supporting CAN FD activecommunication up to 2 Mbit/s in the CANFD data field

Mouting holes

Test and reference points

CAN2_TXCAN2_RX

RESET

FS6522 SBC48pins LQFP

SILK=CANHSILK=CANLSILK=GND

SILK=VSUPSILK=LINSILK=GND

VIN VSUP3

VSUP3

VSUP12

VAUX

VCAN

VPRE

VCORE

VCCA

P5V_AUDIO

P3V3_BRD

P3V3_MCU

P3V3_MCU

VPRE

P3V3_ENET P3V3_AUDIO

P3V3_MCU P3V3_BRD P3V3_MCU P3V3_BRD

P3V3_MCU

VBAT

PTB16 [4]PTB15 [4]

PTC9 [4]PTC8 [4]

PTA5 [4,5,6,8]

PTB17 [4]PTB14 [4]

PTE5 [4]

PTB12 [4]PTB13 [4]

ENETSW_INH[6]

Drawing Title:


Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


POWER/CANFD/LIN

3 8



Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


POWER/CANFD/LIN

3 8



Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


POWER/CANFD/LIN

3 8

___ ___X

R108.06K

C27

100pF

TP13

R643K

D7PESD1CAN-UX

1 23

R12 1k

TP5

C110.1uF

L4 1uH1 2

TP18

1

R42.4K

L1 22uH1 2

C26

100pF

J2 CON PWR 3SILK = 12V_IN

1

23

SH

1S

H2

R85.1K

TP37

R210

TP1

J10HDR 1X3

JUMPER(DEFAULT) = 2-3

1 2 3

TP19

1

J8

HDR 1X3

123

TP9

R98.06K

R22 5.1K

C154.7uF

TP7

D4

PMEG6045ETP

A C

TP8

C10.1uF

R150

R32 10K

R2760.4

C8

22uF10V

U1

MC33FS6522LAE

CAN_5V7

CANH8

IO_5/VKAM11 IO_410

GN

D_C

OM

6

CANL9

IO_012

LIN5

VS

UP

11

VS

UP

22

VSENSE3

VSUP34

FCRBM13

FS014

DEBUG15

AG

ND

16

MUX_OUT17

IO_218

IO_319

TXD20RXD21

TXDL22RXDL23

RST24

MISO25MOSI26

SCLK27

CS28

INT29

VDDIO30

SELECT31

FB

_CO

RE

32

CO

MP

_CO

RE

33

VCORE_SNS34

SW

_CO

RE

35

BO

OT

_CO

RE

36

VP

RE

37

VAUX38 VAUX_B39

VAUX_E40

VCCA_E41

VCCA_B42

VCCA43

GA

TE

_LS

44

DG

ND

45

BO

OT

_PR

E46

SW

_PR

E2

47S

W_P

RE

148

EP

49

R360

C232.2uF

+ C1347uF

C25

0.01uF

C7180PF

R11 62 K

J4HDR1X2


12

SW1

418121270801SWITCH(DEFAULT) = OFF

SILK = SBC_WAKE

1 2

R14 5.1K

TP12

R250

BH1

Mounting Hole

D5

GREEN LED

SILK = 3.3V

A C

C9

0.01uF

R190

C3

22uF10V

C194.7uF

C28

4700pF

C30220pF

R715

BH2

Mounting Hole

C240.01uF

D6

GREEN LED

SILK = 3.3V

AC

R370

C5

0.1uF

TP4

R2 5.1K

R330

J5

HDR 1X3

123

R300

EB

C

Q2

BCP52-16

1

32 4

BH3

Mounting Hole

R160

C290.01uF

C4

22uF10V

D2

BLUE LED

SILK = 5V

A C

TP14

R230

TP3

J1HDR1X2


1 2

D3PMEG4030ER

AC

C120.01uF

R350

C17 82pF

BH4

Mounting Hole

D8

PMEG2010BER

AC

J3HDR1X2


1 2

R2410K

TP10

TP2

C160.01uF

R170

C6

0.47uF

R3160.4

R3 1k

L3

BLM18KG121TZ1

1 2

C200.01uF

D1PMEG4030ER

AC

R290

L2 2.2uH1 2

TP36

TP11

C2470pF

J6HDR1X2


1 2

R340

R543K

FL1

ACT1210-510-2P-TL00DNP

1

2 3

4

R280

J7HDR1X2

JUMPER(DEFAULT) = OPEN

1 2

R392K

C10330pF

R131k

TP16

1

C220.01uF

TP15

R200

TP6

J9HDR 1X3


1 2 3

C181uF

R115

C214.7uF

R402K

R3811kOhms

C144.7uF

EB

C

Q1BCP52-161

324

R265.1K

R180

TP17

1

SBC_SPI_MOSI

SBC_SPI_CS

SBC_SPI_MISOSBC_SPI_CLK

SBC_MUX_OUT

SBC_INT

SBC_LINTXSBC_LINRXSBC_CANTXSBC_CANRX

CAN_HCAN_L

SPLITSBC_CANL

SBC_CANH

SBC_LIN

SBC_RESET

SBC_WAKESBC_FCRBM

SBC_FS0

SBC_DEBUG

SBC_WAKE

SBC_FCRBM

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

S32K148 Microcontroller100pins LQFP

MII_TXD2

MII_RXD2

MII_TX_CLKMII_TX_EN

MII_TXD1MII_RXD3

MII_TXD3

MII_TX_ERMII_TXD0MII_RXD0MII_RXD1

MII_RX_DV

CAN2_TXCAN2_RX

MII_RX_ER

AUDIO_I2C_SCLAUDIO_I2C_SDA

RTC_I2C_SDARTC_I2C_SCL

JTAG_TMS/SWD_DIO

JTAG_TDO

JTAG_TDIJTAG_TCLK/SWD_CLK

SBC_SPI_CS

SBC_SPI_MISOSBC_SPI_CLK

SBC_SPI_MOSI

FLASH_SI

FLASH_SO

FLASH_CS

FLASH_CLK

FLASH_WP

EXTALXTAL

SBC_INT

SAI0_D3

SAI0_BCLKSAI0_SYNC

SAI0_D0

SAI0_MCLK

MII_RX_CLK

ENET_MDIOENET_MDC

ENET_INT

USER_BUTTONUSER_BUTTON

SBC_UART_RXSBC_UART_TX

ENET_TMR0

LEDRGB_BLUE

LEDRGB_REDLEDRGB_GREEN

USER SWITCHUSER SWITCHRESET

RTC_INT

ENET_WAKE

ENET_LED

AMP_SDRAMP_SDL

XTAL

FLASH_GPIO_RESET

ENET_GPIO_RESET

DEBUG_UART_RXDEBUG_UART_TX

HEADERHEADER

HEADER

HEADERENET_TMR0_DET

VDDA_MCU

P3V3_MCU

PTD5 [6]PTD6 [6]PTD7 [6]PTD8 [6]PTD9 [6]PTD10 [6]PTD11 [6]PTD12 [6]

PTC0 [6]PTC1 [6]PTC2 [6]

PTC3 [6]

PTC16 [6]PTC17 [6]

PTA6[8]PTA7[8]

PTE4[5,8]PTE5[3]

PTC6 [8]PTC7 [8]

PTB12[3]PTB13[3]

PTA2[7]PTA3[7]

PTE0[5]PTE1[5]

PTB6[4]PTB7[4]

PTA4[5]

PTA10[5]

PTC4 [5]PTC5 [5]

PTA5[3,5,6,8]

PTB15[3]PTB16[3]

PTB14[3]

PTB17[3]

PTE15[5]PTE16[5]

PTA8[5]PTA9[5]

PTE11[5]

PTC11 [7]

PTB11[8]

PTB9[8]PTB10[8]

PTA11[7]PTA12[7]PTA13[7]PTA14[7]

PTD1 [7]

PTD15 [6,8]PTD16 [8]

PTD0 [8]

PTB4[6]PTB5[6]

PTE8[6]

PTC12 [8]PTC13 [8]

PTC8 [3]PTC9 [3]

PTD14 [7]

PTD2 [8]PTD3 [8]PTD4 [8]

PTA0[8]PTA1[8]

PTA15[7]PTA16[7]

PTE2[8]PTE3[8]

PTB6 [4]PTB7 [4]

PTD13 [6]

PTE9[6]

PTA17[5]PTB0[5]PTB1[5]

PTB2[7]PTB3[8]

PTB8[8]

PTE6[8]PTE7[8]

PTE10[8]

PTE12[8]PTE13[8]PTE14[8]

PTC10 [8]

PTC14 [8]PTC15 [8]

PTD17 [8]

Drawing Title:


Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


S32K148 MCU

4 8



Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


S32K148 MCU

4 8



Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


S32K148 MCU

4 8

___ ___X

C431000pF

R430

C440.1uF

R440DNP

C451000pF

TP20

U2

FS32K148UJT0VLLR

PTA0/FTM2_CH1/LPI2C0_SCLS/FXIO_D2/FTM2_QD_PHA/LPUART0_CTS/TRGMUX_OUT3/ADC0_SE0/CMP0_IN079

PTA1/FTM1_CH1/LPI2C0_SDAS/FXIO_D3/FTM1_QD_PHA/LPUART0_RTS/TRGMUX_OUT0/ADC0_SE1/CMP0_IN178

PTA2/FTM3_CH0/LPI2C0_SDA/EWM_OUT_B/FXIO_D4/LPUART0_RX/ADC1_SE073

PTA3/FTM3_CH1/LPI2C0_SCL/EWM_IN/FXIO_D5/LPUART0_TX/ADC1_SE172

PTA4/CMP0_OUT/EWM_OUT_B/JTAG_TMS/SWD_DIO98

PTA5/TCLK1/RESET_B97

PTA6/FTM0_FLT1/LPSPI1_PCS1/FTM5_CH5/LPUART1_CTS/ADC0_SE258

PTA7/FTM0_FLT2/FTM5_CH3/RTC_CLKIN/LPUART1_RTS/ADC0_SE357

PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3/FTM4_FLT1100

PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2/FTM1_FLT3/FTM4_FLT099

PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO/NOETM_TRACE_SWO92

PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC91

PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/FTM2_QD_PHB/SAI0_BCLK90

PTA13/FTM1_CH7/CAN1_TX/LPI2C1_SCLS/FTM2_QD_PHA/SAI0_D089

PTA14/FTM0_FLT0/FTM3_FLT1/EWM_IN/FTM1_FLT0/SAI0_D388

PTA15/FTM1_CH2/LPSPI0_PCS3/LPSPI2_PCS3/FTM7_FLT0/ADC1_SE1283

PTA16/FTM1_CH3/LPSPI1_PCS2/ADC1_SE1382

PTA17/FTM0_CH6/FTM3_FLT0/EWM_OUT_B/FTM5_FLT062

PTB0/LPUART0_RX/LPSPI0_PCS0/LPTMR0_ALT3/CAN0_RX/FTM4_CH6/ADC0_SE4/ADC1_SE1454

PTB1/LPUART0_TX/LPSPI0_SOUT/TCLK0/CAN0_TX/FTM4_CH5/ADC0_SE5/ADC1_SE1553

PTB2/FTM1_CH0/LPSPI0_SCK/FTM1_QD_PHB/TRGMUX_IN3/ADC0_SE648

PTB3/FTM1_CH1/LPSPI0_SIN/FTM1_QD_PHA/TRGMUX_IN2/ADC0_SE747

PTB4/FTM0_CH4/LPSPI0_SOUT/MII_RMII_MDIO/TRGMUX_IN1/QSPI_B_IO028

PTB5/FTM0_CH5/LPSPI0_PCS1/LPSPI0_PCS0/CLKOUT/TRGMUX_IN0/MII_RMII_MDC27

PTB6/LPI2C0_SDA/XTAL16

PTB7/LPI2C0_SCL/EXTAL15

PTB8/FTM3_CH0/SAI1_BCLK77

PTB9/FTM3_CH1/LPI2C0_SCLS/SAI1_D076

PTB10/FTM3_CH2/LPI2C0_SDAS/SAI1_MCLK75

PTB11/FTM3_CH3/LPI2C0_HREQ74

PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX/FTM6_FLT1/ADC1_SE768

PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX/FTM6_FLT0/ADC1_SE8/ADC0_SE867

PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE966

PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE1465

PTB16/FTM0_CH4/LPSPI1_SOUT/ADC1_SE1564

PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT163

PTC0/FTM0_CH0/LPSPI2_SIN/MII_RMII_RXD[1]/MII_RMII_RXD[0]/FTM1_CH6/QSPI_B_RWDS/ADC0_SE840

PTC1/FTM0_CH1/LPSPI2_SOUT/MII_RMII_RXD[1]/MII_RMII_RXD[0]/FTM1_CH7/QSPI_B_SCK/ADC0_SE939

PTC2/FTM0_CH2/CAN0_RX/LPUART0_RX/MII_RMII_TXD[0]/ETM_TRACE_CLKOUT/QSPI_A_IO3/ADC0_SE10/CMP0_IN530

PTC3/FTM0_CH3/CAN0_TX/LPUART0_TX/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3/ADC0_SE11/CMP0_IN429

PTC4/FTM1_CH0/RTC_CLKOUT/EWM_IN/FTM1_QD_PHB/JTAG_TCLK/SWD_CLK/CMP0_IN296

PTC5/FTM2_CH0/RTC_CLKOUT/LPI2C1_HREQ/FTM2_QD_PHB/JTAG_TDI95

PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2/FTM1_QD_PHB/ADC1_SE481

PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3/FTM1_QD_PHA/ADC1_SE580

PTC8/LPUART1_RX/FTM1_FLT0/FTM5_CH1/LPUART0_CTS56

PTC9/LPUART1_TX/FTM1_FLT1/FTM5_CH0/LPUART0_RTS55

PTC10/FTM3_CH4/TRGMUX_IN1152

PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN1051

PTC12/FTM3_CH6/FTM2_CH6/LPUART2_CTS50

PTC13/FTM3_CH7/FTM2_CH7/LPUART2_RTS49

PTC14/FTM1_CH2/LPSPI2_PCS0/MII_COL/TRGMUX_IN9/ADC0_SE1246

PTC15/FTM1_CH3/LPSPI2_SCK/MII_CRS/TRGMUX_IN8/QSPI_B_CS/ADC0_SE1345

PTC16/FTM1_FLT2/CAN2_RX/LPI2C1_SDAS/MII_RMII_RX_ER/QSPI_B_IO7/ADC0_SE1444

PTC17/FTM1_FLT3/CAN2_TX/LPI2C1_SCLS/MII_RMII_RX_DV/QSPI_B_IO6/ADC0_SE1543

PTD0/FTM0_CH2/LPSPI1_SCK/FTM2_CH0/ETM_TRACE_D0/FXIO_D0/TRGMUX_OUT14

PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK/FXIO_D1/TRGMUX_OUT23

PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/TRGMUX_IN5/ADC1_SE271

PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/TRGMUX_IN4/NMI_B/ADC1_SE370

PTD4/FTM0_FLT3/FTM3_FLT3/ADC1_SE669

PTD5/FTM2_CH3/LPTMR0_ALT2/FTM2_FLT1/MII_TXD3/TRGMUX_IN7/QSPI_B_IO233

PTD6/LPUART2_RX/FTM2_FLT2/MII_TXD2/QSPI_B_IO1/CMP0_IN732

PTD7/LPUART2_TX/FTM2_FLT3/MII_RMII_TXD[1]/ETM_TRACE_D0/QSPI_A_IO1/CMP0_IN631

PTD8/LPI2C1_SDA/MII_RXD3/FTM2_FLT2/FXIO_D1/FTM1_CH4/QSPI_B_IO542

PTD9/LPI2C1_SCL/FXIO_D0/FTM2_FLT3/MII_RXD2/FTM1_CH5/QSPI_B_IO441

PTD10/FTM2_CH0/FTM2_QD_PHB/ETM_TRACE_D3/MII_RX_CLK/CLKOUT/QSPI_A_SCK36

PTD11/FTM2_CH1/FTM2_QD_PHA/ETM_TRACE_D2/MII_RMII_TX_CLK/LPUART2_CTS/QSPI_A_IO035

PTD12/FTM2_CH2/LPI2C1_HREQ/ETM_TRACE_D1/MII_RMII_TX_EN/LPUART2_RTS/QSPI_A_IO234

PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUT25

PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUT24

PTD15/FTM0_CH0/ETM_TRACE_D3/LPSPI0_SCK/ENET_TMR222

PTD16/FTM0_CH1/ETM_TRACE_D2/LPSPI0_SIN/CMP0_RRT/ETM_TRACE_CLKOUT21

PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT120

PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/LPSPI1_SOUT/FTM1_FLT2/SAI0_D294

PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/LPSPI1_PCS0/FTM1_FLT1/SAI0_D193

PTE2/LPSPI0_SOUT/LPTMR0_ALT3/FTM3_CH6/LPUART1_CTS/SAI1_SYNC/ADC1_SE1085

PTE3/FTM0_FLT0/LPUART2_RTS/FTM2_FLT0/TRGMUX_IN6/CMP0_OUT18

PTE4/ETM_TRACE_D1/FTM2_QD_PHB/FTM2_CH2/CAN0_RX/FXIO_D6/EWM_OUT_B9

PTE5/TCLK2/FTM2_QD_PHA/FTM2_CH3/CAN0_TX/FXIO_D7/EWM_IN8

PTE6/LPSPI0_PCS2/FTM7_FLT1/FTM3_CH7/LPUART1_RTS/ADC1_SE1184

PTE7/FTM0_CH7/FTM3_FLT059

PTE8/FTM0_CH6/MII_RMII_MDC/CMP0_IN326

PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR323

PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4/TRGMUX_OUT46

PTE11/LPSPI2_PCS0/LPTMR0_ALT1/FTM2_CH5/FXIO_D5/TRGMUX_OUT55

PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT019

PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT07

PTE14/FTM0_FLT1/FTM2_FLT117

PTE15/LPUART1_CTS/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2/TRGMUX_OUT62

PTE16/LPUART1_RTS/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3/TRGMUX_OUT71

VDD_110

VDD_238

VDD_361

VDD_487

VDDA11

VREFH12

VREFL13

VSS_114

VSS_237

VSS_360

VSS_486

C3310uFDNP

R410

C460.1uF

Y1

8MHZ

12

C471000pF

C480.1uF

C3812pF

C491000pF

C3910uF

C3712pF

C350.1uF

C4010uFDNP

C3410uF

C310.1uF

L5

BLM18KG121TZ1

1 2

TP21

C361000pF

C4110uFDNP

R420

C321000pF

C420.1uF

VREFH_MCU

XTALEXTAL

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ARM JTAG 10-PIN

JTAGJTAGJTAG

JTAG

S32K148 Debugg Connector20-pin Cortex Debug D ETM connector

FLASH_RESET

LPSPI2_SOUT

LPSPI2_PCS0

LPSPI2_SIN

LPSPI2_SCK

FLASH_WP

FLASH Memory 128M-BIT

RESET

LPI2C1_SDA

LPI2C1_SCL

PCA85063A Device Address = 0x51

RTC (NOT POPULATED)

FLASH_GPIO_RESET

SILK=GND

SILK=RXSILK=TX LPUART0_TX

LPUART0_RX

UART 3-PIN

P3V3_BRD

P3V3_MCU

P3V3_BRD

P3V3_BRD

PTA4 [4]PTC4 [4]PTA10 [4]PTC5 [4]PTA5 [3,4,5,6,8]

PTA8[4]PTE16[4]

PTE11[4]PTA5[3,4,5,6,8]

PTA9[4]

PTE15[4]

PTE0[4]

PTE1[4]

PTE4[4,8]

PTB0 [4]PTB1 [4]

PTA17 [4]

Drawing Title:


Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


FLASH/DEBUG

5 8



Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


FLASH/DEBUG

5 8



Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


FLASH/DEBUG

5 8

___ ___X

R53

DNP10K

U4

PCA85063ATTDNP

OSCI1

OSCO2

INT3

VS

S4

SDA5

SCL6

CLKOUT7

VD

D8

R4510K

TP24

R48 33

R674.7KDNP

C5010uF

R59 0

R63 0

C510.1uF

R5410K

R49 33

C521000pF

J19

HDR 1X3

123

R55

DNP10K

R68 4.7K

R60 0

R5610K

R640

MX25L12833FM2Q-10G

U3

CS1

SO/SIO12

WP/SIO23

GN

D4

SI/SIO05

SCLK6

RESET/SIO37

VC

C8

R51 33

R5710K

TP22

R5810K

R69 0DNP

L6

BLM18KG121TZ1

1 2

R61 0

J11

HDR 2X5

1 23 4

657 89 10

R6510K

C530.1uF

C540.1uFDNP

R46 33

R52 33

R70 0DNP

TP23

R66 4.7K

R47 33

QZ132.768KHZ

DNP

21

R62 0

R71 0DNP

R50 33DNP

JTAG_TMSJTAG_TCLKJTAG_TDOJTAG_TDIJTAG_RESET

VCC_FLASH

FLASH_SIFLASH_SOFLASH_WPFLASH_RESET

FLASH_CS

FLASH_CLK

RTC_I2C_SDARTC_INT

RTC_I2C_SCL

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Place 0.1uF near pins 11 and 14

Place 0.47uF near pin 7

Place 0.1uF near VDDIO Pins

PULL UP as Master,PULL DOWN as Slave

00 = Normal MII mode01 = RMII mode(external 50MHz oscillator)10 = RMII mode (external 25MHz crystal)11 = Reverse MII mode

PHY Address 00010b

Autonomous operation

PHY Address is 00010b

ETHERNET

ENET_LED

ENET_GPIO_RESET

SILK=P+

SILK=P-

SILK=P+

SILK=P-

Place close to S32K148

GND

GND

GND

GND

GNDGND

P3V3_ENET P3V3_ENET

GND

P3V3_ENET

P3V3_ENET

P3V3_ENET

VSUP3

P3V3_ENET

P3V3_ENET

P3V3_ENET

P3V3_ENET

P3V3_ENET

PTB4[4]PTB5[4]

ENETSW_INH [3]PTD13 [4]

PTD5[4]PTD6[4]PTD7[4]

PTD8[4]PTD9[4]

PTD10[4]

PTD11[4]

PTD12[4]

PTC16[4]PTC17[4]

PTC0[4]PTC1[4]

PTC2[4]

PTC3[4]

PTA5[3,4,5,8]

PTE8[4]

PTE9 [4]

PTD15[4,8]

Drawing Title:


Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


ETHERNET

6 8



Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


ETHERNET

6 8



Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


ETHERNET

6 8

___ ___X

C58

0.1uF

R81

4.7K

R1114.7K

C95

0.01uF

L10

BLM18KG121TZ1

1 2

C63

0.47uF

R103 0

R86 0 C650.1uF

C610.1uF

R72 1k

U6B

9-2304372-9

34

6785

R97 0

R824.7K

R87 0

R91

1k

R98 0

L8

BLM18KG121TZ1

1 2

R102

4.7KDNP

R104

100K

J12

TB_1X2

A1

B2

R88 0

R99 0

R106 0

A B

R85 0

C57

0.1uF

R95 0

R101

4.7K

D12

1PS76SB21

AC

R100

4.7K

C62

0.47uF

A

B

R76

0

R1084.7KDNP

C56

22uF

R79 33

TPH1

1

SW6

430152050826SILK = ENET_WAKE

1234

A

B

R75

0

R74100K

R73

10K

L11

DLW43MH201XK2L

21

4 3

C640.1uF

R15910K

L9

BLM18KG121TZ1

1 2

TJA1101

U5

EN35

EP

37

CLK_IN_OUT20

GN

D26

INT2

INH10WAKE_IN_OUT

8

MDC1

MDIO36

RST3

RXC/REF_CLK25

RXD0/PHYAD024

RXD2/CONFIG022 RXD1/PHYAD123

RXD3/CONFIG121

RXDV/CRSDV/CONFIG218

RXER/CONFIG3/TXCLK17

TRX_M13

TRX_P12

TXC28

TXD033

TXD132

TXD231

TXD330

TXEN29 TXER34

SE

L_1V

84

VD

DA

_3V

37

VD

DA

_TX

111

VD

DD

_1V

816

VD

DD

_3V

315

VD

DIO

_119

VD

DIO

_227

VB

AT

9

XI6

XO5

VD

DA

_TX

214

Y2

25MHz

1

4

3

2

R1094.7K

C590.1uF

R77 0

R83 0

R93 0

R107 0

R105 0

C55

0.47uF

R89 0R90

1k

R94 0 C66 16pF

R1104.7KDNP

D9

GREEN LED

SILK = ENET_STA

A CC600.1uF

R92 0

R84 0

C68 16pF

R80 10K

R78 33DNP

C674700pF

R161

4.7K

R96 0

U6A

9-2304372-9

12

L7

BLM18KG121TZ1

1 2

R160100K

ENET_EN

ENET_WAKE

ENET_MDIOENET_MDC

VDD3V3_ENET

VDDD1V8_ENETVBAT_ENET

VDDIO_ENET

VDDA3V3_ENET

ENET_TRX_N

ENET_TRX_P

ENET_C_N

ENET_C_P

ENET_INT

MII_RX_DV

MII_RX_CLK

MII_TX_ER

MII_RX_ER

MII_RXD3MII_RXD2

ENET_P

ENET_N

MII_TX_ENMII_TXD0MII_TXD1MII_TXD2MII_TXD3MII_TX_CLK

ENET_J_P

ENET_RESET

ENET_J_N

ENET_U_NENET_U_P

MII_RXD0MII_RXD1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SAI I2S Audio

Headphone connection

Note: R1 only needed ifinternal BIAS_RESISTORsettings are not suitable.

External amplifier connection

Layout Notes�AGND (pin 7) should be "star"connected to the jack grounds for LINEIN andLINEOUT, and to the VAG capacitor ground.This node should via to the ground plane (orconnected to ground) at a single point.

Add the reference clock circuit by NXA07657,for S32K148 SAI module cannot generate MCLKclock for common used audio sample inSGTL5000, 2018.5.21

AMP_SDRAMP_SDL

LPI2C0_SCL

LPI2C0_SDA

SAI0_D0

SAI0_D3

SAI0_SYNC

SAI0_BCLK

SAI0_MCLK

SILK=AR+

SILK=AR-

SILK=AL+

SILK=AL-

GND

GNDGND

GNDGNDGNDGNDGNDGND

GND

P3V3_AUDIO

P3V3_AUDIO

P3V3_AUDIO

P3V3_AUDIO

GND

GND

GND

P5V_AUDIO

GND

P3V3_AUDIO

P5V_AUDIO

GND

GND

P3V3_AUDIO

PTD1 [4]

PTA2[4]

PTA3[4]

PTA15 [4]PTA16 [4]

PTA13[4]

PTA14[4]

PTA11[4]

PTA12[4]

PTC11 [4]PTD14[4]

PTB2[4]

Drawing Title:


Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


SAI AUDIO

7 8



Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


SAI AUDIO

7 8



Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


SAI AUDIO

7 8

___ ___X

+

-

P1

EM6022P

2

1

C72

0.1uF

C8816pF

C75 1uF

R123 10K DNP

L12

BLM18KG121TZ1

1 2

TP25

R128 0

C81 0.1uF

C78 1uF

R162 0

R120 10K DNP

R132 0

R126 4.7K

C851uF

C76 0.22uF

R138 0

C7010uF

R129 0

R1340

R133 0

PAM8404

U8

NC_16

SDL7

SDR8

NC_210

INR+16

INR-17

INL-19

INL+20

G11

OUTL+2

OUTL-5

OUTR-11

OUTR+14

G015

PV

DD

_13

PG

ND

_14

PG

ND

_212

PV

DD

_213

AV

DD

9

AG

ND

18

EP

21

R124 2.2KR

L

J16

AUD 4

SILK = OUT

1

2

3

4

C79 0.22uFC77

1uF

C86

0.1uF

C711uF

L13

BLM18KG121TZ1

1 2

R11610K

R136 0

R125 4.7K

C74

1uF

R11810K

R112 0

R11710K

+

C83 220UF

R11910K

C870.1uF

+

C84 220UF

R113 0

R122 10K DNP

J20HDR1X2

JUMPER(DEFAULT) = OPEN

1 2

Y3 12.288MHz

1

4

3

2

R137 22

J13

TB_1X2

A1

B2

R121 10K DNP

CS2100CP-CZZ

U9

VD

1G

ND

2

CLK_OUT3

AUX_OUT4CLK_IN

5

XTO6 XTI/REF_CLK7

AD0/CS8 SCL/CCLK9 SDA/CDIN

10

R163 0

DNP

C73

0.1uF

J15

TB_1X2

A1

B2

R135 10K

R115

1k

C82 10uF

U7

SGTL5000 32QFN

I2S_SCLK24

NC522

LINEIN_L14

CPFILT18

VD

DIO

20

NC419

SYS_MCLK21

I2S_DOUT25

I2S_DIN26

HP_L6

CTRL_DATA27

NC628

CTRL_CLK29

GN

D1

1

NC18

HP_R2

GN

D2

3

VD

DA

5

LINEOUT_L12

LINEOUT_R11

MIC15

NC317

LINEIN_R13

AG

ND

7

I2S_LRCLK23

VD

DD

30

CT

RL_

AD

R0_

CS

31

CT

RL_

MO

DE

32

HP_VGND4

NC29

VAG10

MIC_BIAS16

GN

D3-

PA

D33

R130 0

R1141k

R139 0

C69

0.1uF

C8916pF

R131 0

C80 1uF

R

L

J14

AUD 4

SILK = IN

1

2

3

4

R1270

AHPL

AHPRAHPGND

AMIC

ALIL

ALIR

VD

DD

_AU

DIO

AUDIO_I2S_DOUT

AUDIO_I2S_DIN

AUDIO_I2S_LRCLK

AUDIO_I2S_SCLK

AUDIO_SYS_MCLK

AUDIO_I2C_SDAAUDIO_I2C_SCL

AINL

AINR AOUTR+

AOUTR-

AOUTL+

AOUTL-

AUDIO_I2C_SDA

AUDIO_I2C_SCL

ENET_TMR0PLL_LOCK

VDDA_AUDIO

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RGB LED User buttons

MCU reset bottom

User switches

RESET

USER SWITCH

USER SWITCH

USER_BUTTON

USER_BUTTON

Unused I/O

SILK=GND

SILK=3.3VSILK=3.3V

SILK=GND

LEDRGB_BLUE

LEDRGB_GREEN

LEDRGB_RED

SILK=3.3V

SILK=PTB9SILK=PTB10

SILK=PTB3

SILK=PTB11

SILK=PTC6

SILK=PTC7

SILK=PTC10SILK=PTE2

SILK=PTC14

SILK=PTB8

SILK=PTE6

SILK=PTE7

SILK=PTE12

SILK=PTE13

SILK=PTD15

SILK=PTE14

SILK=PTD16SILK=PTD17SILK=PTE3SILK=PTE4

SILK=PTC15

SILK=PTE10SILK=PTD0SILK=VSUP3SILK=GND

SILK=PTA0SILK=PTA1SILK=VSUP3SILK=GND

4PIN I/O

P3V3_MCU

P3V3_BRD

P3V3_BRD

VCORE

P3V3_BRD P3V3_BRD

VSUP3

VSUP3

PTC12 [4]

PTC13 [4]

PTA5 [3,4,5,6]

PTD2[4]

PTD3[4]

PTD4[4]

PTB3 [4]

PTB8[4]PTB9 [4]PTB10[4]PTB11 [4]

PTC6[4]

PTC7 [4]

PTC10[4]PTC14[4] PTC15 [4]

PTD15[4,6] PTD16 [4]PTD17[4]PTE3[4]PTE4[4,5]

PTE6 [4]

PTE7[4]

PTE12 [4]

PTE13 [4]PTE14 [4]

PTE2[4]

PTA6 [4]

PTA7 [4]

PTE10 [4]PTD0 [4]

PTA0 [4]PTA1 [4]

Drawing Title:


Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


USER PERIPHERAL

8 8



Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


USER PERIPHERAL

8 8



Date: Sheet of

Page Title:


SCH-47237 PDF: SPF-47237 B

X-S32K148AVB-RDB

C


USER PERIPHERAL

8 8

___ ___X

R143 1k

R147 10K Q3PMBT3904

23

1

Q5PMBT3904

23

1

C940.1uF

R141 1k

D11

LED REDSILK = RST

A C

TP26

R149 10K

R14610K

TP33

TP30

TP35

R151 10K

R142 1k

ON

12

SW4

418121270802

SWITCH(DEFAULT) = ON

12 3

4

R148 33K

TP31

J22

HDR_1x4

1234

Q4PMBT3904

23

1

R158 0

SW2 430152050826

1 23 4

R150 33K

R157 1k

C910.1uF

R153 1k

D10

LED RED/GRN/BL

A2 C2

A1 C1

C3A3R144 1k

R140 1k

R152 33K

TP27 TP28

TP34

TP29

SW3 430152050826

1 23 4

R15510K

SW5

430152050826SILK = RESET

1 23 4

C920.1uF

R154 1k

R15610K

R14510K

J21

HDR_1x4

1234

C930.1uF

C900.1uF

J17

HDR_2X13

1 23 4

657 89 10

11 1213 1415 1617 1819 2021 2223 2425 26

TP32

LEDRGB_BLUE

LEDRGB_GREEN

LEDRGB_RED

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