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19

3C H A P T E R

The CMOS Inverter

Chapter Objectives

Review MOSFET device structure and basic operation.

Establish device models for MOSFET that are used forcircuit-level design. Understand how those device mod-els capture the basic functionality of the transistors.

Analyze a static CMOS inverter circuit, including itsvoltage transfer function and transient performance.

Apply the device models to compute both static anddynamic parameters for a static CMOS inverter using

hand calculations. Understand the sources of power dissipation in the

static CMOS inverter and compute power consump-tion.

3-1 CMOS Devices

In the last chapter, we enjoyed designing logic gates withperfect transfer characteristics and instantaneous transi-tions. While those switch-based gates are useful for learn-

ing how logical gates are implemented physically, theyregrettably remain unrealizable in practice. Since we mustuse real transistors to implement these switches, the non-idealities of those transistors prevent us from creatingideal gates. Nevertheless, the transistors do approximate

the ideal switch behavior, so transistor-based logic doesprovide a robust mechanism for digital computation.

This chapter takes the next step into the circuit domainwhere transistors serve as switches. This allows us todevelop a more realistic view of circuit behavior. We firstexamine the transistor devices themselves and then lookat how their behavior is modeled for circuit analysis. Thenwe use the transistor device models to take a deep look atthe CMOS inverter.

3-1-1 MOSFET Physical Structure

The MOS field-effect transistor (MOSFET) is the elec-tronic device behind the explosive growth in digital elec-tronics since 1970. We can deal with a MOSFET at severallayers of hierarchy. We are most interested in this bookwith the circuit view of a MOSFET, so we will forgo alengthy discussion of the underlying device physics. How-ever, circuit designers do deal with more than just circuitschematics; they also must create the layoutfor their cir-cuits. Layout refers to the drawing that represents how acircuit will be physically constructed. It usually consists ofmany overlapping polygons drawn in different colors and

patterns. Each color/pattern combination represents acertain layer that will be fabricated eventually on the IC.Layout is thus a birds-eye view of these layers. While wewill not delve too deeply into the device physics of theMOSFET, we will give a preview of the MOSFET struc-


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20 Chapter 3 The CMOS Inverter

ture by looking at its layout before we get to the devicemodels for MOS transistors.

The layout and cross section of a modern n-channelMOSFET are shown in Figure 31(a) and (b), respec-tively. Again, the layout view shows the transistor fromabove. The gateof the transistor is a film of n+polycrystal-line silicon (polysilicon or poly). Underlying the gate is the

gate oxide, which is a layer of thermally grown silicondioxide (SiO2). The gate oxide is visible in Figure 31(b),but it is obscured by the poly in the layout view of Figure31(a).

The MOSFET channelis formed under the polysilicongate between the two n+regions, as shown in Figure31(b). The channel is the location of all of the important

Figure 31: (a) Four-mask layout and (b) cross section of an integrated n-channel MOSFET.

deposited

oxide

field

oxide

n+ drain diffusion

drain

interconnect

p+

[ p-type ]

bulk

interconnect

Ldiff

gate contact

(a)

A

drain

contacts

bulk

contact

n+polysilicon gate

channel

active area

(thin oxide area)

polysilicon gate

contact

metal

interconnect

n+source diffusion

edge of

active area

source

interconnect

(b)

L

n+polysilicon gate

gate oxide

gate

interconnect

source contacts

drain

interconnectsource

interconnect

A

W


3/34

Section 3-1 CMOS Devices 21

action in a MOSFET. It appears in the layout as the regionwhere the poly overlaps the diffusion. The gate oxide isnot drawn in the layout but is instead inferred to exist overthis channel region. The channel lengthLof the MOSFETis defined in Figure 31(b) as the gap between the n +dif-fusions or as the horizontal width of the poly over the dif-fusion in the layout. On the layout in Figure 31(a), thechannel width Wof the MOSFET is defined as the widthof the active area overlaid by the poly. One n+diffusion iscalled the source, the other is called the drain. Since thesource and drain are physically indistinguishable due tothe MOSFETs symmetry, the potentials on the diffusionswill be the basis for differentiating the source from thedrain, as discussed in the next section. The source anddrain diffusions have a length Ldiffand the same width Was the channel in this transistor. Metal interconnectionsmake ohmic contacts to the gate, source, and drain. Inaddition, the underlying p-type bulk region (the substrateor a deep p-type diffusion) is contacted with a fourth metal

interconnection called the bulk. This substrate connectionoften is called a tap. Although the body connection isshown near the MOSFET in Figure 31, it does not neces-sarily need to be situated immediately next to the MOS-FET, nor is there always a specific body connectionassociated with every transistor. Instead, the substrate isconnected to the correct potential by multiple body (orwell) taps that provide the proper body voltage for all ofthe transistors that share that substrate. Since pMOSdevices, with p+source and drain diffusion, must reside inn-type silicon, they are placed in an n-well. The n-well issimply a deep (relative to the source/drain diffusion)region of n-type material that is large enough to accomo-

date the pMOS device(s) inside.The complexity and capability of MOS integrated cir-cuits have increased many orders of magnitude over thepast several decades. Many of these advances resultedfrom the scaling (or shrinking) of CMOS technology.Throughout most of the history of CMOS scaling, thebasic MOSFET has remained essentially the same. Mod-ern MOSFETs, however, have adopted more complicatedphysical structures in response to emerging changes to tra-ditional circuit-level characteristics. Since these changesresult for small devices, they often are calledshort-channeleffectsor deep-submicron effects in reference to the shortchannel length of deeply scaled devices. In this book, we

will use conventional models of long-channeltransistorsthat do not include the short-channel effects. A deepunderstanding of the fundamental long-channel MOSFETwill provide you with a firm foundation for incorporatingshort-channel behavior during additional study.

3-1-2 MOSFET Circuit Symbol and TerminalCharacteristics

Before introducing the currentvoltage characteristics ofthe MOSFET, it is helpful to have a symbol for this device.There are two common symbols for each MOSFET type.Figure 32 shows the circuit symbols and basic structurefor an n-channel MOSFET or nMOS ( shown inFigure 31) and for the complementary p-channel MOS-FETorpMOSthat has p+source and drain diffusions in ann-type bulk region. In this text, we will use the symbolswithout arrows for digital circuits. The cross sections forthe two MOSFETS have been rotated 90oin order to illus-trate the close correspondence between the symbols andthe physical structure.

The MOSFETs are oriented as they often appear in cir-cuit schematics: The drain for the n-channel MOSFETand the source for the p-channel MOSFET are on toptoward the positive voltage supply. Voltages between ter-

minals are labeled by an ordered pair of subscripts, such asVGS = VG VS. By IEEE convention, the reference direc-tions for currents are defined as positive into the deviceterminals. Since the drain current for the p-channel deviceis negative, it is convenient to use IDp> 0 (which is posi-tive) leaving the drain terminal.

As we mentioned before, the MOSFET is an inherentlysymmetrical device. It is therefore impossible to distin-guish between source and drain based on physical defini-tions (e.g., the source and drain are interchangeable). Wetherefore use the potentials at the sides of the MOSFETchannel as a basis for definining the source and drain. Forthe nMOS in Figure 32(a), the drain and source terminals

are selected so that VDS> 0, which is equivalent to definingthe source as the terminal with the lower potential. Asshown in Figure 32(b), the labeling convention is oppo-site that for the p-channel MOSFET. Its source and drainare identified so that VSD>0, which means its source isdefined as the terminal with the higherpotential.

The n-channel MOSFETs static (DC) terminal charac-teristics can be measured with voltage sources and amme-ters. Since the MOSFET is a four-terminal device, weneed to experiment and discover which voltages are mostimportant. Let us assume that VBS = 0 V. Since the voltagedifferences between the drain and source and the gate andsource are most important, we ground the source

(VS = 0 V) for convenience. Since the gate terminal is insu-lated, the only current of interest is that into the drain ter-minalIDn.

Figure 33(a) is a schematic of the circuit used to findthe drain currents functional dependence on the two volt-


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ages under our control: the gatesource voltage VGS andthe drainsource voltage VDS. The conventional way tograph the measured datais to plot a family of curves IDn(VGS, VDS), with VGSas a parameter. The drain-current ver-sus drainsource voltage curves for a selected set ofgatesource voltages are called the MOSFET drain char-acteristics.

Figure 33(b) shows simulated drain characteristics for

an n-channel MOSFET in a digital CMOS process.Although the voltage and current ranges can vary with thetechnology and device layout, the ranges in Figure 33(b)are typical for a 1 m technology (e.g., L = 1 m). In thisgraph, the drain current ID is measured as a function ofdrainsource voltage VDSfor seven gatesource voltages.

Several observations can be made from studying thedrain characteristics in Figure 33(b).

1. The MOSFET is cutoff (IDn = 0 A) for gatesourcevoltages that are less than some critical voltage, whichis defined as the threshold voltage VTnof the n-channeldevice. A typical value for the n-channel threshold

voltage in a long-channel transistor is VTn = 0.5 V(modern devices may have lower threshold voltages).The n+source and drain are isolated electrically untilsufficient voltage is applied to the gate to create an n-type inversion layer or channelbetween them.

2. The drain current is nearly independent of thedrainsource voltage once VDS>VGS VTn. In this

region of operation (called saturation)the MOSFETbehaves like a current source. Further study revealsthat the drain current in saturationis proportional tothe square of the gatesource voltage above threshold

. This can be seen from the ratios of draincurrent for VGS = 3 V and for VGS = 2 V. This constant-current behavior is exploited in both analog and digi-tal circuit design.

3. The region whereIDndepends on both VGS and VDSistermed the triode, or linear region.

The p-channel MOSFETs drain characteristics areshown in Figure 34. In this case, the source and n-typebulk terminals are both connected to a 3 V supply. Theeffect of varying the drain voltage and gate voltage on thedrain current can be investigated. The shape of the draincharacteristics are identical to those of the n-channelMOSFET if IDp(which is positive) is plotted against thesourcedrain drop VSD = 3 V VD as a function of thesourcegate voltage VSG = 3 V VG. Notice that the sub-

scripts on those voltages are backwards relative to thenMOS, so that VSG= VS VG. Do not let those reversedsubscripts or negative signs fool you. They have to be thatway to account for the fact that the pMOS source is at ahigher potential (whereas nMOS is at a lower potential)and current flows out of the pMOS drain (and into thenMOS drain). A little practice helps to sort this all out. A

Figure 32: (a) -channel MOSFET symbols and structure and (b) p-channelsymbols and structure.

n+

n+

p bulk or

body

drain

source

gate

(a) n-channel MOSFET

D

G

IDp

B

p+

p+

n bulk or

body

drain

gate

(b) p-channel MOSFET

source

+

_VSG

D

S

G

+

+

_VGS

IDn IDn

B

VSD>0

VDS>0

+

_VBS

+

_VSB

D

GB

S

S S

B

D

G

IDp

VGS VTn( )2


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Section 3-2 MOSFET Device Models for Use in Circuit Design 23

typical value for the p-channel threshold voltage in a long-channel technology is VTp= 0.5 V.

3-2 MOSFET Device Models for Use inCircuit Design

In the previous section, we developed the framework fordevice models for the MOSFET by showing the MOSFETstructure and circuit symbols. In this section, we will

present the device models that describe the currentvolt-age behavior of the MOSFETs, which we can use for cir-cuit design. We will start by deriving the n-channelMOSFET device models and then adapt the analysis to

the p-channel MOSFET.

3-2-1 Device Models for nMOSFETs

The drain-current equations for the cutoff, triode, and sat-uration regions of operation for an n-channel MOSFETare given in Eqs. (3.1) through (3.3).

Figure 33: n-channel MOSFET drain characteristics: (a) test circuit and (b) measurements of draincurrent as function of drainsource voltage, with gatesource voltage as a parameter for a typicalintegrated device. VGS = 0, 0.5, 1, 1.5, 2, 2.5, 3 V, for 0 V


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Figure 34: (a) Test circuit and (b) measured drain characteristicsof a p-channel MOSFET with the same geometric dimensions as then-channel device used for Figure 4.3. The negative of the draincurrent IDp(> 0) is plotted against the sourcedrain drop VSD, withthe sourcegate drop VSGas a parameter. The drain current for thep-channel is about half that of the n-channel device for identicalgeometries and complementary threshold voltages VTp= VTn=

0.5 V.

3 V

VG+

+

S

D

G B

ID(VSG,VSD)

(a)

(b)

IDp

VD

+

_

VSG

+

_

VSD

+

VSD = VSG VTp = VSG 0.5V

VSD (V)

IDp

(A)

(triode region)

(saturation region)

(cutoff region)

VSG= 3.0V

VSG= 2.5V

VSG= 1.5V

VSG= 1.0V

VSG

= 0, 0.5V

VSG= 2.0V

32100

20

40

60

80

100

120


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For VGS VTn the nMOS is in cutoff, so its current is

(3.1)

For , the nMOS is in the trioderegion with current:

(3.2)

For , the nMOS is in satura-tion:

(3.3)

The equations match the behavior that we observed inthe nMOS drain characteristics in Figure 33. For the cut-off region, when the gatesource voltage is below thethreshold voltage, the device conducts essentially zerocurrent, as in Eq. (3.1). As the gatesource voltage rises,carriers in the p-type region under the gate oxide arerepelled from the gate, creating a depletion region underthe gate. Once the gatesource voltage exceeds the thresh-old voltage, the depletion region ceases to widen, andelectrons from the source enter the channel region, pro-ducing a very thin n-layer at the Si-SiO2interface (whichis called the channel). This channel acts as a conductorbetween the n-type source and drain terminals, and thevoltage from the drainsource creates an electric field inorder to drift the electrons through the channel. In the tri-

ode region, the current increases with the drainsourcevoltage according to Eq. (3.2). Once the drain-to-sourcevoltage exceeds the gate overdrive, VGSVTn, the channelbecomes pinched off at the drain end, so current becomesnearly constant with additional VDS. This voltage is called

, where VDS =VGS VTn. Equation (3.3) captures thebehavior of the current in saturation. The factor (1 +nVDS) in Eq. (3.3) models the remaining dependence ofcurrent on VDSin saturation, which results from channel-length modulation. Channel-length modulation refers tothe movement of the pinch-off point near the drain, caus-ing a change in the effective channel length. This descrip-tion of the physics underlying the MOSFET current

equations is about as brief as possible. For further investi-gation of the device physics, read module V.

The channel-length modulation term is included in Eq.(3.2) to prevent a discontinuity in the drain current whenVDS = = VGS VTn. Channel-length modulation canbe neglected in the triode region for hand calculations,

since the drain voltage Vis relatively small and the effecthas no practical significance.

Since the bulk voltage does not appear explicitly inthese equations, it is easy to forget that the nMOS transis-tor has a fourth terminal. The drain current actually doesdepend on the bulk voltage, but indirectly through thethreshold voltage. That is a higher-order effect that we willnot describe in this book. In this text, we will assume thatVTn is a technology-dependent constant and that VB forany nMOS device is tied to VSS. Since VSS is the lowestvoltage in the circuit, this ensures that the p and n-diodesbetween the bulk and source/drain never are forwardbiased (which could cause damage due to large currents).

Of the various terms in Eqs. (3.1) through (3.3), thegate oxide capacitance Cox can be found directly frommeasurements of the gate-oxide thickness tox. The otherterms cannot be measured directly, but experimentalvalues for VTn, n, and ncan be derived by extracting theparameters from the measured drain characteristics.

Although the equations are to some extent simplificationsof reality, their grounding in the physics of the MOSFETprovides us with insight into how it will behave under dif-ferent scenarios. They are therefore a significant improve-ment over an alternative fitted curve (e.g., polynomial fit).

At first glance, the ratio W/L in the device currentequations can be read directly from the device layout.However, the channel length often is designed as the min-imum allowed dimension in the fabrication technology.Since the channel length is in the denominator, smallerrors in L can lead to substantial errors in W/L.Figure 35 illustrates the need to be precise in specifyingthe channel length for the MOSFET. The as drawn

channel length Lmask on the layout becomes the asetched length Lgateof the polysilicon gate due to system-atic lithography and etching effects. Finally, the ion-implanted source and drain regions diffuse under the pol-ysilicon gate by a distance LD, as shown in Figure 35. Theactual channel length, as defined earlier in Figure 31, isgiven by

(3.4)

So far, we have treated the gatesource voltage of then-channel MOSFET as a parameter in the other equa-tions. We can get a feel for how this parameter affects the

device current by sweeping it at a given VDS. Suppose wewish to plotIDas a function of VGSfor VGSranging from 0to 3 V for the n-channel MOSFET. The circuit configura-tion for this measurement is shown in Figure 36. We willassume that n = 215 cm

2V1s1, tox = 150 ,VTn = 0.5 V,L = 1 m, and W= 30m. Figure 37 shows the plot of the

ID 0 A=

V( GS VTn VDS VGS VTn, )

ID W L( )nCox VDS VGS VTn VDS 2( )[ ] 1 nVDS+( )=

V( GS VTn VDS VGS VTn, )

ID W 2L( ) nCox VGS VTn( )2

1 nVDS+( )=

VDSSAT

VDSSAT

L Lgate 2LD=


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equations with these parameters. The changing currentclearly displays the behavior that we would expect basedon the current equations. When VGSis less than VTn= 0.5V,there is no current. As it rises above VGS, the nMOS enterssaturation, because VDS(2 V) is larger than VGSVTn. Thecurrent increases quadratically with the turn on voltageVGSVTn, as the equation states. Finally, when VGSVTnexceeds VDS, the nMOS enters the triode region, and itscurrent increases linearly with VGS.

While Figure 37 shows that the n-channel MOSFETdefinitely cannot be called an ideal switch, it does demon-strate switch-like behavior. When the input VGS to the

switch stays below the threshold voltage, the transistorconducts no current. Once the input rises above VTn, thetransistor begins to conduct current. It clearly cannot pro-vide perfect conductivity (infinite current or 0 resistance)

like an ideal switch, but it does at least behave functionally

in the same fashion. After we look at device models for thepMOS transistor, we will use this switching behavior of thetransistors to construct a realizable inverter using MOS-FETs.

Figure 35: Definitions of the as-drawn gate length Lmaskon the mask, the as-etchedpolysilicon gate length Lgate, and the channel length L = Lgate 2LD.

VDS

(VDS

saturation

VGS VT


9/34


3-2-2 Device Models for pMOSFETs for Use inCircuit Design

In a CMOS technology, both n- and p-channel MOS-FETs are fabricated on the same substrate, which is usu-ally p-type. The pMOS transistors are placed in a well ofn-type (n-well) silicon. The layout of a pMOS looks essen-tially the same as an nMOS layout, except that thesource/drain diffusion sits in the n-well and is p-type. Thetap (n+) connects to the n-well, which is the body terminalof the pMOS transistor.

As described before, the pMOSFET behaves as some-thing of an upside-down version of the nMOSFET. Sinceits source is at a higher potential than its drain, all of thereference voltages are negative (e.g., VGSand VDSare neg-ative). Likewise, pMOS device thresholds are negative,including VTp. There is a straightforward way to alter thenMOS equations to use these negative values. First, switchthe order of all of the subscripts (e.g., GS becomes SG, DS

becomes SD, and SB becomes BS). Second, replace VTnwith VTp. Finally, replace IDwith ID. The current equa-tions for the pMOS then changes:

For (VSG VTp), the pMOS is in cutoff, so its current is

(3.5)

For , the pMOS is in triode:

(3.6)

For , the pMOS is in satura-

tion:

(3.7)

In these equations, VTp is negative, unlike for nMOS.All of the other parameters have the same sign as fornMOS. Thus, p, Cox, and p are positive. As with thenMOS, we will assume that VTpis a technology constant.We also will assume that VB for a pMOS is always tied toVDD, which prevents the p and n diodes between thesource/drain and bulk to be forward biased.

These equations easily can yield mistakes if you misuse

the negative signs. Notice that switching the subscriptssimply makes the reference voltages positive, and theparameter substitutions ensure that the final current valueis positive on the right side of the current equations. Thisis whyIDneeds to become negative on the left side to indi-cate that it flows out of the drain of the pMOS. This is

equivalent to simply treating allof the pMOS referencevoltages and parameters as though they were nMOS val-ues (e.g., by taking absolute value of the reference volt-ages) and using them in the nMOS, as in Eqs. (3.1)through (3.3). Remember to invert the final current valueto make it negative. You may find this trick of calculatingthe pMOS current as though it is an nMOS to be less con-fusing than using Eqs. (3.5) through (3.7).

Consider the nMOS and pMOS transistors arranged inparallel in Figure 38. The gate voltage of the nMOS istied to VDD, and the gate voltage of the pMOS is tied toground. Assume that the input to this configurationinstantly switches from 0 to VDD. As the output charges upfrom 0 to VDD,,in what regions of operation do the transis-tors function? Give the ranges of the output voltage, Vout,and the associated regions of operation. Assume that

(W/L)n = (W/L)p = 2 m/1 m. Assume the followingdata:

,

SOLUTION

We will use the following steps to identify the regions ofoperation. First, we will draw an equivalent circuit. Sec-ond, we will identify the terminals of the device. Third, wewill see if the device is in cutoff. Finally, for the regionswhere the device is not cutoff, we will test to see if thedevice is in triode or saturation.

ID 0 A=

VSG V Tp VSD VSG VTp+,( )

I D W L( ) pCox VSG VTp VSD 2( )+[ ] 1 pVSD+( )VSD=

VSG V Tp VSD VSG VTp+,( )

ID W 2L( ) pCox VSG VTp+( )2

1 pVSD+( )=

Example 3-1: MOSFET Operating Regions

Figure 38: Parallel n-channel and p-channel MOS transistors used as atransmission gate (i.e., a switch) that isturned on. If the input switches instantlyto VDD, in what regions of operation dothe transistors function as the outputchanges from 0 to VDD?

n Cox 2p Cox 50 A V2

= =

VTn VTp 0.5V= = Ln Lp 1m= =

VDD 3V=

Vin Vout

VDD


10/34


Let us begin the solution by looking at the nMOS tran-sistor. Figure 39(a) shows the equivalent circuit for thenMOS after the input has switched. Since the drain isdefined as the highest potential, the drain of the nMOS isat the Vinside of the transistor once it switches to 3 V. Thegate is at 3 V also, and the source is Vout. The next thing tocheck is if the transistor is on. For this, we compare VGSto

VTn. For the nMOS in Figure 39(a), VGS = 3 Vout. ThenMOS is in cutoff then if

Plugging in VTn = 0.5 V and solving for Voutgives

Thus, the nMOS is in cutoffif Voutis over 2.5 V.

This means that the nMOS is on for the range of Voutbetween 0 V and 2.5 V. To divide this range into the triode

and saturation regions, we need to compare VDSto VGSVTn. We know from (3.2) that the device is in triode if VDS< VGS VTn. For the nMOS in Figure 39(a),

and , so the deviceis never in triode. It is thus in saturationfor the range ofVoutfrom 0 V to 2.5 V.

Now, we need to perform the same analysis for thepMOS transistor in Figure 38, and we will use the samefour steps. First, we redraw the equivalent circuit for thepMOS after the input has changed, as shown in Figure39(b). Next, we identify the terminals of the transistor.Since the drain of a pMOS is defined as the lowestvoltage,

the pMOS drain is at Vout, and its source is at 3 V.This means that VSG for the pMOS is 3 V, which isgreater than VTp, so the pMOS will not be cutoff at allduring this transition. Now we need only to distinguishbetween triode and saturation operation. The pMOS is intriode when VSD< VSG (VTp). For the pMOS, VSD = 3Vout, and VSG (VTp) = 2.5 V. Thus, we can write the fol-

lowing equation and solve for Voutto see the range of theoutput for which the pMOS is in triode:

Thus, the pMOS is in triodewhen the output voltage isabove 0.5 V and is in saturationwhen it is less than 0.5 V.

3-2-3 Small-Signal MOSFET Model

In analog applications, a DC operating point specified bythe bias voltages VGS, VDS, and VBS, is established soVDS > = VGS VTn. Incremental voltages vgs, vds, andvbsthat are much smaller in magnitude than the bias volt-ages perturb the operating point. Asmall-signal modelis acircuit representation of the response of the drain current

of the MOSFET to these perturbations. Since this book isabout digital circuits, we will not spend much time with thesmall-signal model of a MOSFET. However, we will needto use it occasionally (such as to calculate gain of a digitalinverter), so we introduce the model in this section usingthe nMOS transistor as an example.

The total drain current iD =ID+ idis a function of thegate, drain, and bulk voltages in saturation. By summingthe contributions from the perturbations vgs, vbs, and vds,we can write a first-order expansion for the drain current

(3.8)

where Qis the DC operating point of the MOSFET, whichis defined by VGS, VSB, and VDS. The partial derivatives inEq. (3.8) represent small-signal circuit elements and aregiven the following symbols.

(3.9)

where

, , and (3.10)

The MOSFETtransconductancegmconnects the small-signal gatesource voltage vgsto the resulting incrementaldrain current. The backgate transconductancegmbrepre-sents the perturbation of the drain current by an incre-mental change in the bulksource voltage. Finally, the

Figure 39: Equivalent circuits for the (a)nMOS and (b) pMOS transistors inFigure 38.

Vout

Vin = VDD = 3 VD

S

(a)

Vout

Vin = VDD = 3 V

D

GG

S

(b)

3 Vou t VTn

Vou t 2.5

VDS 3 Vou t= VGS VTn 2.5 Vou t=

3 Vou t 2.5

Vou t 0.5

VDSSA T

ID id+ ID +iD

vGS

-----------

Q

vgsiD

vBS

-----------

Q

vbsiD

vDS

-----------

Q

vds+ +=

id gmvgs gmb vbs govds+ +=

gmiD

vGS

-----------

Q

= gmbiD

vBS

-----------

Q

= goiD

vDS

-----------

Q

=


11/34


output conductancegorelates the incremental change indrain current due to a small-signal, drainsource voltage.

We can calculate these transconductances by evaluat-ing the derivatives shown in Eq. (3.10). For the purposesof this book, we are interested only in the transconduc-tance and the output conductance. A useful approxima-

tion to the equation forgm can be made by neglecting thecontribution from the channel-length modulation, whichwill be a small error if :

(3.11)

These results indicate thatgmis equally sensitive to thebias drain current, the channel width-to-length ratio, andnCox.For a typical channel mobility 215 cm

2V1s1; oxidecapacitance 2.3 fFm2; bias drain current ID = 100 A;and (W/L) = 10, we find that the transconductance

gm = 316 S (S = A/V).The drain conductancegorepresents the dependence of

the drain current on the drainsource voltage

(3.12)

where we again make the approximation at theoperating point to obtain a simpler result. The channel-length modulation parameternhas been found to vary

inversely with the channel length

(3.13)

for a MOSFET with L = 1 m, and n = 0.06 V1. At a DC

bias currentID = 100 A, the inverse of the drain conduc-tance (called the output resistance) is

(3.14)

3-2-4 Small-Signal Circuit

We can assemble the small-signal model for steadystateperturbations on the operating point by properly connect-ing these three elements between the four terminals of theMOSFET. Kirchhoffs current law indicates that the threeelements are connected in parallel at the drain nodeshown in Figure 310, since their contributions sum to givethe small-signal drain current

(3.15)

Note that the small-signal, steadystate gate current ofthe MOSFET is zero. In addition, the reverse-biasedsourcebulk junction is an open circuit in steadystate, asshown in Figure 310.

nVDS 1

gmW

L-----

nCox VGS VTn( ) 2

W

L-----

nCoxID=

goiD

vDS-----------

Q

W

2L------

nCox VGS VTn( )

2n nID= =

nVDS 1

n 1

L---=

go( ) 1

ro 150 k= =

id gmvgs gmb vbs govds+ +=

Figure 310: Steadystate small-signal model for the n-channel MOSFETin saturation.

gmvgs gmbvbs ro

gate

source

drain

_

_

vgs

+

id

+

bulk

vbs


12/34


3-3 CMOS Inverter Characteristics

We demonstrated the concept for a logical inverter inChapter 2 using ideal switches, and we have seen howMOSFETs behave as approximations of those idealswitches. Now we are ready to use the nMOS and pMOStransistors to construct a CMOS inverter. Figure 311(a)and (b) recounts the inverter structure using idealswitches. Since voltage is the quantity that we use to mapto logic levels, the input to the inverter is the voltage Vin.If the input voltage is high, the lower switch closes to dis-charge the capacitive load. If the input is low, we turn onthe top switch to charge up the capacitive load. At no time(or for a very short time) are both switches on, which pre-vents DC current from flowing from the positive powersupply to ground. A simple implementation of this switch-ing concept is shown by shorting the gate terminals of thep- and n-channel devices shown in Figure 311(c).

Qualitatively, this circuit acts like the switching circuits,since the p-channel transistor has exactly the oppositecharacteristics of the n-channel transistor. Hence, whenthe input voltage is high (e.g., 3 V), the p-channel transis-tor is off (cutoff), and the n-channel transistor is on (tri-ode). When the input voltage is low, the p-channeltransistor is on (triode), and the n-channel transistor is off

(cutoff). In the transition region, both transistors are satu-rated, and the circuit operates with a large voltage gain.To understand how we develop the voltage transfer

characteristic for the CMOS inverter, consider the transis-tor characteristics shown in Figure 312 for the n- and p-channel transistors.

Starting at point(1), where the input voltage is equal to0 V, we see the output voltage is equal to VDD. As weincrease the input voltage to point (2), the n-channel tran-sistor operates in its constant-current region while the p-channel transistor is in the triode region. As we furtherincrease the voltage to point (3), both n- and p-channeltransistors are in their constant-current region, and we arein the high-gain region of the inverter. Further increasingthe input voltage to point (4)puts the n-channel transistorin the triode region and the p-channel transistor in its con-stant-current region. Finally, when the input voltage isgreater than VDD + VTp, at point (5), we find the p-channeltransistor is below its threshold voltage (cutoff) and the n-

channel transistor has 0 V corresponding to an outputvoltage equal to 0 V.

Qualitatively, the CMOS inverter has low power dissi-pation, since there is no DC current flowing in either logi-cal state. Also, the speed of the inverter can be set with aconstant current charging and discharging the load capac-itor. These excellent characteristics, along with its robust-ness to noise (which we discuss in Section 3-3-2) havemade CMOS the technology of choice for complex logicfunctions, as well as for semiconductor memory.

3-3-1 Voltage Transfer Characteristic

The voltage transfer characteristic of the CMOS inverterat the top of Figure 312 has some strong similarities to theideal VTC, which we replicate in Figure 313 for your ref-erence.

Figure 311: The CMOS inverter: (a) switch level representation Vin = High,Vout = Low; (b) switch level representation Vin = Low, Vout = High; and (c) circuitdiagram for CMOS inverter.

CL

input

high

output

low

input

low

output

high

VDD VDD VDD

Vout

Vin

(a) (b) (c)

+

CL

CL


13/34

Section 3-3 CMOS Inverter Characteristics 31

The CMOS-inverter VTC has the same basic shape asthe ideal VTC, but its transistions are less abrupt. We candefine a few key values on the real VTC that help us toquantify its non-idealities. Figure 314 shows a closer lookat a typical CMOS-inverter VTC that has these key pointslabeled.

To start with, the ideal VTC will map any input voltagebelow the switching threshold VMto a logical 1. The sameis not true for the CMOS inverter, because the output volt-age drops below VDDbefore the switching threshold. This

occurs because the gain of the non-ideal inverter is notinfinite (that is, the slope of the vertical part of the VTC isnot straight up and down). We thus must be more carefulabout specifying valid input and output voltages. Wedefine specific input and output voltages as follows.

Figure 312: CMOS voltage transfer characteristic shown with (a) nMOStransistor characteristics and (b) pMOS transistor characteristics. Points 1through 5 correspond to increasingVinfrom 0 V to VDD. Note: Dashed

characteristics on n- and p-channel curves are for equalV

in.

Vin

Vout

1

3

45

IDn= IDp IDp=IDn

(a)

VDD Vout VDD Vout

Vin

(b)

n-channel p-channel

12

3

4

51

24

3

5

VDD

VDD

2

Figure 313: (a) The inverter with an inputvoltage, Vin,output voltage, Vout,and powersupply voltage VDD. (b) Ideal transfercharacteristic for the inverter.

VoutVoutVin

Vin

D

S

S

D

(a)

Vm = VDD/2

G

G

(b)

VDD

VDD

VDD

0

0


14/34


VIL (voltage input low)lower input voltage wherethe slope of the transfer characteristic is equal to 1

VIH(voltage input high)higher input voltage wherethe slope is equal to 1

VOH(voltage output high)output voltage given aninput voltage of VIL

VOL (voltage output low)output voltage given aninput voltage of VIH

VM (voltage midpoint)input voltage at which theinverter yields an output voltage equal to the input

voltageWhen the input voltage is equal to 0 V, Vout =Vmax(max-

imum output voltage), which in most cases of interest isVDD. For a small input voltage between 0 V and VIL, theoutput voltage will be between Vmax and VOH. VOH is theminimum output voltage for a valid logic 1. As we furtherincrease the input voltage, the output voltage rapidly fallsthrough the transition region. When the input voltage isbetween VILand VIH, the output voltage is in the transitionregion where the logic level is undefined. Notice that thedefinition of VILand VIHbased on the slope of the VTC(slope = 1) provides a quantitative method of defining

the transitional region. If the gain never becomes morenegative than , the inverter will not properly rejectnoise. As the input voltage is increased to a value betweenVIHand VDD, the output voltage is a low value between VOLand Vmin(minimum output voltage). VOLis the maximumoutput voltage for a valid logic 0. When Vin is equal toVDD, we define Vout= Vmin. In general, Vminmay not be 0 V,

however for static CMOS circuits like this inverter,Vmin = 0 V.

From this transfer characteristic, one can see that ifVin < VIL, the output voltage is a valid logic 1. Correspond-ingly, if Vin > VIH, the output voltage is a valid logic 0. Ifthe input voltage is between VILand VIH, the logic outputis undefined. This range of input voltages is referred to asthe transition region.

3-3-2 Logic Levels and Noise Margin

As mentioned in the previous section, the inverter charac-teristic has three distinct regions: the low region whereVin < VIL, the high region where Vin > VIH, and the transi-tion region where VIL < Vin < VIH. In Figure 315, we haveone inverter driving a second inverter. The input and out-put voltage levels corresponding to each of these invertersare indicated. If we look at the region where the firstinverters output is connected to the second invertersinput, we see that VOH1 > VIH2and VOL1 < VIL2.

We can define a noise margin high, NMHwhich ensuresthat a logic 1output from the first inverter is interpretedas a logic 1input to the second inverter. Similarly, we candefine a noise margin low, NMLwhich ensures that a logic

0output from the first inverter is interpreted as a logic0input to the second inverter. The expressions for bothnoise margins are given by

(3.16)

(3.17)

Figure 314: Typical inverter transfer characteristic. For Vin = 0 V, Vout = Vmax; for Vin = VIL,Vout = VOH; for Vin = VM, Vout = VM; for Vin = VIH, Vout = VOL; for Vin = VDD, Vout = Vmin.

= 1

Vout

Vmax

Vmin

VOH

VM

VIL VM VDDVIHVin

VOL

00

1

NMH VOH VIH=

NML VIL VOL=


15/34

Section 3-3 CMOS Inverter Characteristics 33

In summary, we have defined several parameters thatindicate the voltage transfer characteristics of the inverter.The conventional notation used to represent voltages indigital circuits is uppercase variable names and uppercasesubscripts.

VOH the minimum output voltage from an inverterwhich indicates a logic 1

VOL the maximum output voltage from an inverterwhich indicates a logic 0

VIH the minimum input voltage to an inverter tooutput a logic 0

VIL the maximum input voltage to an inverter tooutput a logic 1

VM the voltage at which the input and output volt-ages are equal

With these values, we have defined noise margins toensure the proper logical output. The CMOS inverter thatwe have used as an example has excellent noise marginsdue to its high gain in the transition region. The strongrobustness of static CMOS logic-to-noise contributes tothe popularity of this logic implementation choice for dig-ital circuits.

3-3-3 Transient Characteristics

In this section, we will determine the time required for anoutput to change state given that the input changes state.This time is called a propagation delay. Figure 316 showsa waveform describing a change in input voltage as a func-tion of time and also shows how the output voltage of aninverter changes as a function of time. The rise timetRisdefined as the time required for the input or output volt-age to change from 10 percent of its high value to 90 per-cent of its high value. Thefall timetFis defined as the timerequired for the input or output voltage to change from 90percent of its high value to 10 percent of its high value.

Referring to the output waveform, we define the prop-agation delay from high-to-lowtPHLas the delay betweenthe 50 percent points of the input and output waveforms.Similarly, we define the propagation delay from low-to-hight

PLH

as the time between the 50 percent points of theinput and output waveforms during this transition of theoutput. The total propagation delay tP, is the average ofthe low-to-high and high-to-low delays given as

(3.18)

Figure 315: Chain of two inverters to demonstrate the concept of noisemargin. A noise source that represents a variety of noise sources such ascapacitive coupling is placed between the inverters.

1

vnoise

2

VIH1

Voltage VIL1

VOH1

VOL1

VIH2

VIL2

VOH2

VOL2

NMH

NML

NMH= VOH VIHNML= VIL VOL

tPtPHL tPL H+

2---------------------------=


16/34


3-4 CMOS Inverter Analysis

In the previous section, we presented a qualitative view ofthe CMOS inverter and its definitions describing its oper-

ation. In this section, we will perform a static analysis toanalyze the inverter transfer characteristic, quantify logiclevels, and determine noise margins. In addition, we willperform a transient analysis to calculate the propagationdelay for a typical CMOS inverter. Finally, we will calcu-late the power dissipation of the CMOS inverter.

3-4-1 Simplified Transfer Characteristic forHand Calculations

Although it is possible to calculate the transfer functionand specific voltages VIL, VIH, VOL, VOH, and VMfrom the

large-signal models for MOS transistors, it is algebraicallycomplex. If we make some simplifications to the typicalvoltage transfer characteristic for the inverter, we find thatthe calculations become algebraically simple and reason-ably accurate for hand analysis.

The inverter transfer function for hand calculations isshown in Figure 317. For this voltage transfer character-

istic, we have redefined VOHas Vmaxand VOLas Vmin. Theerror introduced is small and negligible for hand analysis.

Figure 316: Input and output voltage as a function of time for an inverter.Definitions of tR, tF, tPHLand tPLHare depicted graphically.

VOL

90%

50%

10%

tPHL tPLHVOH

tR

tcycle

50%

90%

10%

0 t

Vin

Vout

0 t

tR tF

VOH

VOL

tF

Figure 317: Idealized inverter transfer

characteristic superimposed on a typical invertertransfer characteristic. Note: The idealizeddefinitions forVOHandVOLare used in this diagram.

VIL VM VIHVin

VOL= Vmin

VOH= Vmax

Vout

slopeAv

VM


17/34

Section 3-4 CMOS Inverter Analysis 35

The critical points in this transfer function are found byfirst determining VOHand VOLfor the circuit. For CMOSVOH=Vmax = VDDand VOL=Vmin = 0 V. VMis defined as theinput voltage at which the input and output voltages areequal. Under this condition, both the pMOS and nMOStransistors usually are operating in their constant-currentor saturation regions. We can use the current equations ina model of the circuit to find the voltage gain Av atVin = VM. After findingAvwe can draw a straight line atVMwith the slopeAv. The points at which this line intersectsoutput voltages VOHand VOLprovide a new definition forthe input voltages VILand VIHrespectively, which is suit-able for hand calculation.

It should be noted that for digital gates to be useful, thevoltage gain at the midpoint must be greater than one inmagnitude. In practice, the magnitude of the voltage gainis on the order of ten. Because of the relatively large volt-age gain, the error in using these definitions for hand cal-culations is well within those required for an initial design.

3-4-2 Static Analysis of the CMOS Inverter

The goal of this analysis is to determine the logic levelsand noise margins for a CMOS inverter. From the previ-ous qualitative description, we know that VOH= VDDandVOL= 0 V.

Determine Switching Threshold, VM

The next step is to find the input voltage VM when theinput and output voltages are equal. Under this condition,

we will assume that both the n- and p-channel devices areoperating in their constant-current region (it is importantto plug in the numbers so that you can check this assump-tion later). The current for the nMOS is given by

(3.19)

and the current for the p-channel device is given by

(3.20)

If we let

(3.21)

and

(3.22)

and setIDnequal toIDp(i.e., equate the magnitude of thecurrents), we can solve for V

M. We assume that the chan-

nel-length modulation terms can be ignored. In fact, forsymmetrical transistors (n = pand VM = VDD/2) the termsprecisely cancel. The resulting equation for VMis

(3.23)

Looking at Eq. (3.23), we see that if kn kpthen VMisapproximately VTn. Physically, a large knimplies that the n-

channel transistor can sink much more current than the p-channel transistor can provide, and hence, the trip pointwill be reduced. If kp kn, then the opposite effect occursand the trip point VMmoves toward the positive powersupply, and in the limit becomes equal to VDD + VTp. WhileVM will not reach these extremes for reasonably sizeddevices, it is very useful to remember that a stronger (e.g.,larger W/L) nMOS device moves VM towards 0, and astronger pMOS device moves VMtowards VDD.

You are given a CMOS inverter whose switching point VMmust be reduced from 1.5 V to 1.0 V. Due to layout con-straints, the only adjustable parameter is the width of then-channel transistor Wn. When VM = 1.5 V, Wn = 2 m.Find the new n-channel transistor width given the follow-ing data:

,

SOLUTION

First find the width of the p-channel transistor. We wouldlike to use Eq. (3.23), but it is only valid if both transistorsare saturated, so we must check to see if this is the case. AtVM = 1.5 V, VGSn = 1.5 V, so VGSn VTn = 1.0 V whichmeans that the nMOS is on. Furthermore, since VDSn =

InDW

2L------

n

n Cox VM VTn( )2 1 nVM+( )=

I DpW

2L------

p

pCox VDD VM VTp+( )2 1 p VDD VM( )+( )=

knW

L-----

n

nCox=

Example 3-2: CMOS Inverter Static Analysis

kpW

L-----

p

pCox=

VM

VTnkpkn---- VDD VTp+( )+

1 kp

kn----+

------------------------------------------------------=

n Cox 2p Cox 50 A V2

= =

VTn VTp 0.5V= = Ln Lp 1m= =

VDD 3V=


18/34


1.5 V, VGSn VTn< VDSn, so the nMOS is in saturation. Forthe pMOS, VSG = 1.5 V, VSD= 1.5 V, and VTp = 0.5 V, sothe pMOS also is saturated. Now we can safely useEq. (3.23) with VM = 1.5 V to find that kp = kn, so

so Wp = 4 m.To find the n-channel width required to lower VM

to 1 V, rearrange Eq. (3.23) and use VM = 1.0 V.

so

Therefore, the new n-channel transistor width requiredis 18 m. Notice that the required width to move theswitching threshold so low is quite large.

Determine Noise Margins

The first step to finding the noise margins is to calculateVILand VIH. We determine the slope of the transfer char-

acteristic at Vin = VM, (i.e., voltage gain) and use it toproject a line to intersect at Vout = Vmin = 0 V to find Vin.Similarly, we project a line to intersect at Vout = Vmax = VDDto find VIL. To find the voltage gain when the input voltageis equal to VM, we use the small-signal model of both MOStransistors. At that operating point, we find the transcon-

ductance and the output resistance of the n- and p-channeldevices are given by

(3.24)

(3.25)

(3.26)

(3.27)

The small-signal model for the CMOS inverter is shownin Figure 318. Backgate transconductance generators areopen circuits, since we assume that vbs = 0 V .The relation-ship between the output voltage and the input voltage isgiven by

(3.28)

In CMOS inverters, one generally uses the shortestchannel-length transistor that the technology will providein order to have the largest current possible for a givendevice size. For MOSFETs, the output resistance will besmall if the channel length is small, and hence, the voltagegain of typical CMOS inverters is on the order of 10.

To find VILand VIH, we use the known slopeAvand find

(3.29)

(3.30)

These equations are extremely simple because we madethe straight-line approximation that the voltage gain wasconstant between VIL and VIH as shown in Figure 319.

W

L-----

p

W

L-----

n

n Cox

p

Cox

-------------- 41.0-------= =

VM 1 kp

kn----+

VTnkpkn---- VDD VTp+( )+=

kp

kn----

VM VTn

VDD VTp VM+-----------------------------------

1 0.5

3 0.5 1-------------------------

0.5

1.5-------= = =

kn 9kp=

W

L-----

n

9 W

L-----

p

p Coxn Cox-------------- 9

4

1.0-------

1

2--- 18

1.0-------= = =

gmn kn VM VTn( )=

ron 1/ nIDn( )=

gmp kp VDD VM VTp+( )=

rop 1/ pIDp( )=

Avvou t

vin--------

gmn gmp+( ) ron ||rop( )= =

VIL VMVDD VM( )

Av---------------------------+=

VIH VMVMAv-------=

Figure 318: Small-signal model of CMOS inverter evaluated at Vin = VM.

vin gmnv gmpvv

+

vout

+

+

ron rop


19/34


Their accuracy certainly is adequate for hand analysis.The last quantities to calculate for the CMOS inverter

static analysis are the noise margins. They are given by

(3.31)

(3.32)

In this example, we are going to design a basic CMOSinverter. The inverters transition voltage must be

VM = 1.5 V, the current through the n- and p-channeldevices should be 100 A at Vin = VM, andV. The power supply voltage VDD is

3 V. Specify to the process engineer the maximum channellength modulation that can be tolerated to meet all ofthe above design specifications. Assume n = p.

MOS Device Data:

and

SOLUTION

To begin this design, we need to find the (W/L) ratios ofthe devices needed to carry 100 A at Vin = VM. SettingVM = 1.5 V and assuming that is small for this calculation,

We will have to make (W/L)p twice as big as (W/L)n,because , so

To have the required noise margins of 1.35 V, the min-imum voltage gain needed can be found by usingEqs. (3.31) and (3.32).

and .

So

Since (W/L)p = 2(W/L)n and nCox = 2pCox, kn = kp.Using Eq. (3.31) and noting n = p,gmn =gmpand ron = ropfor VM = 1.5 V. We write

Now

.

Substituting for ronand solving for n, we arrive at

We obtain a value forgmnby

Substituting gmn = 0.28 mS, Av = 10, and ID = 100 A

into the expression for n, we have

3-4-3 Propagation Delay

It is extremely difficult to calculate transient voltage wave-forms accurately using only hand analysis. Therefore, as

Figure 319: CMOS transfer characteristicillustrating the calculation of VIL, using thehand-analysis approximation.

Design Example 3-3: CMOS Static Inverter

VinVIHVMVIL

VOL= 0 V

Vout

Av

Av

VDD VM

VOH= VDD

VDD VM

VM

NML VIL VOL VM VDD V M( ) A v+= =

NMH VOH VIH VDD VM VM Av+= =

NML NMH 1.35=

nCox 2 pCox 50 A V2

==

VTn VTp 0.5V== Ln Lp 1m==

IDn1

2---

W

L-----

n

n Cox VM VTn( )2

=

W

L-----

n

4.0

1.0-------=

n 2 p=

WL----- p8.01.0-------=

NML VMVDD2Av---------+= NMH VDD VM

VDD2Av---------+=

Av

VDD

2 NML VM( )----------------------------------- 10= =

A v gmn gmp+( ) ron rop||( ) 2gmn( ) ron

2------

= =

ron1

nID-----------=

ngmn

AvID------------

gmn 2 W

L-----

n

n Cox IDn 0.28mS= =

n 0.28 V 1


20/34


21/34


At t= 0, the input voltage is equal to zero and the out-put voltage is equal to VOH. Att= 0

+, we assume the inputvoltage has made an instantaneous transition to VOH. Theoutput voltage then decreases along the trajectory shown.As discussed in Section 3-3-3, tPHLis defined as the time ittakes the output voltage to discharge fromVOHto VOH/2.To discharge the capacitor, CL, from VOH to VOH/2, weneed to remove an amount of charge . Currentis the flow of the charge over time, so we can write anequation for tPHLas

(3.33)

We have assumed that the nMOS transistor remains in theconstant-current region throughout this transition, so thecapacitor voltage is linearly discharged by its saturationcurrent, as shown in Figure 322(b). Although this may

not be strictly true for our definition of , it is quiteadequate for this simplified hand analysis. We also haveignored the effects of channel-length modulation, whichwould cause the delay to decrease slightly due to the largercurrent.

The load capacitance CLconsists of two major compo-nents.

1. The total gate capacitanceCGthat is the gate capaci-tance of the transistors being driven by the inverter.

2. Aparasitic capacitanceCPthat results from the draindiffusions of the driving inverter and the wiring to thegates being driven.

In the following paragraphs, we will explore themethod to calculate these two components of CL. Refer-ring to Figure 321, we see that the inverter being ana-lyzed is driving two additional inverters. Its fan-out istherefore two. These two inverters are switching from thetriode region through saturation to cutoff during either ahigh-to-low or low-to-high transition. To accurately calcu-late the total charge supplied to the load inverters, wemust perform an analysis with non-linear charge storageelements. However, for a simple hand calculation, we canestimate a worst-case capacitance. The total gate capaci-tance of the load inverters is given by

(3.34)

where the input-gate capacitance of a single inverter isapproximated by

(3.35)

The total gate capacitance CGfor the two inverters in Fig-ure 321(b) can be estimated as

(3.36)

Refer to the layout and cross-section of an NMOS transis-tor in Figure 323(a) to calculate the parasitic capacitance,which is the second component of CL, due to the drain dif-fusions of Inverter 1. The n+drain diffusion has a deple-

Q CLV=

tPH LCLV

ID--------------

CLVOH /2

kn

2---- VOH VTn( )

2

---------------------------------------= =

VDSSAT

CG Cin

load( )inverters

=

Cin Cox W L( )p Cox W L( )n+

CG Cox WL( )p2 WL( )n2 WL( )p3 WL( )n3+ + +[ ]=

Figure 322: (a) NMOS transistor characteristic showing the trajectory of thecurrent-voltage relationship from t= 0 s to t= tPHL. (b) Transient waveform for Vout.

ID

2

t= tPHLt= 0+

t= 0

Vin= 0V

Vin= VOH

tPHL t

2

(a) (b)

VoutVOHVOH

Vout

VOH

VOH

00

00


22/34


Figure 323: Origin of parasitic drain-bulk depletion capacitance. (a) nMOScross section; (b) nMOS top view; (c) definition for dimensions Ldiffand Wused to calculate depletion capacitance.

deposited

oxide

field

oxide

n+ drain diffusion

drain

interconnect

p+

[ p-type ]

bulk

interconnect

Ldiff

gate contact

(b)

A

drain

contacts

bulk

contact

n+polysilicon gate

active area (thin

oxide area)

polysilicon gate

contact

metal

interconnect

n+source diffusion

edge of

active area

source

interconnect

(a)

L

n+polysilicon gate

gate oxide

gate

interconnect

source contacts

drain

interconnect

source

interconnect

W

Ldiff

(c)

W

L

L


23/34


tion-region capacitance that is determined primarily bythe doping concentration in the p-type region under thatdiffusion. The doping concentration due to the fieldimplant can be higher along the sides of the n+drain diffu-sion, than at the bottom of the diffusion. Because of this,we separately account for the perimeter capacitance alongthe edge of the drain diffusion. Although this capacitanceis voltage dependent, for hand analysis we usually use azero-bias capacitance value for our worst-case estimate.

Most MOS process technologies specify a value to thecircuit designer for the bottom junction capacitance perunit area, CJn, and a sidewall junction capacitance per unitlength,CJSWn. Figure 323(b) shows a top view of the n-channel MOS transistor. Because there are design rulesthat limit the minimum size of the contact, the spacingbetween the contact and polysilicon gate, and the contactand outer region of the active region, there is a minimumlength of the drain diffusionthat we callLdiff. This impor-tant dimension (along with the device width) is sketched

in Figure 323(c).The area of the drain diffusion then is W Ldiff. Thesidewall perimeter of the device is equal to W+ 2Ldiff. Itshould be noted that the diffusion capacitance along theedge of the gate is not included in this calculation. Thiscapacitance already is taken into account in the intrinsicMOS transistor model. A similar analysis applies to thepMOS transistors. This discussion shows that the totaldrain-bulk depletion capacitance CDB for an inverter isgiven by

+ (3.37)

Finally, we should add a component to the parasiticcapacitance that is due to the wiring between the drain ofthe inverter and input of the next gate. Figure 324 showsa cross section of a metal line connecting a polysilicon gateand running across both thermal and deposited oxide. Thecapacitance of this structure is given approximately by thepermittivity of the oxide divided by the total dielectricthickness. To calculate the contribution of the wiring tothe parasitic capacitance, multiply this capacitance per-unit-area times the width and length of the metal intercon-nect line.

Between tightly coupled logic gates, the metal wiringcapacitance often is negligible compared to the drainbulkdepletion capacitance. However, it is important to realizethat in large digital systems we often have metal bussesthat extend a significant distance across a chip. Under thiscondition, the wiring capacitance is the dominant capaci-tance that determines the speed of the transition. In fact,in modern integrated circuits, the ultimate speed of micro-

processors often is determined by the delay caused by longwires. Wire capacitance (specifically due to capacitancebetween wires in the same routing layer) contributes evenmore significantly in more deeply scaled technologies dueto the fact that the distance between wires is shrinkingwhile their heights remain roughly constant.

The total parasitic capacitance in our example is givenby

(3.38)

We add the values of CGand CPto obtain the total loadcapacitance CL. Substituting CG + CP for CL,we find the

value of tPHLto be

CDB

WnLdiffn CJn( ) WpLdiffp CJp( )

+=

Wn

2Ldiffn

+( )CJSWn

Wp

2Ldiffp

+( )CJSWp

+

CP CDB Cwire+=

Figure 324: Cross section showing origin of parasitic wiring capacitance.

pp

+

0.6 m deposited oxide

0.5 m thermal oxide

metal interconnect

(width Wm, length Lm)polysilicon

gate

gate oxide

(grounded)


24/34


(3.39)

Similarly, we can find a value for tPLHto be

(3.40)

It often is useful to design digital gates to make thepropagation delay symmetrical; namely to maketPHL = tPLH. This removes the data dependency of the delayand minimizes the time that both transistors are on simul-taneously. Because the mobility of holes in the p-channeltransistor is approximately one-half that of electrons inthe n-channel transistor, Eqs. (3.39) and (3.40) indicatethat setting (W/L)p = 2(W/L)nequalizes the rise and falldelays, assuming VTn = VTp.

The average propagation delaytPcan be estimated by

averaging the transition times as shown in

(3.41)

In large, complex digital systems, many individual gate-propagation delays are incurred by placing digital gates inseries. In our example, the driving inverter had a fan-outof two. The average fan-out is higher than two, and aninverter with a fan-out of four commonly is used to pro-vide a reference propagation delay called the FO4 delay.Typical systems have between twenty and fifty FO4 prop-agation delays for every major clock cycle, although thefastest modern processors may shrink this towards ten forsome blocks. This implies that a microprocessor with aclock speed of 3 GHz must have single gate delays lessthan 30 picoseconds. These small delays are possible onlyin newer process technologies than the example technol-ogy that we present in this text.

A CMOS inverter driving two other identically sizedinverters is shown in Figure 325. Calculate tPHLandtPLH.Ignore wiring capacitance but include the parasitic drain-

bulk depletion capacitance.MOS Device Data

nCox = 50 A/V2

pCox = 25A/V2

VTn = VTp = 0.5V

Cox = 2.3 fF/m2

CJn = 0.1 fF/m2

CJp = 0.3 fF/m2

CJSWn = 0.5 fF/m

CJSWp = 0.35 fF/m

Ldiffn = Ldiffp = 6 m

SOLUTION

Begin the solution by finding CL. Since Inverters 2 and 3are identically sized, CG is two times that of Inverter 2.From Eq. (3.34), we find

Since the wiring capacitance is neglected, CP = CDB.

Example 3-4: CMOS Inverter Propagation

Delay Analysis

tPH LCG CP+( )VOH /2

kn /2 VDD VTn( )2

-----------------------------------------=

tPL HCG CP+( )VOH / 2

kp/ 2 VDD VTp+( )2--------------------------------------------=

tP tPH L tPL H+( )/ 2=Figure 325: Exampleinverter with fan-out of two forcomputing propagation delayin Example 3-4.

Vin

VDD= 5 V

VDD= 5 V

1

2

3

121.5

121.5

61.5

61.5

VDD= 5 V

121.5

61.5

CG 2Cox WL( )p2 WL( )n2+[ ]=

CG 2= 2.3 fF

m2

---------- 12 m 1.0 m( ) 6 m 1.0 m( )+[ ]

82.8fF=

CP CDB Wn1LdiffnCJn Wp1LdiffpCJp+= =

Wn1 2Ldiffn+( )CJSWn Wp1 2Ldiffp+( )+ CJSWp

CDB 6m 6 m 0.1 fF

m2

---------- 12m 6m 0.3 fF

m2

----------+=


25/34


CDB = 3.6 fF + 21.6 fF + 9 fF + 8.4fF = 42.6 fF

So

CL = CG + CDB = 82.8 fF + 42.6 fF = 125 fF.

From Eq. (3.39),

and

so tPHL = 200 ps.

From Eq. (3.40),

and

sotPLH = 200 ps.

Design a 3-V CMOS inverter that is an input to an inte-

grated circuit. The midpoint logic level of the signal driv-ing the CMOS inverter is 0.9 V. The CMOS inverter mustbe able to drive a 6-m wire that may traverse the entire1-cm chip as well as two other inverters sized at(W/L)p = 2(W/L)n = 10/1.0. The specifications needed forthe inverter require tPto be less than 5 ns and both noisemargins to be at least 0.8V. n = p =0 .1V

1, and thecapacitance value of the wire is 0.035 fF/m2. Specify thechannel widths needed to build such an inverter. Use thesame device data as in Example 3-4. Verify your designwith a SPICE simulation.

SOLUTION

Start by finding the ratios of the n- and p-channel devices.After checking to ensure that both devices are in satura-tion, rearrange Eq. (3.23) to find

,

.

Since kn kp,tPHLwill be negligible. This leaves tPLHtobe determined by the tP specification. To find tPLH, firstdetermine the values of CG and CP. From Example 3-4,CG = 83 fF. Since the size of the p-channel device is not yetknown, we cannot accurately determine CP. However, wedo know it will be dominated by the long wire.

From Eq. (3.40) we determine

This implies that (W/L)p = 8.0/1.0. To make kn = 16kp, weneed (W/L)n = 16/2(W/L)p, so (W/L)n = 64/1.0.

Finally, check to see if our inverter will meet the mini-

mum noise-margin requirements. Since VMis closer to 0,the low noise margin is the only one likely to fail to meetthe constraint. Since we know that the noise margin mustbe 0.8 V, we can solve Eq. (3.31) to find the gain that isrequired to ensure adequate NML, which shows that thegain must be . Now we can find the voltage gainAvof our inverter, at Vin= VM, to compare with this constraint.

where

yielding

gmn = 1.28 mS and

Thus,

, soAv= 31.2.

Since the gain is less than -21, the noise margins are suf-ficient, and our hand analysis has given us a good approx-imation.

In digital-integrated circuit design, it is very importantto use computer simulation tools to verify both static andtransient analyses. Tools that accurately extract the gateand parasitic capacitance should be used. These capaci-

Design Example 3-5: CMOS Input

Inverter/Buffer

6m 2 6 m+( ) 0.5fFm--------+

12m 2 6 m+( ) 0.35fFm--------+

tPH LCG CP+( ) VDD 2( )

kn

2---- VDD VTn( )

2

-----------------------------------------------= kn6

1.0-------

50A V

2,=

tPL HCG CP+( ) VDD 2( )

kp2---- VDD VTp+( )

2

-----------------------------------------------= kp12

1.0-------

25 A V

2=

kp

kn----

VM VTn

VDD VTp VM+------------------------------------ 0.9 0.5

3 0.5 0.9------------------------------=

0.4

1.6-------= =

kn 16kp=

CP Cwire 6m 10 000m, 0.035fF m2

1

1000------------ pF

fF------=

2.1pF=

kp200A

V2

-----------------

Av 21

Av gmn gmp+( ) ron rop||( )=

gmn 2knIDn=

IDn Vin VM=( ) kn

2---- VM VTn( )

2256A=

gmpgmn

16---------- 0.32mS= =

ron rop1

IDn

----------- 39k= = =


26/34


tance values can be transferred into a circuit simulationprogram (such as SPICE) to find more accurate delaytimes for the particular digital gate being studied.

3-4-4 Power Dissipation

The increased use of portable electronics (such as cellular

phones and notebook computers) has made power dissi-pation an important design metric in modern microelec-tronics. Portable devices that operate using a battery havea limited energy supply and thus have lifetimes that areconstrained by their power consumption. Even ICs in sys-tems that are plugged into a continuous power supply arebecoming power constrained due to the difficulty of dissi-pating the heat that results from consuming power on achip with many tightly packed transistors.

There are two primary components that make up thepower dissipation in static CMOS digital gates. The first isdynamic power, which is needed to charge and dischargethe load capacitance.

Dynamic Power

Figure 326 shows an inverter driving a capacitive load,which we will use to calculate the dynamic power con-sumption. We begin by noting that energy is drawn fromthe positive power supply VDD only when the invertercharges the load capacitor up to a logical 1. Thus, on thehigh-to-low output transition, no energy is drawn from thepower supply. For the low-to-high output transition, wecan calculate the energy drawn from the supply as the inte-gral of power over time. Thus, we can write that the energy

drawn from the power supply to charge up CLis equal to

(3.42)

where Tis the clock period. Now, we know that the cur-

rent coming from the power supply to charge the capacitormust be equal to the current in the pMOS transistor, andthis current is nonlinear according to the MOS equations.However, the current from the power supply is also equalto the current flowing onto the capacitor. The charge on acapacitor equals the capacitance times the voltage acrossthe cap (Q= CV, so long as Cis not a function of voltage,which we will assume), and current is just the flow ofcharge:

Using these facts, we can rewrite the current as

(3.43)

Now, plugging Eq. (3.43) into Eq. (3.42) gives:

(3.44)

The total energy pulled from the supply to charge up thecapacitor is thus independent of the dimensions of theMOSFET devices and the length of the transition. Instead,it depends solely on the size of the capacitor and on thevoltage swing.

We can use a similar approach to calculate the energystored in the capacitor after the transition completes andthe capacitor is fully charged to VDD. Again, energy equalsthe integral of power:

(3.45)

Making a similar substitution as before yields

(3.46)

The energy stored in the capacitor is thus half of the total

energy drawn from the power supply during the transition.Therefore, the energy dissipatedby the p-channel transis-tor in charging the capacitor to VDDis equal to the totalenergy drawn from the supply less the amount remainingon the cap after it is charged. This subtraction yieldsEdiss=(1/2) CLVDD

2. Notice that the remaining energy onthe capacitor will be dissipated during the high-to-low

Figure 326: Inverter driving a capacitive load, CL.

EVDD

P t( ) td0

T

VDD iVDD t( ) td0

T

= =

Vout

CL

Vin

O

VDD

i t( )td

dq t( )=

iVDD

t( ) ica p t( )td

dqca p CL td

dVout= = =

EVDD

CLVDD td

dVouttd

0

VDD

CLVDD Voutd0

VDD

= =

EVDD

CLVDD2

=

Eca p P t( ) td0

T

VoutiVDD t( ) td0

T

= =

Eca p CL Vout Voutd0

DD

1

2---CLVDD

2= =


27/34


transition of the output.We can use this analysis of the energy consumed during

an inverters operation to determine the average powerconsumption of that inverter. Consider that the inverter inFigure 326 switches on and off f times/second. Thismeans that it will charge the load capacitanceftimes/sec-ond, and it will draw CLVDD

2Joules of energy from thepower supply each time. Since average power is just aver-age energy divided by time, let us use 1/fas the time periodof interest. This corresponds to the equivalent clockperiod of the circuit containing the inverter. If we dividethe total energy per transition by the clock period, thenthe average dynamic power PDdissipated by the CMOSgate is equal to

(3.47)

This equation tells us the average power consumed bythe inverter, assuming that it switches high then low once

every cycle (e.g., every 1/fseconds). If the inverter has aninput that is clocked at the frequency fbut that does notswitch every cycle, then we must scale this power numberby the rate at which the input transitions. Specifically, wecan quantify this switching rate as the activity factor of theoutput switching from low-to-high, as . The averagepower consumption thus becomes

(3.48)

For a well designed CMOS circuit, the majority of thepower consumption is attributed to dynamic power. Equa-tion (3.48) shows the power consumed by an inverter driv-

ing a capacitive load. This same equation often is used to

describe the power consumption of a larger digital CMOScircuit. In that case, f is the clock frequency, and VDDremains the supply voltage. The other terms, however,become approximations of the actual values for the activ-ity factor and the switched capacitance of the circuit. Forexample, the activity factor will change as different inputsare applied to a complicated circuit. Selecting an torepresent the average switching activity and calculatingthe capacitance as the average effective switched capaci-tance allows us to use Eq. (3.48) to find a good estimate ofthe total average power consumption.

Short Circuit Power

The second type of power dissipated in a CMOS circuithappens during the time when the output of the circuit isundergoing its transition. During this time, both thenMOS and pMOS transistors are on, and current can flowfrom the power supply to ground. This type of power iscalled short-circuit power. Figure 327 shows an inverterdriving a capacitive load. Depending on the direction ofthe output transition, a current will flow to charge or todischarge the capacitor. Regardless of the direction of theoutput transition, short circuit current will flow tempo-rarily from power to ground while both transistors are on.

From a DC point of view, we can see that the short cir-cuit current will flow in an inverter as long as its input volt-age is between VTnand VDD|VTp|, since both transistorswill be in either the linear or saturation mode for thisrange of the input. The short circuit power can be defined

as

PD fCLVDD2

=

0 1

PD 0 1 fCLVDD2

=

0 1

Figure 327: Inverter driving a capacitive load, CL, with short circuitcurrent illustrated during (a) a rising and (b) falling transition.

Vin

(a)

Vout

ISCCL

VDD

Vin

(b)

Vout

ISC

IdischargeIcharge

CL

VRD


28/34


29/34


30/34


Thus, for a rising input, the input voltage will reach VDDwhile the output remains at VDD. This biases the nMOSstrongly in the saturation region, and it will begin to dis-charge the large capacitance. However, by this time, thepMOS already is cut off, since the input is at VDD. Thus,due to the slow reaction of the output voltage, there willbe zero short circuit current in this case. Therefore, thecases when CLequals zero or infinity set the bounds on theshort circuit current. Generally, a larger CLwill lead to lessshort circuit power (but more dynamic power). Figure329 confirms this result for a few specific cases of CL. Agood design rule related to this observation is to ensurethat the rise and fall times of a gates input are equal to orless than the rise and fall times of the gates output. Forthis condition, the short circuit power will be a small frac-tion of the total power dissipation [1]. Figure 330(a)shows the input and output waveforms of an inverter driv-

ing a capacitive load. As the input fall time increases, theshort circuit current also increases. Figure 330(b) showsthe ratio of short circuit current to total current versus theratio of output rise (fall) time to input (rise) fall time.Since most designs keep the input and output trfapproxi-mately the same, short circuit power largely can beignored relative to dynamic power.

In general, the total CMOS power dissipation is quitelow when compared to other digital technologies. How-ever, as clock frequencies continually increase, thedynamic power in CMOS digital integrated circuits isbecoming large to the point of becoming the limiting con-straint. One important method to significantly reduce thispower is to lower the power-supply voltage, since thisreduces dynamic power dissipation quadratically. Thepower-supply voltage in modern technologies with gatelengths of 45 nm is around 1.0 V.

Figure 330: (a) Varying input fall time for an inverter driving a capacitive load.(b) The percentageof short circuit current to total current versus the ratio of input to output rise(fall) times.

0 5 100

0.5

1

1.5

2

2.5

3

Volta

ge(V)

Time (ns)

in

out

1 2 3 40

10

20

30

40

Input trf/ Outputtrf (s/s)

ISC/Itotal(%)

(a) (b)


31/34


32/34


Problems

P3.1 Noise often comes from capacitive coupling betweenclock lines and our signal of interest, as shown in FigureP3-1. Given VOH = 2.7V, VOL = 0.3 V, VIH = 1.8 V andVIL = 1.3 V

(a) Calculate NMHand NML.

(b) Find the maximum value for C1given the noise mar-gins calculated in (a). (Hint: Recall that

.

(c) To improve the immunity to capacitive coupling wecould increase the size of C2by 2X. What is the newvalue of C1 which can be tolerated? (Note: Thismethod of reducing coupling also increases propaga-tion delay.)

P3.2 Given an nMOS inverter with a pull-up resistor of

1k (that replaces the pMOS)(a) Find the W/L of the nMOS transistor such that

VOL = 0.5 V

(b) For the nMOS device size found in (a), calculateNMHand NML. Use the simplified hand calculationmethod that linearizes the gain.

(c) Repeat (a) and (b) for a pull-up resistor of 10 k.

P3.3 Repeat Problem P3.2 for a pMOS inverter with apull-up resistor of 1 k.

P3.4 In this problem, compare an nMOS and pMOS

inverter with a current source pull-up as shown in FigureP3-4. Size the n- and p-channel devices such thatVM = 1.5 V for both cases. Choose the smaller device sizeto be 2/1.0.

(a) For the nMOS case in Figure P3-4(a), calculate VOH,VOL , andAvgiven that the gate of the p-channel pull-up device is tied to VB = 2.0 V.

(b) For the pMOS case in Figure P3-4(b), calculate VOH,VOLandAv given that the gate of the n-channel pull-down device is tied to VB = 1.5 V.

P3.5 For the nMOS inverter with current source pull-upshown in Figure P3-4(a) with (W/L)n = (W/L)p = 4/1.0 andVB = 2.0 V

(a) CalculatetPHLand tPLHif the inverter is loaded onlyby an identical inverter. Include C

DB for both the

nMOS and pMOS transistors.

(b) Calculate tPHLand tPLHif the inverter is loaded withthree identical inverters.

(c) Assume that the system must have a clock withperiod T10tp, where tpis the average propagationdelay. Find the maximum length of interconnect

Figure P3-1

C2= 0.5 pF

C1

outin

5 V

0 V

1 2

V V C1 C1 C2+( )=

Figure P3-4

VB

Vin VoutCL

M2

M1

VDD

(a)

+

Vin

VB Vout

M2

M1

VDD

(b)

+

CL


33/34


wires from the output of the inverter to the inputs ofthe next stages for a fan-out of 3 if we want the systemclock to run at 50 MHz. Assume the width of theinterconnect is 4 m and the capacitance of the wiresare 0.05 fF/m2.

P3.6 An nMOS inverter with current source pull-up

shown in Figure 3-4(a), has (W/L)n = 4/1.0, and(W/L)p = 2/4, and VB = 0 V. Use the simplified hand-calcu-lation method. Assume devices are in their constant-cur-rent region.

(a) Sketch the voltage transfer characteristic and labelVIL,VIH, VM, VOHand VOL.

(b) If a 100 -fF load capacitor is connected to the outputof the inverter, calculate the propagation delay tp.Neglect CDBfor this part.

(c) Calculate tpincluding CDB.

(d) What is the static power consumed by this circuit?

(e) Calculate the device widths such that CDB = 100 fFwhile maintaining the same VM.

(f) What is tpfor the device sizes calculated in part (e)?

P3.7 To explore how the noise margin can change withdevice sizing in a CMOS inverter, calculate VM, NMH, andNMLwhen

(a) (W/L)n = 1 and (W/L)p = 2

(b) (W/L)n = 10 and (W/L)p = 0.2

(c) (W/L)n = 0.1 and (W/L)p = 20

P3.8 In this problem, we will explore the accuracy of our

simplified equation Eq. (3.33), to calculate tPHL for theCMOS inverter.

(a) Write a differential equation that is valid when thenMOS transistor is saturated that relates the devicecurrent andcapacitor current in termsof Vout(t).

(b) Write another differential equation that is valid whenthe nMOS transistor is in the triode region thatrelates the device current andcapacitor current.

(c) Solve these equations and write an expression fortPHL, that is the time it takes for the output voltage todrop from VOHto VOH/2.

(d) For an nMOS transistor with W/L = 4/1.0 andCL = 100 fF, solve for tPHLusing the expression foundin (c) and compare it with the value found fromEq. (5.30).

(e) Repeat (d) for W/L = 20/1.0 and CL = 500 fF.

P3.9 In this problem, you will size a CMOS inverter withprocess parameters:

VTn = 0.5 V, VTp = 0.7 V,n = 50 cm2/Vs,

p = 20 cm2/Vs, tox = 20 nm, n=p = 0.05 V

1.

Assume equal channel lengths, VDD = 3 V and allother process parameters are unchanged.

(a) Calculate the ratio Wn/Wpsuch that VM = 1.5 V

(b) When Vin = VM we want the current through theinverter to be 1mA. What are WnandWpassuming thechannel length of both devices is 1.5 m?

(c) Sketch and label the voltage transfer characteristic.

(d) What are NMLand NMH?

P3.10 The CMOS inverter which you have sized in Prob-lem P3.9 must drive two identical inverters connected inparallel, as shown in Figure 321. Using process parame-ters from Problem P3.9,

(a) What is the component of load capacitance for thedrainbulk capacitance from your inverter?

(b) What is the component of load capacitance from thetwo additional inverters?

(c) CalculatetPHLand tPLH.

P3.11 With a greater emphasis on portable electronics,CMOS logic is being designed with lower power-supplyvoltages to reduce power dissipation. In this problem, wewill investigate the changes in the voltage transfer func-tion and the propagation delay when the power supply isreduced. You are given a CMOS inverter driving threeidentical inverters with (W/L)n = 2/1.0 and (W/L)p = 4/1.0.

(a) Sketch the voltage transfer function for VDD

= 3 V.

(b) Calculate tPHLandtPLH.

(c) What is the dynamic power dissipation when theinverter is running at 50 MHz

(d) Repeat (a) through (c) withVDD = 1.8 V.

P3.12 In Problem P3.11 we saw that the power dissipationwas significantly reduced with the reduction of the powersupply voltage at the expense of noise margin and propa-gation delay. Modern processes are using reduced thresh-old voltages to reduce this problem. RepeatProblem P3.11 with VTn = VTp = 0.4 V.

P3.13 Given a minimum-geometry CMOS inverter with(W/L)n = 2/1.0 and (W/L)p = 4/1.0, what is the maximumfan-out possible while keeping tPLHand tPHL 600 ps? Cal-culate with

(a) VDD = 3 V

(b) VDD = 1.8 V


34/34


P3.14 How many identical inverters with

(a) (W/L)n = 2/1.0 and (W/L)p = 4/1.0

(b) (W/L)n = 20/1.0 and (W/L)p = 40/1.0

(c) (W/L)n = 100/1.0 and (W/L)p = 200/1.0

can be driven by a single inverter, if the propagation delay

must be less than 10x larger than that of the unloaded sin-gle inverter? For the unloaded inverter, neglect wiringcapacitance but include CDB.

P3.15 For the device data and inverter sizes given inExample 3-4, what is the maximum wire length betweenthe first inverter and inverters 2 and 3 for tp 1ns?Assume that Cwire = 0.1 fF/m.

P3.16 A figure of merit for a digital technology is thepower-delay product, PDtp. Plot the power-delay productas a function of VDDfor 1.25 V VDD 3 V. For this calcu-lation, use a CMOS inverter with (W/L)n = 2/1.0 and

(W/L)p = 4/1.0 driving three identical inverters (fan-out = 3). Assume a clock frequency of 50 MHz.

Design Problems

For these design problems, the technology restrictsW> 2 m and L > 1.0 m.

D3.1 You are to design an nMOS inverter with resistorpull-up to drive a load capacitance of 0.3 pF. The RCtimeconstant must be less than 1 ns. Size the nMOS transistor

such that VM = 1.5 V and NMLand NMH0.8 V. Minimizethe power dissipation.

(a) For the initial design neglect CDB.

(b) Include CDBfor the refined design.

(c) Verify your design in SPICE

D3.2 Repeat the design in Problem D3.1 with a pMOSinverter with resistor pull-up.

D3.3 The goal of this problem is to determine the numberof identical inverters that a CMOS inverter can drive,given that they are far away from the driving inverter.

(a) Calculate the component of load capacitance from asingle inverter load, CG. The device sizes for theinverter are (W/L)n = 4/1.0 and (W/L)p = 8/1.0

(b) The load inverters are located 1000 m from the driv-ing inverter. The connecting wire is 2-m wide alumi-num and lies on a deposited glass and field oxidelayer. The total thickness of the dielectric layer is1.0 m and you can assume it behaves like a parallelcapacitor. The permittivity of the dielectric is 3.9o.

What is the parasitic capacitance resulting from driv-ing one inverter? Include both wiring and drainbulkcapacitance.

(c) Calculate tPHLand tPLHfor a single inverter load.

(d) The specifications of the system you are designinghas a clock rate of 50 MHz, and during each clockphase, a signal may experience a maximum of 25propagation delays. Using a 20 percent safety margi

calhoun sample ch3 (1)

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