chap. 3 describing logic circuits 3-1microcom.koreatech.ac.kr/course...

Digital Systems© Korea Univ. of Tech. & Edu.

Dept. of Info. & Comm.Chap. 3 Logic Gates/Boolean Algebra

3-1Chap. 3 Describing Logic Circuits

Chapter Outcomes (Objectives)

Perform the three basic logic operations. Describe the operation of and construct the truth tables for the AND, NAND,

OR, and NOR gates, and the NOT (INVERTER) circuit. Draw timing diagrams for the various logic-circuit gates. Write the Boolean expression for the logic gates and combinations of logic

gates. Implement logic circuits using basic AND, OR, and NOT gates. Use Boolean algebra to simplify complex logic circuits. Use DeMorgan’s theorems to simplify logic expressions. Use either of the universal gates (NAND or NOR) to implement a circuit

represented by a Boolean expression. Explain the advantages of constructing a logic-circuit diagram using the

alternate gate symbols versus the standard logic-gate symbols. Describe the concept of active-LOW and active-HIGH logic signals.




Chapter Outcomes (Objectives) – cont.

Describe and measure propagation delay time. Use several methods to describe the operation of logic circuits. Interpret simple circuits defined by a hardware description language (HDL). Explain the difference between an HDL and a computer programming

language. Create an HDL file for a simple logic gate. Create an HDL file for combinational circuits with intermediate variables.




Logic Gates : the basic elements of logic circuits(AND, OR, NOT,...) Boolean Algebra

A tool for the analysis and design of digital systems Describes relationship between logic circuit’s inputs and outputs Used to help simplify a logic circuit

3-1 Boolean constants and variables

Only two possible values (Many different terms used synonymously)

Logic level 0 Low /1 High 0 and 1 do not present actual

numbers but instead represent the state of a voltage variable(High/Low)

3-2 Truth tables Describing how a logic circuit’s

output depends on the logic level of circuit’s input(2N possible inputs)

Fig. 3-1 Truth Table(2, 3, 4 inputs)

Logic 0 Logic 1FALSE TRUE

Off OnLow HighNo Yes

Open Close

A B x

0 0 1

0 1 0

1 0 1

1 1 0

A B C x0 0 0 00 0 1 10 1 0 10 1 1 01 0 0 01 0 1 01 1 0 01 1 1 1

A B C D x0 0 0 0 00 0 0 1 10 0 1 0 10 0 1 1 00 1 0 0 00 1 0 1 00 1 1 0 00 1 1 1 11 0 0 0 11 0 0 1 11 0 1 0 01 0 1 1 01 1 0 0 01 1 0 1 01 1 1 0 11 1 1 1 1

?AB

x

Tab. 3-1 Fig. 3-1

(a)

(b)(c)

Tab. 3-1



3-4

3-3 OR Operation with OR gates Output x is a logic 1 if one or more inputs are 1 Boolean expression : x = A + B

x= 1 + 1 = 1, x = 1 + 1 + 1 = 1, x = 1 + 1 + …+ 1 = 1

OR Gate : Fig. 3-2(b) Multiple input OR Gate : Fig. 3-3 Summary of the OR operation Exam. 3-1, 3-2, 3-3A, 3-3B

3-4 AND Operation with AND gates Output x is 1 only when all inputs are 1 Boolean expression : x = AB = A•B AND Gate : Fig. 3-7(b) Multiple input AND Gate : Fig. 3-8 Summary of the AND operation Exam. 3-4, 3-5A, 3-5B

A B x= A+B

0 0 0

0 1 1

1 0 1

1 1 1

A B C x= A+B+C0 0 0 00 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 11 1 1 1

Fig. 3-2 Truth Table and Symbol Fig. 3-3 Three-input OR

AB

ABC

X= A+B X= A+B+C

A B x= AB

0 0 0

0 1 0

1 0 0

1 1 1

A B C x= ABC0 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 1

X= ABAB

Fig. 3-7 Truth Table and Symbol

X= ABCABC

Fig. 3-8 Three-input AND

(b)

(a)

(b)

(a)

Fig. 3-2(a)

Fig. 3-7(a)



3-5

3-5 NOT Operation Single input operation, Complement of input NOT operation : x= A NOT circuit : Inverter(Fig. 3-11(b)) App. 3-1 : typical application of NOT gate

(pressed=0, not pressed =1) Fig. 3-12 3-6 Describing Logic Circuits Algebraically

Boolean logic can describe any logic circuit by Boolean expression. Order of precedence : Parentheses, NOT, AND, OR (Next Slide) AꞏB+C can be interpreted in various ways : Fig. 3-13

1) (AꞏB)+C, 2) Aꞏ(B+C) Circuits containing Inverter : Fig.3-14, Fig.3-15

3-7 Evaluating Logic Circuit Output Given a Boolean expression

Evaluate output for given inputs Exam. : Fig. 3-15(a)

» A=0, B=1, C=1, D=1, x=0 Exam. : Fig. 3-15(b)

» A=0, B=0, C=1, D=1, E=1, x=1 00111

)1(111

)10(111

)10(110

)(

DABCAx

111

1]11[1]01[

1]101[

1]1)00(1[

])([

ECBADx

A x= A'

0 1

1 0

Fig. 3-11 Truth Table, Symbol, waveform

AX= A

1A

0 1

x 0

(a)

(b)

Fig. 3-11(a)



3-6

Evaluation rule for Boolean expression1) Perform all inversions of single terms2) Perform all operations within parentheses3) Perform an AND operation before an OR operation4) If an expression has a bar over it, perform the expression first and then

invert the result Determining output level from a diagram

The output can be determined directly from the circuit diagram without using Boolean expression.

Analysis Using a Table The best way to analyze a combinational logic circuit Analyze one gate or logic combination at a time Easily double check your work Benefit in troubleshooting the logic circuit

Fig. 3-15(a) Determining the output from a diagram

AB C

Dx1 0

00

01

1

1

11

)( zyx



3-7

Analysis of a logic circuit using truth tables : Fig. 3-161) List all input combinations : A, B, C2) Create column for each intermediate signal (node) : u, v, w neither inputs nor output3) Fill the u, v, and w4) Fill the output x

Exam. 3-6 : Analyze the operation of Fig. 3-15(a) 3-8 Implementing circuits from Boolean expression

Circuit can be implemented from expression

Exam. 3-7 : draw circuit diagram Fig.3-18

BCACBACy

BCACBACy AC

BCACB

Fig. 3-17 Constructing a logic circuit from a Boolean expression

AC

CB

BCA

A

B C

BCACBACy



3-8

3-9 NOR gates and NAND gates NOR gate : Exam. 3-8, 3-9 NAND gate : Exam. 3-10, 3-11, 3-12

3-10 Boolean Theorems Single variable theorems Fig. 3-25(1)….(8)

x • 0 = 0, x • 1 = x, x • x = x, x • x = 0 x + 0 = x, x + 1 = 1, x + x = x, x + x = 1

Multivariable theorems x + y = y + x, x•y = y•x x + (y + z) = (x + y)+ z = x + y + z, x (yz) = (xy)z = xyz, x (y + z) = xy + xz, (w + x)(y + z) = wy + xy + wz + xz x + xy = x : P.114 Truth Table or x + xy = x(1+y) = x•1= x x + xy = x + y : (x + x)•(x + y) = 1 •(x + y) = x + y x + xy = x + y : (x + x)•(x + y) = 1 •(x + y) = x + y

Exam. 3-13, 3-14, 3-15

BAx

BAx

Commutative lawsAssociative laws

Distributive laws

A B A+B A+B

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

A B AB AB

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0

BAx BAx

Fig. 3-19 NOR Gate Fig. 3-22 NAND Gate



3-9

3-11 DeMorgan’s Theorems DeMorgan’s Theorems

Exam.

yxyx )(yxyx )(

zyxzyx )(zyxzyx )(

yxyx

yxyx

yx yxyx

yxyx

yx yxyx

yxyx

Fig. 3-26, 27 Equivalent circuits implied by DeMorgans Theorems

Exam. Exam. Exam. 3-16

CBCACBACBA

CBA

CBAx

)()(

)(

)(

)()(

)(

CBACBA

CBA

CBAz

FDEDCABAFEDCBA

EFDBCA

EFDBCA

EFDBCAw

)]([)]([)()(

)()(

)()(

EFCDABEFCDAB

EFCDABx

DBCADBCA

DBCA

DBCAz

)()(

)()(

)()( Exam.

Exam. 3-17 : Determine the output expression and simplify it using DeMorgan Theorems

CBACBA

CBAz



3-10

3-12 Universality of NAND and NOR gates Implement any logic expression using only NAND or NOR gates

Exam. 3-18 : A conveyer belt will shut down whenever specific conditionsoccur(x = AB + CD)

74LS00 NAND, 74LS08 AND, 74LS32 OR gate 사용(Fig. 3-31)

AAAx

AAAx

BA BA ABx BAx

A

B

A

B

BABAx BABAx

Fig. 3-29 & 3-30 NAND/NOR gates can be used to implement any Boolean operation

Fig. 3-32 Possible implementation



3-11

3-13 Alternate Logic-Gate Representations Standard Logic Symbols : AND, OR, Inverter, NAND, NOR Alternate Logic Symbols : Fig. 3-33

1) Add bubbles on input and output lines that do not have bubbles, and Remove bubbles that are already there

2) Change the operation symbol from AND to OR, or from OR to AND(Inverter is not changed)

Note:» The equivalence can be extended to gates with any

number of inputs» None of the standard symbols have bubbles on their

inputs, but all the alternate symbols have bubbles on their inputs

» The standard and alternate symbols for each gate represent the same physical circuit(No differences)

» NAND and NOR gates are inverting gates(both the standard and the alternate symbols have a bubble on either the input or the output)

» AND and OR gates are non-inverting gates(the alternate symbols have bubbles on both inputs andoutputs)

BABA

BABA

BABA

BABA

AA

BA

BA

BA

BA

Fig. 3-33 Standard and alternate symbols

no bubble bubble



3-12

Logic Symbol Interpretation Active-HIGH : An input or output line has no bubbles Active-LOW : An input or output line does have bubbles

Exam. 3-19 : Give the interpretation of the two OR gate symbols

3-14 Which Gate Representation to Use Proper use of the alternate gate can make the circuit operation much clear: (d) truth table

Fig. 3-34 Interpretation of the two NAND gates

Fig. 3-35 Interpretation of the two OR gates

BA BABA

Active-LOWActive-HIGH Active-LOW Active-HIGH

Output goes LOW only when all inputs are HIGH

Output goes HIGH only when any inputs are LOW

Output goes HIGH only when any inputs are HIGH

Output goes LOW only when all inputs are LOW

BA BABA

Active-HIGH

Output goes HIGHwhenever either

A=B=1 or C=D=1

Output goes LOW only when A or B=0 and

C or D=0

Active-LOW

Fig. 3-36 Alternate Representation(a) original (b) active high (c) active low



3-13

Which Circuit Diagram Should be Used? The answer to this question depends on the particular function being

performed by the circuit output» If the circuit is used to turn on/off an LED, Relay, or Motor

Active-HIGH : On when output goes to 1 Active-LOW : On when output goes to 0

Bubble Placement Whenever possible, choose gate symbols so that

» Bubble outputs connected to bubble inputs(Fig. 3-36 (b))» Non-bubble outputs connected to non-bubble inputs(Fig. 3-36 (c))

Exam. 3-20, 21, 22, 23 Asserted Levels

Asserted = Active Unasserted = Inactive

Labeling Active-LOW Logic Signals Over-bar = Active Low Signal

Labeling Bi-state Signals Output signals have two active states

Address Decode 회로

MEMRAMBROMAROMRD ,,,,

DATACONTWRRD /,/



3-14

3-15 Propagation Delay Propagation delay is the time it takes for a system to produce the

appropriate output after it receives an input. An AND gate serves as an example that propagation delay does exist

and that it can be measured : Fig. 3-41(a) Two things are important to note from the timing diagram in Fig. 3-41(b)

1. Transitions are not truly vertical(instantaneous) so we measure from the 50% point on the input to the 50% point on the output

2. The time it takes to make the output to High is not necessarily the same as the time to make the output go Low. These delay times are called t PLH

and t PHL : Fig. 8-2 Chapter 8 will provide more information about the inner workings of

logic ICs : Fig. 8-8 The speed of a logic circuit is related to this characteristic of

propagation delay. Whatever part is chosen to implement the logic circuit will have a data

sheet that states the value of propagation delay : Fig. 8-11



3-15

IEEE/ANSI standard Logic Symbols Compare the IEEE/ANSI symbols to

traditional symbols These symbols are not widely accepted

but may appear in some schematics. Symbol descriptions

Rectangular symbols represent logic gates and circuits.

The notation inside symbols show how output depends on inputs.

A small triangle replaces the inversion bubble.

Standard Logic Symbol;(a) traditional; (b) IEEE/ANSI



3-16

3-16 Summary of Methods to Describe Logic Circuits 1. We must be able to represent these logical decisions.

The three basic logic functions are AND, OR, and NOT. 2. We must be able to combine these logic functions and implement a

decision-making system. If it is raining OR it looks like rain I will take an umbrella. If I get paid AND I go to the bank I will have money to spend.

Seatbelt warning indicator in a car : Exam. 3-24 3-17 Description Languages vs. Programming Languages

HDL – Hardware Description Languages to represent logic circuits. AHDL – Altera Hardware Description Language (Altera). VHDL – Very high speed integrated circuit Hardware Description Language

(DoD, IEEE). Hardware Description Languages vs. Programming Languages : Exam. 3-25

Hardware Description Language : to describe the hardware configuration of a circuit (Concurrent)

Programming Language : to represent a sequence of instructions intended to be carried out by a computer to accomplish some task (Sequential)- Fig. 3-43

AND gateHardware

AND program



3-17

3-18 Implementing Logic Circuits with PLDs : Fig. 3-44 Programmable Logic Devices (PLDs) are devices that can be configured

in many ways to perform logic functions. Internal connections are made electronically to program devices.

1 – connected, 0 – not connected The hardware description language defines the connections to be made

and is loaded into the device after translation by a compiler. Compiler :

A special application software to translate from the HDL into the grid of 1s and 0s that can be loaded into the PLD.

In details : Fig. 13-3 PLD Basic (next slide) 3-19 HDL Format and Syntax

Languages (interpreted by computers) must follows strict rules of syntax. Syntax refers to the order of elements.

Format refers to a definition of inputs, outputs, and how the output responds to the input (operation). Format of HDL files Fig. 3-46 Inputs and outputs may be called ports (the left & right of Fig. 3-45) – I/O

definitions How the output responds to the input (the middle of Fig. 3-45) – Functional

description



3-18

PLD Basic



3-19

Boolean Description using AHDL Figure 3-47 defines an AND gate. The keyword SUBDESIGN names the circuit block, in this case and_gate The input and output definitions are enclosed in parenthesis. Variables are

separated by commas and follows by :INPUT; / :OUTPUT;. The logic section is between the BEGIN and END keywords. Operators

are: & = AND, # = OR, ! = NOT, $ = XOR

Boolean Description using VHDL Figure 3-48 defines an AND gate. The keyword ENTITY names the circuit block, in this case and_gate The keyword PORT defines the inputs and outputs. The keyword ARCHITECTURE describes the operation inside the block.

ARCHITECTURE name : ckt The BEGIN and END contain a description of the operation



3-20

3-20 Intermediate Signals Buried nodes or local signals in HDL are reference points inside a circuit

block that are not inputs or outputs. (Signal m in Fig. 3-49) AHDL Buried Nodes : Fig. 3-50

Keyword VARIABLE defines intermediate signal. Keyword NODE designates the nature of the variable.

VHDL Local Signals : Fig. 3-51 Keyword SIGNAL defines intermediate signal. Keyword BIT designates the type of signal

chap. 3 describing logic circuits 3-1microcom.koreatech.ac.kr/course...

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