chapter 3 singel stage amplifier

8/13/2019 Chapter 3 Singel Stage Amplifier

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Single Stage Amplifier


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Common Source Amplifier

Source Follower

Common Drain


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Common Source Amplifier

Resistive Load

Diode Connected

Current Source Load Triode Load

Source Degeneration


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CS with Resistive Load


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CS with Resistive Load

W/L=35.6 um/0.6um


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Small Input Signal

Amplitude of input: 2 mV (peak to peak)Amplitude of output: 19.5 (peak to peak)

Av=9.75


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Small Signal Operation


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Calculation of Small Signal Gain

(Valid only for device in saturation region)


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Small Signal Model

1. small signal analysis2. the intuitive approach


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Numerical Calculation

Small Signal Gain:

gm=2 mS

ro=1/gds=22.288 Kohms

RD=6 Kohms

AV=-gm(roRD/(ro+RD))=-9.454


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What if the magnitude of the

input signal is increased?

Distortion is observed when Vin swings high.


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Triode Region (1)Triode

Region

Reduction of transconductance

in the triode region


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Triode Region (2)

Disadvantage of resistively loaded CS:The DC level of Vout is tied to the AV.

An increase of RD will increase AV, but at the price of pushingthe transistor closer into the triode re ion.


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Diode Connected Load

Common Source


NFET Implementation

PFET Implementation


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Impedance:

(Body Effect ignored.)

Useful when tightly controlled resistors are not available,or physically not realizable.


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Diode Connected Load With

Body Effect


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Example

M1: W/L=4.62 um/0.6umBias Current: 100 uAg

m2=8 mS

gds2=35.43 uSgmbs2=100.6 uSRX=1,068 Ohms


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CS Stage with Diode Connected

Load

Not sensitive of biascurrent, e.g. gm

Better linearity.


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Diode Connected Load (NFET)

W/L_To=35.6 um/0.6um; W/L_T1=4.62 um/0.6um


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Amplitude of input: 2 mV (peak to peak)Amplitude of output: 4.447 mV (peak to peak)

Av=2.22


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Design Issue

If the bias current is fixed and the dcVout (VGS) is fixed, then (W/L) of theload is fixed.

It maybe difficult to increase Av.


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Diode Connected PFET with CS


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Plot

Amplitude of input: 2 mV (peak to peak)Amplitude of output: 15.24 mV (peak to peak)

Av=7.62


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Gain Calculation

M1: W/L=6.00 um/0.6umBias Current: 100 uACurrent source: 75 uAgm=2 mSgm2=200 uS

gds2=4.69 uSgds=44.8 uS

Av=-8.013


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CS Stage with Current Source

Load

ro2depends on L and IDof a transistor.|VDS2,min=VGS-Vth2| can be reduced by increasing the width of M2.

Downside: the DC output voltage is not well-defined.


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Spice Example


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Sensitivty

Even a slight deviation in the gate voltage of PFET is enoughto change the output voltage signficantly.

E.g. Sensitivity of output voltage around 0.6 V.


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Calculation:

W/L for T2: 24.06um/0.6um

ro1=22.288 Kohm

ro2=53.20 Kohm

gm=2 mSAv=-31.41

Ideal Vout=0.6 V

Vth2=-0.269Vod=-0.213

Vb=717.64 mV


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CS Stage with Triode Load

Disadvantage: Sensitivity to a precise Vb.Advantage: Vout, max=VDD


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CS Stage with Source

Degeneration

Intuition

Small signal gain

Output resistance


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Intuition

Vin, ID, VSvin is dropped across RS, thus leading to asmoother variation of ID.


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Small Signal Gain

If gmRS>>1, AVis approximately RD/RSID=Vin/RS


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Effective Gm with Non-

negligible body effect


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Gain By Inspection

Interpretation: The resistance at the drain

Divided by the resistance in the source path


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Determination of Gain by

Inspection Example


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Output Resistance

Homework: Derive the output resistance using the small

equivalent circuit


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A More Intuitive Approach


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Analysis


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Norton Equivalent Circuit


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Gain of a Degenerated Current

Source

Conductance with body effectOutput Resistance

chapter 3 singel stage amplifier

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