session-04-current mirror and single stage amplifier

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©M S Ramaiah School of Advanced Studies - Bangalore

Current Mirrors and Single Stage Amplifiers

Session Speaker Chandramohan P

Session - 04

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Session Objectives

• To understand and design sub blocks of analog circuits design

• To understand the concept of current mirrors and current sources/sinks

• To design current mirrors and current sources/sinks• To model and simulate subcircuits using spice• To understand the single stage amplifiers

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Session Topics

• Current mirrors– Simple current mirror– Wilson current mirror– Cascode current mirror

• Single stage amplifiers– Common source amplifier– Common drain amplifier– Common gate amplifier– Differential amplifier and design

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Mixed Signal Sub circuits

Each consists of one or more transistors.They are not used by themselves.

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Current sources / sinks

Current sink

Current sourceI

V

I

V

V

I

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Non-ideal current sources / sinks

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Current Mirrors/Current Amplifiers

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Simple MOS Current Mirror

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Simple CMOS Current Mirror

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Current Mirror Design ExampleSimple CMOS Current Mirror

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Simple CMOS Current Mirror

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Cascoding

M1 and M2 are the mirror pair that determines io.

VDS1 and VDS2 matched

go is small

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Cascode Current Mirror

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Small signal model

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Wilson Current Mirror

go is small

VDS1 and VDS2not matched

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Small signal circuit

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Computation of rout

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Characteristics

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Improved Wilson Current Mirror

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SPICE simulation

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Applications of current mirrors

Common source amplifier: Load for C.S. Amp

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Common drain amplifier (source follower)

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Differential input single-ended output gain stage

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Simple Current Mirror Design• Design a NMOS based current mirror which can sink/mirror a current of

30µA. Estimate the output resistance. Also find the device dimensions in order to mirror 30µA of current.

Solution:Assume VGS= 0.7V

RVVI DSDD

D−

=1

The value of R, can be found by assuming ID1= ID2 = 30µA, is determined by solving the equation below

Ω=μ−

=−

=⇒ KI

VVRD

DSDD 66.3630

7.08.1

1

VDD

IRef

M1 M2

ID2= Iout

VGS

+

–

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PEMP VSD 528


Simple Current Mirror Design

22 )(

230 THGS

nD VV

LWKAI −=μ=

2)379924.07.0(5.16530 −××=μLWA

769.1=L

W

Solving for the width of the transistors, since the transistors operate in saturation region

Let L1 = L2= 0.36µm, then W2=0.636µm, which gives W1=0.636µm

The small signal output resistance of the current source is given by

Ω=μ×

=λ

= MAI

ro

o 37.03009.0

11

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Simple Current Mirror Design• SPICE code

NMOS Current Souce / Current Mirror

.include "C:\synopsys\FT07Analog\modelfile018.txt"

R1 Vdd P1 32.5KM1 P1 P1 gnd gnd CMOSN L=0.36U W=0.7UM2 P2 P1 gnd gnd CMOSN L=0.36U W=0.7U

Vdd Vdd gnd dc 1.8V2 P2 gnd dc 0.dc V2 0 1.8 0.01.op.print dc i(M1) i(M2) v(P2) i(R1).end

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Simple Current Mirror Design• Simulation Results

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Cascode Current Mirror• Design a cascode current source with a DC output current

of 50µA and a small signal output resistance of 100MΩ.

Solution

Begin the design by setting the gate voltage of M1 and M3 to ensure that M2and M4 are operating in their constant current region with VD4=0.5V

Let VGS of M1, M2, M3 and M4 be 0.8V, the gate voltage on M4 will be 1.6V

With VGS4=0.8V, it implies that the source of M4, which is the drain of M2 will be at 0.8V

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PEMP VSD 528



2oxn

REFTnGS C

LW

IVVμ

+=

712.1=L

W

Note that VDS(Sat)4 = 0.8V the source of M4 is at 0.8V, the drain voltage must be greater than 0.5V to ensure operation in the constant current region.

Setting the W/L ratio of M1and M3 to yield VGS = 0.8V with Iref = 50µA

5.165

50379924.08.0×

+=

LW

Since VDS2 = 0.8V, Recalling that VGS2 – VTn = 0.8 – 0.379924 = 0.420076V, => VDS2 > VDS(SAT)2

712.13

3

1

1 ==∴LW

LW

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712.14

4

2

2 ==∴LW

LW

244 )( oomS rrgR ⋅=

We can match the (W/L) of M2 and M4 with M1 and M3, respectively, since we want IREF = IOUT

To calculate the small signal output resistance

04.238505.165712.1424 =×××=μ= REFoxnm ICL

Wg

Dnoo I

rrλ

==1

24 Ω=μ×

== Mrr oo 22.05009.0

124

Ω=××=⋅= MrrgR oomS 52.1122.022.004.238)( 244

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Cascode Current Mirror• SPICE code


M1 P3 P3 Gnd Gnd CMOSN L=0.7U W=1.2UM2 P4 P3 Gnd Gnd CMOSN L=0.7U W=1.2UM3 P1 P1 P3 Gnd CMOSN L=0.7U W=1.2UM4 P2 P1 P4 Gnd CMOSN L=0.7U W=1.2U

I1 Vdd P1 dc 50uVdd Vdd Gnd dc 1.8VV1 P2 gnd dc 0.5V

.dc V1 0 1.8 0.01

.Print dc i(M1) i(M2) i(M3) i(M4)

.end

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• Simulation Results

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Common-Source Amplifier

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Common Drain amplifier

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Common Gate Amplifier

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Common Source Amplifier with a Current Mirror Active LoadConsider a common source amplifier with a current mirror active load as shown in the figure. Assume all transistors have W/L = 100μm/1.6μm , and that μnCox=90μA/V2, μpCox=90μA/V2, Ibias = 100μA, rds-n(Ω) = 8,000L(μm)/ID(mA), and rds-p(Ω) = 12,000L(μm)/ID(mA). What is the gain of the stage?

Solution:

We have

Also

and

Therefore

VmAILWCg biasoxnm /06.1)/(2 11 == μ

Ω=×

= kmA

mrds 1281.0

6.1000,81

μ

Ω=×

= kmA

mrds 1921.0

6.1000,122

μ

4.81)192||128(06.1)||( 211 −=−=−= dsdsmV rrgA

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Common Source Amplifier with a Current Mirror Active Load

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Vdd 1 0 dc 5

Ibias 2 0 dc 100u

M3 2 2 1 1 pmos W=200u L=2.6u

M2 3 2 1 1 pmos W=200u L=2.6u

M1 3 4 0 0 nmos W=200u L=2.6u

Vin 4 0 dc 0.849 ac 1

.op

.ac dec 10 1k 10000Meg

.plot ac vdb(3)

.lib C:\Documents and Settings\Desktop\SPICE\CMOS 2U.lib

.end

SPICE CODE

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Frequency Plot for the Common Source Amplifier

The gain is 36dB, which corresponds to 63V/V

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Use the parameters as in example1 along with the following : Rin=180 KΩ, CL= 0.3pF, Cgs1= 0.2pF, Cgd1= 0.015pF, Cdb1= 20fF, and Cdb2= 36fF.Estimate the –3dB frequency of the common-source amplifier shown in the figure.

Solution:

We have

And

Therefore the time constant due to Rin, namely, Rin[Cgs1+ Cgd1(1+A)]=0.26μs.The time constant due to R2, namely, R2[Cgd1+ C2]=0.03μs.The –3-dB frequency (in hertz) is equal to

= 550kHz.

Common Source Amplifier

Ω== krrR dsds 77|| 212

pFCCCC dbdbL 36.0212 =++=

( )[ ] ( )[ ] 121221113 1

21 −

− ++++⎥⎦⎤

⎢⎣⎡= CCRRgCCRf gdmgdgsindB π

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Common Source Amplifier

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Vdd 1 0 dc 5

Ibias 2 0 dc 100u

M3 2 2 1 1 pmos W=400u L=2u

M2 3 2 1 1 pmos W=400u L=2u

M1 3 4 0 0 nmos W=150u L=2u

Rin 5 4 180k

Vin 5 0 dc 0.849 ac 1

Cl 3 0 0.3p

.op


.plot ac vdb(3)

.lib C:\Documents and Settings\Desktop\SPICE\CMOS 2U.lib

.end

SPICE CODE

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Frequency Response for a Common Source Amplifier

The -36dB frequency occurs around 460kHz

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Source Follower Stage with a Current Mirror used to supply bias currentConsider the source follower in the figure where all transistors have W/L = 100μm/1.6μm, μnCox=90μA/V2, μpCox=30μA/V2, Ibias = 100μA, γn= 0.5V1/2 rds-n(Ω) = 8,000L(μm)/ID(mA). What is the gain of the stage?

Solution:We have

Also

Taking body effect into consideration

Consider VSB ≈ 2V

We have

VmAILWCg biasoxnm /06.1)/(2 11 == μ

|2|21FSB

ms V

ggφ

γ+

=

VmAggg mm

s /16.015.07.022

5.01 ==

+×

=∴

VVAV /86.0128/1128/116.006.1

06.1=

+++=

Ω=×

== kmA

mrr dsds 1281.0

6.1000,821

μ

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Source Follower Stage with a Current Mirror used to supply bias current

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Vdd 1 0 dc 5

Ibias 1 2 dc 100u

M3 2 2 0 0 nmos W=80u L=2u

M2 3 2 0 0 nmos W=80u L=2u

M1 1 4 3 0 nmos W=80u L=2u

Vin 4 0 dc 2 ac 1

.op


.plot ac vdb(3)

.lib C:\Documents and Settings\Desktop\SPICE\CMOS CN20.lib

.end

SPICE CODE

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The gain is –1.36dB, which corresponds to 0.86V/V

Frequency Plot for the Source-Follower

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Using the parameters in example2 and assume Rin=180 KΩ, CL= 10pF, Cgs1= 0.2pF, Cgd1= 15pF, Csb1= 40fF, and Cin= 30fF.Find ω0, Q, and the frequency of the zero for the source follower.

Solution:

From example2 we have gm1=1.06mA/V, rds1= 128KΩ, rds2=128kΩand gs1=0.16mA/V

Thus

And so we can find ω0 as)(

)(

1'

1

110

sgsinsgs

smin

CCCCCGgG

+++

=ω

MHzsrad 34.82/1024.5 7 ×=×= π

fFCCC gdinin 451' =+=

VmAgggG dsdsss /176.02111

Step Response of Source Follower

=++=

pFCCC sbLs 04.101 =+=

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= 0.8

This results in an overshoot for a step input given by

Zero frequency , and thus it can be ignored.

1111'

1'

111

)(])()[(

sgssminsin

sgsinsgssmin

GCGgCCGCCCCCGgG

Q+++

+++=

%8100% 14/ 2

== −− Qeovershoot π

MHzC

g

gs

mz 844

1

1 =−

=ω

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Step Response of Source Follower

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Vdd 1 0 dc 5

Vss 2 0 dc -5

Ibias 3 2 dc 100u

Rin 4 0 180k

Cin 4 0 30f

Cl 3 0 5p

M1 1 4 3 2 nmos W=150u L=2u

Iin 4 0 pulse(0 -5u 10n 0 0)

.op

.tran 0.5n 300n

.plot v(3)

.lib C:\Documents and Settings\Desktop\SPICE\CMOS 1.2UL3.lib

.end

SPICE CODE

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Step Response of a Source Follower

The overshoot here is about approx. 10%

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Using the parameters as in example above find the compensation network and the resulting first order and second order poles of the source follower

Solution:

and

The capacitor is a reasonable value to be realized on chip. The resistor can be realized by a MOS transistor biased in the triode(ie., linear) region. Assuming the compensation network is used, the poles of the transfer function then become

And

The speed penalty paid for using the compensation network is quite high, because the pole frequency without compensation was around 8 MHz whereas here the dominant pole is at 3.6 MHz.

pFCCGg

CCgC

sgssm

sgsm 170.0))(( 111

111 =

++≅

Ω≅+

≅ kgCCCC

Rmsgs

sgs 3.49)(

11

21

1

MHzCC

Gpings

in 61.32'1

1 ×=+

≅ π

MHzCCGgp

Lgs

sm 3.192112 ×=

++

= π

Source Follower with Compensation Network

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Source Follower with Compensation Network

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Vdd 1 0 dc 5

Vss 2 0 dc -5

Ibias 3 2 dc 100u

Rin 4 0 180k

Cin 4 0 30f

Cl 3 0 10p

M1 1 4 3 2 nmos W=200u L=2u

Iin 4 0 dc 0 ac 1

C1 4 5 0.17p

R1 5 0 49.3k

.op


.print vdb(3)

.lib C:\Documents and Settings\Desktop\SPICE\CMOS 1.2UL3.lib

.end

SPICE CODE

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The Bode Plot of a Source Follower with compensation network

-20dB/decade

-40dB/decade

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CMOS Differential Amplifier

• Design the currents and W/L values of the current mirror load MOS differential amplifier to satisfy the following specifications:

VDD = -VSS = 1.8VSR ≥ 10V/μs (CL=5pF), f-3dB ≥ 100kHz (CL=5pF), small signal gain of 100V/V, -1V ≤ ICMR ≤ 1.5V Pdiss ≤ 1mW.

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CMOS Differential AmplifierDesign of a CMOS Differential Amplifier with a Current Mirror Load

Design Considerations:

Constraints SpecificationsPower supplyTechnologyTemperature

Small-signal gainFrequency response (CL)ICMRSlew rate (CL)Power dissipation

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• Procedure:– Pick ISS to satisfy the slew rate

knowing CL or the power dissipation

– Check to see if Rout will satisfy the frequency response, if not change ISS or modify circuit

– Design W3/L3 (W4/L4) to satisfy the upper ICMR

– Design W1/L1 (W2/L2) to satisfy the gain

– Design W5/L5 to satisfy the lower ICMR

– Iterate where necessary

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Solution

ApFsVCSRI L μ=×μ=⋅= 505)/10(5

Step1:- To meet the slew rate, and maximum Power Dissipation

( ) 5IVVP SSDDdiss ⋅+= AmWI μ=+

= 7.277)8.18.1(

15

Step2:- To meet the frequency requirement

LoutdB CR ⋅=ω

13

Ω=⋅⋅π

=⇒⋅

=⋅π 33.31847151002

15

11002pFk

RpFR

k outout

)1(505 LLAI μ≥⇒

)2(7.2775 LLAI μ≤⇒

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5)(2

IR

PNout ⋅λ+λ=

AI μ=⋅+

= 888.3433.318471)09.009.0(

25

)3(355 LLAI μ≥⇒

Rout is given by

From Eqns. (1), (2) and (3) We can pick the I5 as approx. 100µA

Step3:- The maximum input common mode voltage gives

VGS3 = VDD – VIC(max) + VTN1 = 1.8 – 1.5 + 0.379924 = 0.6799V ≈ 0.7V

Therefore, we can write

TP

oxP

DSSG V

LWC

IV +

⎟⎟⎠

⎞⎜⎜⎝

⎛μ

⋅=

3

33

2

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508.1

5.1652100 1

1

×

⎟⎟⎠

⎞⎜⎜⎝

⎛××

=LW

4038864.0/36

507.0

3

32

+

⎟⎟⎠

⎞⎜⎜⎝

⎛μ

μ=

LWVA

A

42

11

dsds

moutmV gg

gRgA+

=⋅=

16839.153

3 ≈=⎟⎟⎠

⎞⎜⎜⎝

⎛⇒

LW

Step4:- Using the small signal gain specification gives

3

1

12

)(

2

I

LWI

APN

ds

V λ+λ

⎟⎟⎠

⎞⎜⎜⎝

⎛⋅

=⇒

499425.481

1 ≅=⎟⎟⎠

⎞⎜⎜⎝

⎛LW

Solving for W1/L1 gives

164

4

3

3 ==∴LW

LW

Solving for W1/L1 gives

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1(min))(5 GSSSICsatDS VVVV −−=

491

1

2

2 ==∴LW

LW

Step5:- Using the minimum input common mode voltage gives

TN

oxn

DSSICsatDS V

LWC

IVVV +μ

−−=

1

1

1(min))(5

2

3415.0379924.0495.165

508.11)(5 =+×

−+−=satDSV

18.5)3415.0(5.165

10022

)(5'

5

5

5 =×

==satDSnVK

ILW

This value of VDS5(sat) gives a W5/L5 of

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PEMP VSD 528



491

1

2

2 ==∴LW

LW

164

4

3

3 ==∴LW

LW

55

5 =LW

56

6 =LW

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• SPICE codeCMOS Differential Amplifier with PMOS Current Mirror

M3 P1 P1 Vdd Vdd CMOSP L=1U W=16UM4 Vout P1 Vdd Vdd CMOSP L=1U W=16UM1 P1 Vin+ P2 gnd CMOSN L=1U W= 49UM2 Vout Vin- P2 gnd CMOSN L=1U W=49U M5 P2 P3 Vss Vss CMOSN L=1U W=5UM6 P3 P3 Vss Vss CMOSN L=1U W=5UCload vout gnd 5pF Ibias Vdd P3 100UVdd Vdd Gnd DC 1.8Vin1 Vin+ Gnd DC 0.5 ac 1Vin2 Vin- Gnd DC 0.5 Vss Vss gnd dc -1.8

.AC DEC 25 1 10Meg

.print ac vm(Vout) vdb(vout)

.end

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• Simulation Results

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Summary

• Current mirrors are used as current references and as load circuits

• Single stage amplifiers forms the basic building block of analog circuit design

• Single stage amplifiers can be designed carefully taking care of loading conditions and active loads for better gain

• Differential amplifiers form the basic building block of operational amplifiers