chapter 5 bist (4in1)

VLSI TESTING 2012 Chapter 5-1

VLSI TESTING

1

CHAPTER 5BUILT-IN SELF-TEST (BIST)

PING-LIANG LAI

VLSI TESTING 2012 Chapter 5-2PING-LIANG LAI

Outline

Introduction Basic Concepts of Logic BIST BIST Design Rules Test Pattern Generation (TPG) and Output Response Analysis

(ORA) Techniques


Introduction (1/2)

What are the problems in todays semiconductor testing? Traditional test techniques become quite expensive No longer provide sufficiently high fault coverage

Todays test requirement Higher fault coverage, smaller test patterns, shorter test cycles, at-speed test,

and better performance-cost ratio

Why do we need built-in self-test (BIST)? Because todays test requirement For mission-critical applications Detect un-modeled faults Provide remote diagnosis


Introduction (2/2)

Implement the function of automatic test equipment (ATE) on circuit under test (CUT)

Hardware added to CUT Test pattern generation (TPG) Output response analysis (ORA) BIST controller

CUT

Stored TestPatterns

StoredResponses

PinElectronics

Comparator

Test Controller

ATE

Traditional test

TPG

ORA

CUT

Go/No-go signature

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BISTEnable

BIST


Basic Concepts of Logic BIST

Circuit Under Test (CUT): usually using full-san DFT BIST Controller: to produce control signal Test Pattern Generator (TPG): generate test pattern to SI (RAM or ROM, Counter,

Pseudorandom pattern generator) Output Response Analyzer (ORA): fault-free value compared to POs and SO


BIST Techniques Categories

On-line BIST Concurrent on-line BIST Non Concurrent on-line BIST

Off-line BIST Functional off-line BIST Structural off-line BIST

Fig. 2. Logic BIST techniques [Abramovici 1994]


BIST Design Rules

Logic BIST requires much more stringent design restrictions when compared to conventional scan

Therefore, when designing a logic BIST system, it is essential that the circuit under test meet all scan design rules and BIST specific design rules, called BIST design rules


BIST Design Rules

Logic BIST requires much more stringent design restrictions when compared to conventional scan Therefore, when designing a logic BIST system, it is essential that the circuit under test

meet all scan design rules and BIST specific design rules, called BIST design rules

Typical X-bounding Methods (BIST_mode = 1)

Fig. 3. Methods for blocking an unknown (X) source


X-bounding Methods

Depending on the nature of each unknown (X) source, several X-bounding methods can be appropriate for use

Common problems Increase the area of the design Impact timing


Test Pattern Generation

Test pattern generators (TPGs) constructed from linear feedback shift registers (LFSRs)

TPG Stored Pattern Exhaustive testing Pseudo-random testing Weighted Pseudorandom Testing Pseudo-exhaustive testing


LFSR

Standard LFSR: consists of n D flip-flops and a selected number of exclusive-OR (XOR) gates

Modular LFSR: each XOR gate placed between two adjacent D flip-flops

Fig. 6. A n-stage (external-XOR) standard LFSR [Golomb 1982]

Fig. 7. A n-stage (internal-XOR) standard LFSR [Golomb 1982]


LFSR Properties

The internal structure of the n-stage LFSR can be described by a characteristic polynomial of degree n, f(x)

nnn xxhxhxhxf 112211)(

Where hi is either 1 or 0,depending on the feedback path


LFSR Properties

Let Si represent the contents of the n-stage LFSR after I shifts of the initial contents, S0, of the LFSR, and Si(x) be the polynomial representation of Si

11

22

2210)(

ninniniiii xSxSxSxSSxS

If T is the smallest positive integer such that f(x) divides 1+xT, then the integer T is called the period of the LFSR


4-stage Standard and Modular LFSRs

4-stage Standard LFSR 4-stage Modular LFSR

f(x) = 1+x+x4

The test sequences generated by each LFSR, when its initial contents, S0, are set to {0001} or S0(x) = x3


Exhaustive Testing

Exhaustive Testing Applying exhaustive patterns to a n-input combinational circuit under test

(CUT)

Exhaustive pattern generator Binary counter Complete LFSR


Binary Counter

Example binary counter as EPG [Wakerly 2000] Simple to design but require more hardware than LFSRs


Complete LFSR (CFSR)

Example complete LFSRs (CFSRs) as EPG


Exhaustive Testing Performance

Exhaustive Testing guarantees all detectable, combinational faults will be detected

Test time maybe be prohibitively long if input number is large than 20 and is thus not recommended A techniques called Pseudo-Random Testing are aimed at reducing the

number of test patterns


Pseudo-Random Testing

Pseudo-random pattern generator Reduce test length but sacrifice the fault coverage Difficult to determine the required test length and fault coverage Types of modified LFSR for Pseudo-random

Maximum-length LFSR RP-resistant problem (Random-pattern resistant)

Weighted LFSR Cellular Automata


RP-Resistant Problem

Either the probability of certain nodes randomly receiving a 0 or 1, or the probability of observing certain nodes at the circuit outputs is low RP-resistant faults


Output Response Analysis (ORA)

For BIST operations, it is impossible to store all output responses on-chip, on-board, or in-system to perform bit-by-bit comparison.

Instead, output responses compacted into a signature and compared with a golden signature Compaction signature: lossy Compression signature: loss-less Error masking: the faulty and fault-free signatures are the same Alias: erroneous output response is said to be an alias of the correct output

response [Abramovici 1994]

Three output response compaction techniques Ones count testing Transition count testing Signature analysis


Ones Count Testing

Assume the CUT has one output and the output contains a stream of L bits. Let the fault-free output response be

R0 = {r0, r1, r2, , rL-1}

Ones count testing will need a counter to count the number of 1s in the bit stream For example: if R0={0101100}, then the signature or ones count of R0,

OC(R0)=3 Erroneous response R1 = {1100110}, then it is detectable because OC(R1) = 4 R2 = {0101010} is not detectable

Aliasing probability: L-bit stream and ones count be m [Savir 1985]

POC(m)={C(L, m)-1}/(2L-1)


Ones Count Testing

Ones count test circuit for testing the CUT with T patterns The number of stages in the counter must be

)1(log2 L


Transition Count Testing

Transition count testing is similar to that for ones count testing, except the signature is defined as the number of 1-to-0 and 0-to-1 transitions [Hayes 1976] Aliasing probability: L-bit stream and transition count be m [Savir 1985]

PTC(m)={2C(L-1, m)-1}/(2L-1)


Signature Analysis

Signature analysis is the most popular compaction technique used today, based on cyclic redundancy checking

Two signature analysis schemes Serial signature analysis: for compacting responses from a CUT having a

single output Parallel signature analysis: for compacting responses from a CUT having

multiple outputs


Serial Signature Analysis

N-stage single-input signature register (SISR)

Define L-bit output sequence M = {m0m1m2mL-1}

M(x) = m0+m1x1+m2x2++mL-1xL-1

Let the polynomial of the modular be f(x) IF M(x) = q(x)f(x) + r(x), then signature is the polynomial remainder, r(x)


Example 1

A 4-stage SISR


Response Analyzer using LFSR

Response analyzer design methodology Additional XOR gate instead of original input of specific LFSR

Property There are n FFs, thus must have xn and constant term 1 From the input, if the output of kth FF have XOR gate, then must have xk

Example 1: f(x) = x5+x4+x2+1

Input Output


Example 2 (1/2)

M(x) = x7+x6+x5+x4+x2+1 f(x) = x3+x2+1

Input Output

Pass/Fail


Example 2 (2/2)

Divider Polynomial: f(x) = x3+x2+1Dividend: M(x) = x7+x6+x5+x4+x2+1 Quotient: q(x) = x4+x2+x+1 Remainder: r(x) = x2+xWhere M(x) = f(x)q(x)+r(x)

Output Q3Q2Q1 Input000 11110101001 1110101011 110101111 10101

1 010 010110 100 101

101 100 011011 101 1

10111 110Quotient Remainder


Problems in Serial Signature Analysis

One count testing, transition count testing and serial signature analysis have the excessive hardware cost to test an m-output CUT Using an m-to-1 multiplexer, but this increases the test time m times

An parallel signature analysis called Multiple-Input Signature Register (MISR) had presented N-stage MISR using n extra XOR gates for compacting n L-bit output

sequences, M0 to Mn-1, into the modular LFSR simultaneously


Parallel Signature Analysis

Multiple-input signature register (MISR) [Hassan 1984]

An n-input MISR can be remodeled as a single-input SISR with effective input sequence M(x) and effective error polynomial E(x)

M(x) = M0(x)+xM1(x)++xn-2M2(x)++xn-1Mn-1(x)E(x) = E0(x)+xE1(x)++xn-2E2(x)++xn-1En-1(x)


4-stage MISR

Aliasing probability

PPSA(n) = (2(mLn)1)/(2mL1)

A 4-stage MISR An equivalent M sequence

Divider Polynomial: f(x) = 1+x+x4

chapter 5 bist (4in1)

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