chapter2 manufacturing process

7/27/2019 Chapter2 Manufacturing Process

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EE415 VLSI Design

ManufacturingProcess

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.

and presentation by J.Christiansen/CERN]


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Fabrication

Wafers Processing

Processed

Wafer

Chips

Masks


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Traditional CMOS Process


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A Modern CMOS Process

p-

p-epi

p well n well

p+n+

gate oxide

Al (Cu)

tungsten

SiO2

SiO2

TiSi2

Dual-Well Trench-Isolated CMOS

field oxide

Epi-layer is a high quality crystal grown on thepolished surface of pre-doped silicon wafers for

making CMOS nano devices.


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EE415 VLSI Design

oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single

photolithographic cycle (from [Fullman]).

Photo-Lithographic Process


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Growing the Silicon Ingot

From Smithsonian, 2000


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E-Beam Lithography

As the miniaturization of

IC devices continues,

electron beam exposure

technology is gainingprominence as a

technology for next-

generation design rules

From: ADVANTEST CORPORATION


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EE415 VLSI Design

Silicon Oxidation

The oxide is grown by

exposing the silicon surface

to high temperature steam.

As the oxide grows, thesilicon is consumed. The

arrows represent the direction

of motion of each surface of

the oxide.

Underneath the nitride mask,

the growth is suppressed,

and these areas will become

the active transistor area. Source: Bell Laboratories


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EE415 VLSI Design

Patterning - Photolithography

1. Oxidation

2. Photoresist (PR) coating

3. Stepper exposure

4. Photoresist development andbake

5. Acid etchingUnexposed (negative PR)Exposed (positive PR)

6. Spin, rinse, and dry

7. Processing stepIon implantationPlasma etchingMetal deposition

8. Photoresist removal(ashing)

mask

SiO2 PR

UV light


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EE415 VLSI Design

CMOS Process at a Glance

Define active areas

Etch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers

One full photolithography

sequence per layer

(mask)

Built (roughly) from the

bottom up

5 metal 2

4 metal 1

2 polysilicon3 source and drain

diffusions

1 tubs (aka wells,

active areas)

exception!


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EE415 VLSI Design

Example of Patterning of SiO2

Si-substrate

Silicon base material

Si-substrate

3. Stepper exposure

UV-lightPatternedoptical mask

Exposed resist

1&2. After oxidation and

deposition of negative

photoresist

PhotoresistSiO2

Si-substrate

Si-substrate

SiO2

8. Final result after

removal of resist

Si-substrate

SiO2

5. After etching

Hardened resist

SiO2

Si-substrate

4. After development and

etching of resist, chemical orplasma etch of SiO2

Hardened resist

Chemical or plasmaetch


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Diffusion and IonImplantation

1. Area to be doped is

exposed

(photolithography)

2. Diffusion

or

Ion implantation


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Ion Implantation

1. Dopant atoms are ionized

and then accelerated by an

electric field until they

impinge on the silicon

surface, where they embedthemselves.

2. A polysilicon line crosses

the active area in the upper

left and forms the gate of atransistor.

Source: Bell Laboratories


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EE415 VLSI Design

Deposition and Etching

1. Pattern masking

(photolithography)

2. Deposit material overentire wafer

CVD (Si3N4)

chemical deposition

(polysilicon)

sputtering (Al)

3. Etch away unwanted

materialwet etching

dry (plasma) etching


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Metallization

1. First an insulating glass layeris deposited to cover thesilicon, then contact holesare cut into the glass layerdown to the silicon.

2. Metal is deposited on top ofthe glass, connecting to thedevices through the contactholes.

3. The graphic shows asnapshot during the filling ofa contact hole with

aluminum.Source: Bell Laboratories


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F5112 E-Beam Lithography

Single-Column System

Minimum Feature Size: 100nm

Overlay Accuracy:|mean|+3 sigma


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Planarization: Polishing theWafers

From Smithsonian, 2000


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Self-Aligned Gates

1. Create thin oxide inthe active regions,thick elsewhere

2. Deposit polysilicon

3. Etch thin oxide fromactive region (polyacts as a mask for thediffusion)

4. Implant dopant

Si lifi d CMOS I


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Simplified CMOS InverterP-well Process

cut line

p well


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P-Well Mask


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Active Mask


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Poly Mask


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P+ Select Mask


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N+ Select Mask


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Contact Mask


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Metal Mask


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VLSI Fabrication: The Cycle


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The n-well CMOS process starts with amoderately doped (impurity concentrationless than 1015 cm-3) p-type siliconsubstrate.

Then, an oxide layer is grown on theentire surface. The first lithographic maskdefines the n-well region. Donor atoms,usually phosphorus, are implantedthrough this window in the oxide. Thisdefines, the active areas of the nMOS andpMOS transistors.

Thin gate oxide is grown on top of the

active regions. The thickness and thequality of the gate oxide are criticalfabrication parameters, since they affectthe characteristics of the MOS transistor,and its reliability.

CMOS N-well Process (contd)


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The polysilicon layer is

deposited using chemical

vapor deposition (CVD) and

patterned by dry (plasma)

etching.

The created polysilicon lines

will function as the gate

electrodes of the nMOS and the

pMOS transistors and their

interconnects.

Also, the polysilicon gates act

as self-aligned masks for the

source and drain implantations

that follow this step.


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EE415 VLSI Design


Using a set of two masks, the

n+ and p+ regions are

implanted into the substrate

and into the n- well,

respectively.

The ohmic contacts to the

substrate and to the n-well are

implanted in this process step.


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EE415 VLSI Design


An insulating silicon dioxide

layer is deposited over the

entire wafer using CVD.

Then, the contacts are definedand etched away to expose the

silicon or polysilicon contact

windows.


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Metal is deposited over the

entire chip surface using metal

evaporation, and the metal lines

are patterned through etching.

Since the wafer surface is non-

planar, the quality and the

integrity of the metal lines

created in this step are very

critical and are essential for

circuit reliability.


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The composite layout and the

resulting cross-sectional view of

the chip, showing one nMOS

and one pMOS transistor (built-

in n-well), the polysilicon and

metal interconnections.

The final step is to deposit the

passivation layer(overglass -

for protection) over the chip,

except for wire-bonding pad

areas.


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Advanced Metallization


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From Design to Reality


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EE415 VLSI Design

DesignRules


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CMOS Process LayersLayer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (p+,n+) Green

L i 0 25


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EE415 VLSI Design

Layers in 0.25 mmCMOS process


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EE415 VLSI Design

Design Rules

Interface between the circuit designer and process

engineer

Guidelines for constructing process masks

Unit dimension: minimum line width scalable design rules: lambda parameter

absolute dimensions: micron rules

Rules constructed to ensure that design works even

when small fab errors (within some tolerance) occur

A complete set includes

set of layers

intra-layer: relations between objects in the same layer

inter-layer: relations between objects on different layers


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EE415 VLSI Design

3D Perspective

Polysilicon Aluminum


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EE415 VLSI Design

Why Have Design Rules?

To be able to tolerate some level offabrication

errors such as

1. Mask misalignment

2. Dust

3. Process parameters

(e.g., lateral diffusion)

4. Rough surfaces

Intra Layer Design Rule


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EE415 VLSI Design

Intra-Layer Design RuleOrigins

Minimum dimensions (e.g., widths) of objects on each

layer to maintain that object after fab

minimum line width is set by the resolution of the

patterning process (photolithography)

Minimum spaces between objects (that are not

related) on the same layer to ensure they will not

short after fab

0.3 micron

0.3 micron

0.15

0.15

Inter Layer Design Rule


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EE415 VLSI Design

Inter-Layer Design RuleOrigins

1. Transistor rules transistor formed by

overlap of active and poly layers

TransistorsCatastrophicerror

Unrelated Poly & DiffusionThinner diffusion,but still working

Inter-Layer Design Rule


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EE415 VLSI Design

Inter-Layer Design RuleOrigins, Cont

2. Contact and via rules

M1 contact to p-diffusion

M1 contact to poly

Mx contact to My

Contact Mask

Via Masks

0.3

0.14

both materialsmask misaligned

M1 contact to n-diffusion

Contact: 0.44 x 0.44


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EE415 VLSI Design

Intra-Layer Design Rules

Metal24

3

10

90

Well

Active3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal13

3

2

Contactor Via

Select

2

or

6

2

Hole


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EE415 VLSI Design

Transistor Layout

1

2

5

3

Trans

istor


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EE415 VLSI Design

Vias and Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2


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Select Layer

1

3 3

2

2

2

WellSubstrate

Select3

5


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IC Layout


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CMOS Inverter Sticks Diagram

1

3

InOut

VDD

GND

Stick diagram of inverter

Dimensionless layout entities

Only topology is important

Final layout generated by

compaction program


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EE415 VLSI Design

CMOS Inverter max Layout

VDD

GND

NMOS (2/.24 = 8/1)

PMOS (4/.24 = 16/1)

metal2

metal1polysilicon

InOut

metal1-poly via

metal2-metal1 via

metal1-diff via

pfet

nfet

pdif

ndif


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EE415 VLSI Design

Layout Editor


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EE415 VLSI Design

Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.


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EE415 VLSI Design

CMOS Inverters

Polysilicon

InOut

Metal1

VDD

GND

PMOS

NMOS

1.2mm=2l


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EE415 VLSI Design

Well-well spacing = 9

M1- M1 spacing = 3

M1width = 4

Active to well edge = 5

Min active width = 3

Poly overlap of active = 2

M2 - M2 spacing = 4

All distances in l

Layout Design Rule Violation


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EE415 VLSI Design

Building an Inverter

A

VCC

VSS

A

Output

Step 1 Step 2

A

OutputP

N

A

P diffusion

N diffusion

Step 3 Step 4

VCC

Output

VSS

With permission of William Bradbury


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EE415 VLSI Design

Building a 2 Input NOR Gate

A A BA B A BB

A

B

Out

P

Output

Shared node

A B

A

B

P

NN

Step 1 Step 3

O

utput

O

utput

Sh

ared

node

V

SS

V

CC

V

SS

Step 2

P

N

Step 4

VSS

Ou

tput

V

CC



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EE415 VLSI Design

Building a 2 Input NAND Gate


A A BA BB

Step 1 Step 3

O

utput

O

utput

Sh

ared

node

V

SS

V

CC

V

SS

Step 2

P

N

Step 4

A B

V

SS

O

u

t

pu

t

V

CC

Shared node

Output

P BA P

AN

BN

A

B

Out


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EE415 VLSI Design

Combining Logic Functions


A

Out

B

B

B

B

B

AP

Out

P

B

A

BN

N

AB

VCC

VSSB

B

VSS

VCC

Out

AB

Out

B

VSS

VCC

Cell Symbol to Logic to


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EE415 VLSI Design

Cell Symbol to Logic toTransistor Schematic to Layout


INPUT OUTPUT

LD LD

SRAM

OUTPUT

P 1.4

N 1.4

LD

LD

P 1.8N 2.0

P 2.0N 2.0

P .5/1.0

N .6/1.0

INPUT B

A

SRAM BIT LOGIC

Minimum poly width

L = 0.20

OUTPUT

SRAM BIT TRANSISTOR SCHEMATIC

INPUTP2, 1.8

N2, 2.0

P3, .5/1.0

P4, 2.0

N4, 2.0P1, 1.4

N1, 1.4

LD

LD

B

A

N3 , .6/1.0

Note the listing of the L dimension

which is not the minimum defined by

the process


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Schematic to Transistor


AINPUT

LD

P1

VCC

A

B

P2VCC

OUTPUTB

P4

VCC

A

B

P3

A

INPUT

LD

N1

VSS

A

B

N2

VSS

B

OUTPUT

N4

VSSA

B

N3

Assembling the Transistors by


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EE415 VLSI Design

Assembling the Transistors byType and Node Name

With permission of William BradburyWith permission of William Bradbury

VSS

A

LD

B

OUTPUT

VSS

A

B

VSS

B

INPUT

VCCAA

INPUT

LD

A

VC

C

B

B

VCC OUTPUT

B

C ti th N d


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EE415 VLSI Design

Connecting the Nodes


VSS

A

LD

B

OUTPUT

VSS

A

B

VSS

B

INPUT

VCCAA

INPUT

LD

A

VC

C

B

B

VCC OUTPUT

B

C ti th D t


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EE415 VLSI Design

Connecting the Dotes


INPUT

V

C

C

A

B

A

I

N

PU

T

LD

VC

CB

V

C

C

O

U

T

P

UT

B

V

S

SA

I

N

P

U

T

LD

VSS

B

O

UT

P

U

T

A

B

A

BA

UNMERGED DATA:

Notice the addition of contacts

where necessary and also the use of

redundant contacts to improve

reliability

VSS

Cleaning Connections and


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EE415 VLSI Design

gCompleting the layout


.

P-TAP

V

C

CB

A

V

C

C

B

O

U

T

P

U

T

VS

S

A

IN

PUT

VS

S

B

OUTP

UT

VS

S

BA

A

B

OUTPUTINPUT

LD

B

B

B

P-IMPLANT

N-TAPN-WELL

P1

P2

P

3

P4

N1 N3 N4

N-IMPLANT

N2

VC

C

IN

PU

T

A

LDDD

Added:1.Taps2.Implants

3.Cell boundry


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EE415 VLSI Design

Using sticks


.

N diffusion

Metal1

P diffusion

Contact

Poly

B AB

VSS

VCC

Output


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EE415 VLSI Design

Same cell, different shape


.

ABB

VSS

VCC VCC

Out

AB

VCC

B

OutB

VSS

B AB

VSS

VCC

Output


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EE415 VLSI Design

Cells Designed for Sharing


.

1 Bit

1 Bit

Memory Row 1

Compare Row 1

Reference VoltageSense

Ckt. for

One Row

Height of 1

Memory Bit

1 Bit

1 Bit

Memory Row 1

Compare Row 1Reference Voltage

Dual

Sense AmpCell Height

Compare Row 2

Memory Row 2Reference Voltage

Dual Sense Amps Dual Write Line Ckts

Courtesy Mentor Graphics Corp. Layout created using IC-Station.


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EE415 VLSI Design

Cells Designed for Sharing


.


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EE415 VLSI Design

Packaging


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EE415 VLSI Design

Packaging RequirementsDesired package properties

Electrical: Lowparasitics

Mechanical: Reliable and robust

Thermal: Efficient heat removal

Economical: Cheap

Wire bonding

Only periphery of chip available

for IO connections

Mechanical bonding of one pinat a time (sequential)

Cooling from back of chip

High inductance (~1nH)

http://www.embeddedlinks.com/chipdir/package.htm

More about packaging:


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B di T h i


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EE415 VLSI Design

Bonding Techniques

Lead Frame

Substrate

Die

Pad

Wire Bonding

Tape Automated Bonding (TAB)


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EE415 VLSI Design

Tape-Automated Bonding (TAB)

(a) Polymer Tape with imprinted

(b) Die attachment using solder bumps.

wiring pattern.

Substrate

Die

Solder BumpFilm + Pattern

Sprocket

hole

Polymer film

Lead

frame

Test

pads

N k t


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EE415 VLSI Design

New package types

BGA (Ball Grid Array)

Small solder balls to connect

to board

small

High pin count

Cheap

Low inductance

CSP (Chip scale Packaging)

Similar to BGA

Very small packages

Package inductance:

1 - 5 nH

Flip Chip Bonding


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EE415 VLSI Design

Flip-Chip Bonding

Solder bumps

Substrate

Die

Interconnect

layers

Package to Board Interconnect


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EE415 VLSI Design

Package-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount

P k T


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EE415 VLSI Design

Package Types

Through-hole vs. surface mount

From Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/

Chi P k B di
http://www.ece.utexas.edu/~adnanhttp://www.ece.utexas.edu/~adnan


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EE415 VLSI Design

Chip-to-Package Bonding

Traditionally, chip is surrounded bypad frame Metal pads on 100 200 mm pitch

Gold bond wires attach pads to package

Lead frame distributes signals in package

Metal heat spreaderhelps with cooling



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EE415 VLSI Design

Advanced Packages

Bond wires contribute parasitic inductance

Fancy packages have many signal, powerlayers

Like tiny printed circuit boards Flip-chip places connections across surface

of die rather than around periphery Top level metal pads covered with solder balls

Chip flips upside down Carefully aligned to package (done blind!)

Heated to melt balls

Also called C4(Controlled Collapse Chip Connection)



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EE415 VLSI Design

Package Parasitics

Chip

SignalPins

Package

Capacitor

SignalPads

Chip

VDD

ChipGND

Board

VDD

BoardGND

Bond Wire Lead Frame

Package

Use many VDD, GND in parallel Inductance, IDD



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EE415 VLSI Design

Signal Interface

Transfer of IC signals to PCB Package inductance.

PCB wire capacitance.

L - C resonator circuit generating oscillations.

Transmission line effects may generate reflections Cross-talk via mutual inductance

L

C

Package

ChipPCB trace

L-C Oscillation

Z

Transmission line reflections

R

f =1/(2p(LC)1/2)

L = 10 nH

C = 10 pF

f = ~500MHz

P k P t


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EE415 VLSI Design

Package Parameters

P k P t


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EE415 VLSI Design

Package Parameters

P k P t


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EE415 VLSI Design

Package Parameters2000 Summary of Intels Package I/O Lead Electrical Parasitics for Multilayer Packages

Packaging Faults


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EE415 VLSI Design

Packaging Faults

Small Ball Chip Scale Packages (CSP) Open

Packaging Faults


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EE415 VLSI Design

CSP Assembly on 6 mil Via in 12 mil pad

Void over via structure

Packaging Faults

Mi i i i f El i S


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EE415 VLSI Design

Miniaturisation of Electronic Systems

Enabling Technologies :

SOC

High Density Interconnection

technologies

SIPSystem-in-a-package

From ECE 407/507 University of Arizona

http://www.ece.arizona.edu/mailman/listinfo/ece407
http://www.ece.arizona.edu/mailman/listinfo/ece407http://www.ece.arizona.edu/mailman/listinfo/ece407


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EE415 VLSI Design

The Interconnection gap

Improvement in density of standard interconnectionand packaging technologies is much slower than theIC trends

IC scaling

Time

PCB scaling

Interconnect Gap

Advanced PCB

Laser via




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EE415 VLSI Design

The Interconnection gap

Requires new high density Interconnecttechnologies

IC scaling

Time

PCB scaling

Advanced PCB

Reduced Gap

Thin film lithography based

Interconnect technology




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Multi-Chip Modules


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EE415 VLSI Design

Multi Chip Modules

l l Ch d l ( C )


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EE415 VLSI Design

Multiple Chip Module (MCM)

Increase integration level of system (smaller size) Decrease loading of external signals > higher performance

No packaging of individual chips

Problems with known good die:

Single chip fault coverage: 95%

MCM yield with 10 chips: (0.95)10

= 60% Problems with cooling

Still expensive

C l PC i MCM


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Complete PC in MCM

chapter2 manufacturing process

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