COEN 6521 VLSI Testing

Zeljko ZilicMcGill University, Dept. ECE(on sabbatical leave in Ottawa)

zeljko@ece.mcgill.cawww.macs.ece.mcgill.ca/~zeljko

Overview

Class Overview Testing Role Economy of Testing Digital Circuit Testing Tutorial Fault Modeling Q&A

Class Outline Course with large project component Testing Methods and Practice

Manufacturing tests – Basic methods Automated test pattern generation (ATPG), techniques for

efficient test generation, simulation and evaluation

Built-in test (BIST) and Design for Testability (DFT) Pseudo-random and pseudo-exhaustive generation and

evaluation Design techniques incorporation

Fault tolerant and self-repaired computing

Testing and Related Problems

Major problem: Manufacturing verification Was manufacturing correct? Extreme economic importance (only if you

intend to make a good living by IC design) Relation to related problems:

“Testing” of a design – implementation verification Software testing – really the program verification

Manufacturing testing of software – CD ROM ErrorCorrecting Codes eliminate need for testing!

Testing Game: Pass vs. Fail

Separate good from faulty: two-sided error Fail correct IC: income loss (<$100/pc.) Pass incorrect IC: potential liability (>$100k)

Find optimal error detection level

0

10

20

30

40

50

60

70

80

90

100

85% 90% 95% 100%

Income

Liability Risk

Net Income

Testing in Design and Production

Design and test in product development cycle

Testing pushed early – Design For Testability(DFT)

Marketing and SalesSystems EngineerVLSI Design EngineerTest EngineerApplication Engineer

Project Start Project End

Involvement

Mechanics of Testing

Design verification/characterization Simulation, emulation, prototypes

Manufacturing tests: Standalone testers (probing pins or internals)

Advantest, HP/Agilent, Teradyne, LTX, … Burn-in test (tester + oven, higher voltage) Speed-binning (tester + speed characterization tests)

Test during product lifetime Self-test (chip or board), on-line (concurrent to

normal operation), boundary scan (board)

What Are We Testing?

waferdie

Why Faults Occur?

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)+=

area dieareaunit per defects1yield die

a is approximately 3 4area) (die cost die f=

impurities MechanicalMalfunctioning

How Testing Works

DIGITALCIRCUIT

COMPARATOR

--- 11--- 00--- ----- ----- 01

INPUT PATTERNS OUTPUT RESPONSES

TEST RESULT

10 ---00 ----- ----- ---01 ---

STOREDCORRECT

RESPONSE

Cost of Integrated Circuits

NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor

Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area

Unit Cost Breakdown

Yielddependent

Probe yield Packaged yield Testing cost

figures insignificantly

Running costs

Nonrecurring Engineering Cost

NRE: designcost

Weigthing inDFT – nontrivial

Includes time,resources

Seriouslyinfluences profits

NRE Cost is Increasing

Testing Cost Tester total cost (T.C.):

Purchase price of tester: A+B*pin_count Running cost: Depreciation+Operating

T.C.: From 1 to 6 $M

Testing cost: T.C./time Several cents/sec.

Cannot afford wasted time Inefficient tester use, test vectors Low yield

T. C.: increasing in proportion : ~ 30% currently

Conclusions

Introduction to VLSI TestingOverview of Testing Problems, ApproachesBasics of Economy of TestingProject Considerations