cortex-a9 mpcore evaluation board kzm-ca9-01 · cortex-a9 mpcore evaluation board kzm-ca9-01...

Cortex-A9 MPCore Evaluation Board

KZM-CA9-01 Operation Manual

Kyoto Microcomputer Co., Ltd.

KZDOC090918

Preface KZM-CA9-01, as an evaluation board for ARM Cortex-A9 MPCore multi-processor, has 4 pieces of Cortex-A9 CPU, snoop control unit, 512K byte of L2 cache and operates at 400MHz clock frequency. KZM-CA9-01 evaluation board can be utilized as a configurable platform, which enables the evaluation of Cortex-A9 MPCore for development of low-power and high-performance application of next generation.

Important Notice Thank you for purchasing our product. We are requesting the customer registration for the after-sales service/version up/new product notification, and for our reference of further development and sales activities. Returning the registration card, the customer will be registered to our customer list and the customer support and hardware assurance become available.

This document is protected by copyright law, and any kind of copy, reprinting, modification and etc., are

prohibited except with the prior written permission from Kyoto Microcomputer Co., Ltd.

The copyright, dealership and all rights of this product belong to Kyoto Microcomputer Co., Ltd.

The contents or specification of this product may be changed without notice.

Although this product is designed and produced with taking all possible attention, Kyoto Microcomputer Co.,

Ltd. shall not be liable for any consequence of using the product.

Generally, the program, system or device names appear in this document are the registered trademark of

each company.

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Contents 1. Overview ................................................................................................................................................... 3

1.1. Specifications Overview .................................................................................................................... 3 1.2. Memory Map ...................................................................................................................................... 8

2. Functional Block Diagram ....................................................................................................................... 9 2.1. PCB image (FYI) .............................................................................................................................. 10

3. Detailed Specifications ........................................................................................................................... 12 3.1. CPU ................................................................................................................................................... 12

3.1.1. Clock Input ................................................................................................................................ 12 3.1.2. Reset input ................................................................................................................................ 12 3.1.3. System Configuration ............................................................................................................... 12 3.1.4. Interrupt .................................................................................................................................... 12

3.2. DMC .................................................................................................................................................. 12 3.2.1. DDR2-SDRAM Specifications (FYI) ........................................................................................ 12

3.3. PCI Express ...................................................................................................................................... 13 3.3.1. PCI Express Switch (PEX8616) ............................................................................................... 13

3.3.1.1. Port0 Upstream .................................................................................................................. 13 3.3.1.2. Port1 Downstream ............................................................................................................. 14 3.3.1.3. Port5 Downstream ............................................................................................................. 14 3.3.1.4. Port6 Downstream ............................................................................................................. 14

3.3.2. PCI Express x4 connector ......................................................................................................... 15 3.3.2.1. PCIex4connector CN1: PCIE-064-02-F-D-TH .................................................................. 15

3.3.3. PCI Express x1 connector ......................................................................................................... 16 3.3.3.1. PCIex1connector CN2: PCIE-036-02-F-D-TH .................................................................. 16

3.3.4. PCI Express MiniCard connector ............................................................................................ 17 3.3.4.1. MiniCard connector CN3:MM60-52B1-B1, Latch:MM60-EZH039-B5 ........................... 17

3.4. SMC0 Bus ......................................................................................................................................... 18 3.4.1. SMC0 Memory Map .................................................................................................................. 18

3.4.1.1. CS0 Memory Map ............................................................................................................... 19 3.4.1.2. CS1 Memory Map ............................................................................................................... 19 3.4.1.3. CS2 Memory Map ............................................................................................................... 19 3.4.1.4. CS3 Memory Map ............................................................................................................... 19

3.4.2. Bus Timing ................................................................................................................................ 20 3.4.2.1. Write Bus Timing ............................................................................................................. 20 3.4.2.2. Read Bus Timing .............................................................................................................. 20

3.5. SMC1 Bus ......................................................................................................................................... 21 3.5.1. SMC1-BUS Connector CN25: QTH-060-03-L-D-A (not implemented) ............................... 21

3.6. NMC .................................................................................................................................................. 23 3.7. CLCD ................................................................................................................................................ 24

3.7.1. LCD Board Specification .......................................................................................................... 24 3.7.2. LCD-IF1 Connector CN5: 04-6240-040-021-846+ LCD board ............................................... 24 3.7.3. LCD-IF2 Connector CN7: 04-6240-024-026-846+ LCD board ............................................... 26 3.7.4. LCD Capturing Board Specifications ...................................................................................... 27 3.7.5. Capture Connector CN6: 54104-5096 (not implemented) LCD Capturing Board ............... 27

3.8. UART0 (COM1) ................................................................................................................................ 29 3.8.1. COM1 Connector CN13: MX2C-0912-132 ............................................................................... 29

3.9. Multiplexed AXI Master/Slave Interface ....................................................................................... 29 3.9.1.1. HDRX Connector CN9: QTH-090-05-F-D-A-K (not implemented) ................................. 30 3.9.1.2. HDRY Connector CN10: QTH-090-05-F-D-A-K (not implemented) ............................... 32 3.9.1.3. HDRZ Connector CN8: QTH-150-05-F-D-A-K (not implemented) ................................. 34

3.10. NOR Flash ROM ............................................................................................................................ 35 3.11. FPGA EPC1F400C8N .................................................................................................................... 36

3.11.1. Functions ................................................................................................................................. 36 3.11.2. CPU System Configuration Setup ......................................................................................... 37 3.11.3. System Configuration Sequence ............................................................................................ 37 3.11.4. CPU Reset Control .................................................................................................................. 38 3.11.5. Reset Sequence ........................................................................................................................ 38 3.11.6. CPU Port Configuration ......................................................................................................... 39 3.11.7. CPU Interrupt Connection ..................................................................................................... 39

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2 ---- Contents

3.11.8. SMC0 Bus Control .................................................................................................................. 41 3.11.9. Control Logic in FPGA ............................................................................................................ 42

3.11.9.1. FPGA Register Map .......................................................................................................... 42 3.11.9.2. FPGA Register Detail ....................................................................................................... 43 3.11.9.3. LCD Board Switch Status Capturing (LCD_KEY) ........................................................ 43 3.11.9.4. Capturing touch panel coordinates in LCD board (LCD_PAD)..................................... 44 3.11.9.5. I2C Communication between CODEC (CDOEC) ........................................................... 45 3.11.9.6. Playing Operation Control to CODEC (PLAY_C) .......................................................... 46 3.11.9.7. Playing data output to CODEC (PLAY_D) ..................................................................... 46 3.11.9.8. Write Timing of playing data FIFO to CODEC .............................................................. 47 3.11.9.9. Control Recording Operation from CODEC (REC_C).................................................... 48 3.11.9.10. Recording data input from CODEC (REC_D) .............................................................. 48 3.11.9.11. Read Timing of sampled data FIFO from CODEC....................................................... 49 3.11.9.12. Serial Communication between RTC (RTC) ................................................................. 50 3.11.9.13. PEX Serial Communication Parameter ........................................................................ 51 3.11.9.14. Timer Counter................................................................................................................. 51 3.11.9.15. USER DIPSW, HW DIPSW Status Capturing and USER LED Control (MISC_F) .. 52

3.11.10. FPGA Configuration ............................................................................................................. 53 3.12. UART2,3,4 Connector .................................................................................................................... 54

3.12.1. COM2,3,4 Connector CN14, CN15, CN16: HTST-105-01-L-DV .......................................... 54 3.13. USB HOST ..................................................................................................................................... 55

3.13.1. USB HOST-IF Connector CN11: 5787745-2 ....................................................................... 55 3.14. LAN ................................................................................................................................................. 56

3.14.1. LAN-IF Connector CN12: J0026D21BNL ............................................................................. 56 3.15. SD Card .......................................................................................................................................... 57

3.15.1. SD-CARD Connector CN17: DM1AA-SF-PEJ ...................................................................... 57 3.16. AUDIO CODEC ............................................................................................................................. 58

3.16.1. Connector CN4: JA33331-H21P-4F ....................................................................................... 58 3.17. RTC ................................................................................................................................................. 59 3.18. Switch ............................................................................................................................................. 59

3.18.1. POWER SW SW1: JB-15HFBP2............................................................................................ 59 3.18.2. RESET SW SW3: JB-15HFBP2 ............................................................................................. 59 3.18.3. USER DIPSW SW2: CHS-08TA1 ........................................................................................... 59 3.18.4. HW DIPSW SW4: CHS-04TA1 ............................................................................................... 59

3.19. Jumper Post ................................................................................................................................... 60 3.19.1. JP1 R Voice Channel XJ8B-0311 ........................................................................................... 60 3.19.2. JP2 L Voice Channel XJ8B-0311 ............................................................................................ 60 3.19.3. JP3 CPU Core Power Supply XJ8C-0611 .............................................................................. 61

3.20. Indicators ....................................................................................................................................... 62 3.21. Debugger Connector ...................................................................................................................... 63

3.21.1. JTAG-ICE Connector CN18: XG4C-2031 .............................................................................. 63 3.21.2. TRACE-A Connector CN23: 2-5767004-2 .............................................................................. 64 3.21.3. TRACE-B Connector CN24: 2-5767004-2 (not implemented).............................................. 65 3.21.4. DB_DBGACK, TC_EDBGRQ process.................................................................................... 65

3.22. Power On Reset .............................................................................................................................. 66 3.23. Panel Connector ............................................................................................................................. 66

3.23.1. Panel Connector CN20 : XJ8C-1011 .................................................................................... 66 3.24. Power Supply Connector ............................................................................................................... 67

3.24.1. Connector CN19: 44206-0007................................................................................................. 67 3.24.2. Connector CN21: HEC0470-01-630 ....................................................................................... 67

3.25. Cooling Fan Connector .................................................................................................................. 68 3.25.1. Connector CN26: 0039276023 (not implemented) ................................................................ 68

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1. Overview 1.1. Specifications Overview

No. Item Specification 1 CPU CPU Cortex-A9 MPCore Test Chip *1

CPU frequency 400MHz bus frequency 80MHz

２ NOR Flash ROM size 64MB use device S29GL256P90TFIR10×２

controller Cortex-A9 SMC0 + SN74AVC16T245 ３ NAND Flash

ROM size 256MB use device MT29F2G08AADWP:D

controller Cortex-A9 NMC + SN74AVC16T245 ４ DDR2 SDRAM size 512MB

use device EDE2116ABSE-6E-E(2Gb) clock frequency 250MHz

controller Cortex-A9 DMC

５ PCI Express Switch

use device PEX8616-BB50BCF

EEPROM AT25256AN-10SU-1.8

６ PCI Express x4 lane SLOT

connector(CN1) PCIE-064-02-F-D-TH

use device Cortex-A9 PCI Express + PCI Express SW

７ PCI Express x1 lane SLOT

connector(CN2) PCIE-036-02-F-D-TH


８ PCI Express Mini Card

connector(CN3) MM60-52B1-B1

latch MM60-EZH039-B5


９ LCD connector (CN5,CN7) (LCD board)

04-6240-040-021-846+ 04-6240-024-026-846+

connector(CN6) (capture)

54104-5096

controller Cortex-A9 CLCD + SN74AVC16T245 + FPGA

１０ Tile Site connector (CN8,9,10)

QTH-090-05-F-D-A-K (HDRX, HDRY) (not implemented) QTH-150-05-F-D-A-K (HDRZ) (not implemented)

controller Cortex-A9 MAXI, SAXI

１１ FPGA use device EP1C4F400C8N

controller Cortex-A9 SMC0

*1 For Cortex-A9 Technical Reference Manual and the detail specification of Test Chip, please contact to ARM office of your neighbor.

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4 ---- KZM-CA9-01 User's ManualOverview

No. Item Specifications １２ RS232 (COM1)

connector (CN13) MX2C-0912-132

comm. method asynchronous, full duplex

control TXD,DTR,RTS,RXD,DSR,CTS,DCD,RI

clock freq. 7.3728MHz

comm. speed 1200bps ～ 460800bps

controller Cortex-A9 UART0 + SN74AVC16T245+ MAX3243ECPWE4

１３ RS232 (COM2,3,4)

connector (CN14,CN15, CN16)

HTST-105-01-L-DV

comm. method asynchronous, full duplex

control TXD,DTR,RTS,RXD,DSR,CTS,DCD,RI

clock freq. 7.3728MHz

speed 1200bps ～ 460800bps

controller Cortex-A9 SMC0 + TL16C554APNG4(UART2) + MAX3243ECPWE4

１４ USB HOST connector (CN11)

5787745-2

indicator VBUS2, VBUS3: light on at power supplied

use device ISP1761BE

controller Cortex-A9 SMC0 + SN74AVC16T245 + FPGA

１５ LAN connector (CN12)

J0026D21BNL

indicator SPEED_100, LINK_ACK status display

use device LAN9118-MT

controller Cortex-A9 SMC0, FPGA

EEPROM M93C46WMN6P

１６ SD card connector (CN17)

DM1AA-SF-PEJ

use device TE4301PF

CLK_IN 50MHz (ext-clock input), with STOP control

１７ AUDIO CODEC connector (CN4)

JA33331-H21P-4F BLUE : LINE IN GREEN : PHONE OUT RED : MIC IN

use device CS42L51-CNZ

MCLK 12.288MHz

AUDIO DATA I2S, CS42L51-CNZ master

control I2C

controller FPGA

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Overview ---- 5

No. Item Specification １８ RTC use device RV5C348B-E2-F

battery (BTS1) CH74-2032LF(holder) CR2032 (button cell)

１９ SMC1 extension connector (CN25)

QTH-060-03-L-D-A

use device Cortex-A9 SMC1 ２０ Switch POWER SW

(SW1)

3.3V,5V,12V power supply ON/OFF control

RESET SW (SW3)

Reset switch

USER DIPSW (SW2)

status can be captured by software

HW DIPSW (SW4)

Hardware configuration switch (cannot be altered)

２１ Jumper Post JP1,JP2 PHONE OUT / LINE OUT selection

JP3 CORE_1.0V power supply configuration

２２ Indicator VBUS2(LED4), VBUS3(LED5)

USB bus power supply ON/OFF, indicated

SPEED_100 (GREEN)

LAN

LINK_ACK (YELLOW)

LAN

SB POWER (LED12)

5VSB power supply status indication

3.3V POWER (LED13)

3.3V power supply status indication

5V POWER (LED14)

5V power supply status indication

USER LED (LED6,7,8,9,10, 11,15,16)

Light on/off by software control

JTAGnSW (LED17)

JTAGnSW signal status, indicated

２３ Debugger connector (CN22,CN23,CN24)

XG4C-2031(JTAG-ICE) 2-5767004-2(TRACE PORT A) 2-5767004-2(TRACE PORT B) (not implemented)

use device Cortex-A9

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２４ Reset POWER SW *1 (SW1)

3.3V,5V,12V power supply ON/OFF control

RESET SW (SW3)

Reset switch

ICE_nRST (TP71)

Reset from ICE

nSRST Reset from JTAG-ICE or TRACE-A connector

２５ Panel connector (CN20)

XJ8C-1011

POWER LED 5V power supply status indication

POWER SW *2 Power ON/OFF switch

STANBY LED *3 5VSB power supply status indication

RESET SW Reset switch

２６ Power Supply *4 connector 44206-0007(CN19) HEC0470-01-630(CN21)

3.3V A min ×

5V A min 3.5A min

5VSB A min ×

12V A min ×

Specification ATX v2.2 DC+5V IN

２７ Cooling fan power supply

Connector (CN26)

0039276023(not implemented)

２８

Generated power supply (from 5V)

CORE_1.0V 12A max

Variable range (theoretically)

0.874V ～ 1.249V

use device EN5366QI-T two pieces in parallel

PEX_1.0V 6A max

use device EN5366QI-T

1.0V 3A max


1.5V 1A max


2.5V 1A max


1.8V 3A max


* 1 For detail of the use devices, please refer to individual document, such as data sheet. * 2 In case of DC+5V IN input, POWER SW is not available. * 3 In case of DC+5V IN input, STANBY LED is not available. * 4 In case of DC+5V IN input, external power supply from the board is not available, either

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Overview ---- 7

3.3V 6A max


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1.2. Memory Map

0xE000_0000 External AXI 0x8000_0000 Reserved 0x6000_0000 DMC (DDR2 SDRAM) 0x5000_0000 SMC1 extension connector (CN25) 0x4000_0000 SMC0 bus 0x2000_0000 PCI 0x1000_0000 peripherals 0x0000_0000 DMC

SMC0(SMC0 CS0) For detail about each region, please refer to this document and Cortex-A9 MPCore test chip specifications.

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Functional Block Diagram ---- 9

2. Functional Block Diagram

Nor Flash (64MByte)

SMC0

LAN (LAN9118)

USB (ISP1761)

FPGA (EP1C4F400C8N)

RTC (RV5C348B)

Audio codec (CS42L51)

MPU

LCDC

PCIe

AXI(M)

AXI(S)

TILE

PCIex4

LAN-IF

LCD-IF1

LCD-IF2 LCD board(touch panel, switch) ッチパネル、スイッチ)

LCD board (display)

DDR2 DDR2 SDRAM (512MByte)

NAND NAND Flash (256MByte)

Audio

UART2 (16C554A)

UART0 COM１

COM2

USB HOST-IF

SD (TE4301FP)

ＳＤ-CARD

4 Lane

Battery backup

SMC1

PCIex1 1 Lane

MiniCard 1 Lane

PCIe SW ( PEX8616)

4 Lane

MAX3243

MAX3243

I2S

I2C

3.3V-1.8V conversion IC (SN74AVC16T245)

Capture-IF LCD output capturing board

ATX POWER

DC+5V DC-DC

5VSB

12V

ATX_3.3V

5V

CORE_1.0V 1.0V 1.5V 1.8V PEX_1.0V 2.5V 3.3V

SMC1-BUS

COM3

COM4

connector

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10 ---- KZM-CA9-01 User's ManualFunctional Block Diagram

2.1. PCB image (FYI)

top side (side-A)

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Functional Block Diagram ---- 11

bottom side (side-B)

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12 ---- KZM-CA9-01 User's ManualDetailed Specifications

3. Detailed Specifications

3.1. CPU 3.1.1. Clock Input

Cortex-A9 port Frequency Notes TCREFCLK 50 MHz OSC(3.3V) output is supplied via 3.3V to 1.8V level

conversion. 3.1.2. Reset input

Cortex-A9 port Notes nPLLRESET refer to FPGA

section nTCPORESET nSYSRESET

3.1.3. System Configuration

Cortex-A9 port Notes CFGCLK refer to FPGA

section

nCFGRST CFGLOAD CFGWnR CFGDATA CFGDATAOUT

3.1.4. Interrupt

Cortex-A9 port Notes CPUIRQ[0..42] refer to FPGA

section

EVENT_I nFIRQ_I[0..3] nIRQ_I[0..3]

3.2. DMC Two pieces of DDR2-SDRAM are used to comprise 32bit data bus.

2Gb：EDE2116ABSE-6E-E

3.2.1. DDR2-SDRAM Specifications (FYI)

DDR2 memory clock up to 250MHz words x bits 128M x 16(2G) internal banks 8 speed bin DDR2-667 (CL-tRCD-tRP) (5-5-5)

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Detailed Specifications ---- 13

3.3. PCI Express Clock (CICREF) input 100MHz (differential input) Via CPU PCIe port and PCI Express Switch (PEX8616), connected to

PCI Express x4 SLOT PCI Express x1 SLOT PCI Express Mini Card

3.3.1. PCI Express Switch (PEX8616)

CPU PCIe Port and PEX8616 Port0, PEX8616 Port1 and PCI Express x1 connector, Port5 and MiniCard connector, Port6 and PCI Express x4 connector, are connected, respectively. For PEX8616 initialization, EEPROM is available. And Hot Plug function is not used.

Port 0 Port 1

Port 5

Port 6 EEPROM

PCIex1

MiniCard

PCIex4

PEX8616

4

4

1

1 CPU

PCI Express Connections

3.3.1.1. Port0 Upstream

4 lanes out of 8 lanes at CPU, are connected to PEX8616 Port0.

CPU port signal PEX8616 port

TOD0 TC_TOD0 PEX_PER0 RID0 TC_RID0 PEX_PET0 TOD1 TC_TOD1 PEX_PER1 RID1 TC_RID1 PEX_PET1 TOD2 TC_TOD2 PEX_PER2 RID2 TC_RID2 PEX_PET2 TOD3 TC_TOD3 PEX_PER3 RID3 TC_RID3 PEX_PET3 TOD4 - - RID4 - - TOD5 - - RID5 - - TOD6 - - RID6 - - TOD7 - - RID7 - -

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3.3.1.2. Port1 Downstream

1 lane out of 4 lanes of PEX8616 Port1, is connected to PCIex1 connector.

PEX8616 port signal PCIex1 PEX_PET4 TX4 PET0 PEX_PER4 RX4 PER0 PEX_PET5 NC - PEX_PER5 NC - PEX_PET6 NC - PEX_PER6 NC - PEX_PET7 NC - PEX_PER7 NC -


1 lane out of 4 lanes of PEX8616 Port5, is connected to MiniCard connector.

PEX8616 port signal MiniCard PEX_PET24 TX24 PET0 PEX_PER24 RX24 PER0 PEX_PET25 NC - PEX_PER25 NC - PEX_PET26 NC - PEX_PER26 NC - PEX_PET27 NC - PEX_PER27 NC -


All 4 lanes of PEX8616 Port6, are connected to PCIex4 connector.

PEX8616 port signal PCIex4 PEX_PET28 TX28 PET0 PEX_PER28 RX28 PER0 PEX_PET29 TX29 PET1 PEX_PER29 RX29 PER1 PEX_PET30 TX30 PET2 PEX_PER30 RX30 PER2 PEX_PET31 TX31 PET3 PEX_PER31 RX31 PER3

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3.3.2. PCI Express x4 connector 3.3.2.1. PCIex4connector CN1: PCIE-064-02-F-D-TH

Pin Side B Pin Side A Name Description Name Description

1 +12V 1 (PRSNT1#) PU 2 +12V 2 +12V 3 +12V 3 +12V 4 GND 4 GND 5 (SMCLK) 5 (TCK) 6 (SMDAT) 6 (TDI) 7 GND 7 (TDO) 8 +3.3V 8 (TMS) 9 (TRST) 9 +3.3V

10 3.3Vaux 10 +3.3V

11 (WAKE#） PD 11 PERST#

Mechanical key 12 (RSVD) 12 GND 13 GND 13 REFCLK+ 14 PETp0 14 REFCLK- 15 PETn0 15 GND 16 GND 16 PERp0 17 (PRSNT2#) PU 17 PERn0 18 GND 18 GND 19 PETp1 19 RSVD 20 PETn1 20 GND 21 GND 21 PERp1 22 GND 22 PERn1 23 PETp2 23 GND 24 PETn2 24 GND 25 GND 25 PERp2 26 GND 26 PERn2 27 PETp3 27 GND 28 PETn3 28 GND 39 GND 39 PERp3 30 (RSVD) 30 PERn3 31 (PRSNT2#) PU 31 GND 32 GND 32 (RSVD)

Signal inside of braces () is not used. PU: pull-up, PD: pull-down

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3.3.3. PCI Express x1 connector 3.3.3.1. PCIex1connector CN2: PCIE-036-02-F-D-TH

Pin Side B Pin Side A Name Description Name Description

1 +12V 1 (PRSNT1#) PU 2 +12V 2 +12V 3 +12V 3 +12V 4 GND 4 GND 5 (SMCLK) 5 (TCK) 6 (SMDAT) 6 (TDI) 7 GND 7 (TDO) 8 +3.3V 8 (TMS) 9 (TRST) 9 +3.3V

10 3.3Vaux 10 +3.3V

11 （WAKE#） PD 11 PERST#

Mechanical key 12 (RSVD) 12 GND 13 GND 13 REFCLK+ 14 PETp0 14 REFCLK- 15 PETn0 15 GND 16 GND 16 PERp0 17 (PRSNT2#) PU 17 PERn0 18 GND 18 GND


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3.3.4. PCI Express MiniCard connector

USB controller port1 is connected, also. 3.3.4.1. MiniCard connector CN3:MM60-52B1-B1, Latch:MM60-EZH039-B5

Pin Name Description Pin Name Description 52 +3.3V 51 (RSVD) 50 GND 49 (RSVD) 48 +1.5V 47 (RSVD) 46 (LED_WPAN#) 45 (RSVD) 44 (LED_WLAN#) 43 (RSVD) 42 (LED_WWAN#) 41 (RSVD) 40 GND 39 (RSVD) 38 USB_D+ 37 (RSVD) 36 USB_D- 35 GND 34 GND 33 PETp0 32 (SMB_DATA) 31 PETn0 30 (SMB_CLK) 29 GND 28 +1.5V 27 GND 26 GND 25 PERp0 24 (+3.3Vaux) 23 PERn0 22 PERST# 21 GND 20 W_DISABLE# PD->High*1 19 (UIM_C4) 18 GND 17 (UIM_C8)

Mechanical Key 16 (UIM_VPP) 15 GND 14 (UIM_RESET) 13 REFCLK+ 12 (UIM_CLK) 11 REFCLK- 10 (UIM_DATA) 9 GND 8 (UIM_PWR) 7 (CLKREQ#) PU 6 1.5V 5 (RSVD) 4 GND 3 (RSVD) 2 3.3V 1 (WAKE#) PU


* 1 Goes to Low level by pull-down during FPGA configuration, goes to High level after finishing the

configuration

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3.4. SMC0 Bus Via SN74AVC16T45, connected with NOR Flash ROM, UART, LANC, USBC, SDC and FPGA. At CPU and FPGA, some signals are directly connect.

1.8<->3.3V conversion

SMC0A

SMC0D

32

32

CPU

FROMA

FROMD

FPGA

control

SMC0 bus diagram

3.4.1. SMC0 Memory Map

Chip Select Base Address(Hex) device CS0 4000 0000 NOR Flash ROM CS1 5000 0000 not used CS2 4800 0000 UART2, SDC, FPGA CS3 4C00 0000 LAN, USB

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3.4.1.1. CS0 Memory Map

Offset(Hex) Device Data bus width (bit) 0000 0000 NOR Flash ROM 32

3.4.1.2. CS1 Memory Map Not used at the product.


All address space belong to 32bit space.

Offset(Hex) Device Data bus width (bit) 31-24 23-16 15-8 7-0

0000 0000 UART2 CSA ○ 0080 0000 UART2 CSB ○ 0100 0000 UART2 CSC ○ 0180 0000 UART2 CSD ○ 0200 0000 SD ○ ○ 0280 0000 FPGA ○ ○ ○ ○

Bit lane marked by ○ is valid.


Offset(Hex) Device Data bus width (bit) 31:24 23:16 15:8 7:0

0000 0000 LAN ○ ○ ○ ○ 0200 0000 USB ○ ○ ○ ○

Bit lane marked by ○ is valid.

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3.4.2. Bus Timing

3.4.2.1. Write Bus Timing

bus clock.

cs_n

we_n

add

data_out

3.4.2.2. Read Bus Timing

bus clock.

cs_n

oe_n

add

data_in

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3.5. SMC1 Bus

Not used at the product.

3.5.1. SMC1-BUS Connector CN25: QTH-060-03-L-D-A (not implemented)

Pin Side B Side A Name Description Name Description

1 1.8V Power 1.8V Power 2 1.8V Power 1.8V Power 3 1.8V Power 1.8V Power 4 1.8V Power 1.8V Power 5 SMC1_A1 Address SMC1_A0 Address 6 SMC1_A3 Address SMC1_A2 Address 7 SMC1_A5 Address SMC1_A4 Address 8 SMC1_A7 Address SMC1_A6 Address 9 SMC1_A9 Address SMC1_A8 Address

10 SMC1_A11 Address SMC1_A10 Address 11 SMC1_A13 Address SMC1_A12 Address 12 SMC1_A15 Address SMC1_A14 Address 13 GND Ground GND Ground 14 SMC1_A17 Address SMC1_A16 Address 15 SMC1_A19 Address SMC1_A18 Address 16 SMC1_A21 Address SMC1_A20 Address 17 SMC1_A23 Address SMC1_A22 Address 18 SMC1_A25 Address SMC1_A24 Address 19 SMC1_A27 Address SMC1_A26 Address 20 SMC1_A29 Address SMC1_A28 Address 21 SMC1_A31 Address SMC1_A30 Address 22 GND Ground GND Ground 23 SMC1_nADV Control SMC1_nBAA Control 24 SMC1_nCS1 Control SMC1_nCS0 Control 25 SMC1_nCS3 Control SMC1_nCS2 Control 26 SMC1_nWE Control SMC1_nOE Control 27 GND Ground SMC1_nCRE control 28 SMC1_CLK0 Clock GND Ground 29 GND Ground SMC1_CLK1 Clock 30 RSVD Reserved GND Ground SMC1_A is connected with SMC0_ADD.

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Pin Side B Side A

Name Description Name Description 31 GND Ground GND Ground 32 SMC1_CLK2 Clock GND Ground 33 GND Ground SMC1_CLK3 Clock 34 SMC1_FBCLK Control SMC1_WAIT Control 35 SMC1_INT Control GND Ground 36 GND Ground SMC1_D0 Data 37 SMC1_D0 Data SMC1_D2 Data 38 SMC1_D3 Data SMC1_D4 Data 39 SMC1_D5 Data SMC1_D6 Data 40 SMC1_D7 Data SMC1_D8 Data 41 SMC1_D9 Data SMC1_D10 Data 42 SMC1_D11 Data SMC1_D12 Data 43 SMC1_D13 Data SMC1_D14 Data 44 SMC1_D15 Data GND Ground 45 GND Ground SMC1_D16 Data 46 SMC1_D17 Data SMC1_D18 Data 47 SMC1_D19 Data SMC1_D20 Data 48 SMC1_D21 Data SMC1_D22 Data 49 SMC1_D23 Data SMC1_D24 Data 50 SMC1_D25 Data SMC1_D26 Data 51 SMC1_D27 Data SMC1_D28 Data 52 SMC1_D29 Data SMC1_D30 Data 53 SMC1_D31 Data GND Ground 54 GND Ground SMC1_nBLS0 Control 55 SMC1_nBLS1 Control SMC1_nBLS2 Control 56 SMC1_nBLS3 Control RSVD Reserved 57 3.3V Power 3.3V Power 58 3.3V Power 3.3V Power 59 3.3V Power 3.3V Power 60 3.3V Power 3.3V Power SMC1_D is connected with SMC0_D.

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3.6. NMC

Via SN74AVC16T45, 256MB NAND Flash ROM is connected. NMC_CS0 is used.

NAND FLASH CPU

1.8V <-> 3.3V conversion

NMC_CS0

NAND Flash block circuit composition

NMC Timing register configuration value (FYI)

NAND_t_rr 0x4 NAND_t_ar 0x2 NAND_t_clr 0x2 NAND_t_wp 0x2 NAND_t_rea 0x2 NAND_t_wc 0x4 NAND_t_rc 0x6

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3.7. CLCD

Clock Input (CLCDCLK) 23.8MHz Via SN74AVC16T245, connected with LCD-IF1 for LCD board, LCD-IF2 connector and Capture-IF connector for LCD out capturing board. For LCD-IF1 and LCD-IF2 connector, LCD board is available from Shimafuji Electric Incorporated., and display and touch panel on LCD board is utilized. And LCD output capturing board is able to be connected with Capture-IF connector.

LCD-IF1 CPU CLCD

1.8V <-> 3V conversion

LCD-IF2

Capture-IF

FPGA

CLCD circuit composition

3.7.1. LCD Board Specification

DCLK 23.8MHz Display pixels 800x480 pixels Display color 65536 colors (R=5bits, G=6bits, B=5bits) Touch panel controlled by logic in FPGA (LCD_PAD) Switch controlled by logic in FPGA (LCD_KEY)

3.7.2. LCD-IF1 Connector CN5: 04-6240-040-021-846+ LCD board

1 40

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PIN Name Description

1 3.3V Power 2 3.3V Power 3 3.3V Power 4 3.3V Power 5 NC Not Connected 6 GND Ground 7 GND Ground 8 NC Not Connected 9 NC Not Connected

10 NC Not Connected 11 VSYNC V sync 12 DEN Data Enable 13 NC Not Connected 14 DCLK Dot Clock 15 HSYNC H sync 16 GND Ground 17 GND Ground 18 R5 Data 19 R4 Data 20 R3 Data 21 R2 Data 22 R1 Data 23 G5 Data 24 G4 Data 25 G3 Data 26 GND Ground 27 GND Ground 28 G2 Data 29 G1 Data 30 G0 Data 31 B5 Data 32 B4 Data 33 B3 Data 34 B2 Data 35 B1 Data 36 NC Not Connected 37 NC Not Connected 38 NC Not Connected 39 NC Not Connected 40 NC Not Connected Connector pin numbers are different from pin assignment of connector itself.

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3.7.3. LCD-IF2 Connector CN7: 04-6240-024-026-846+ LCD board

PIN Name Description 1 3.3V Power 2 3.3V Power 3 GND Ground 4 GND Ground 5 nPOWER LCD I/F 6 /LCD FLON LCD I/F 7 /RESET LCD I/F 8 PAD DCLK PAD I/F 9 PAD DOUT PAD I/F

10 PAD DIN PAD I/F 11 /PAD IRQ PAD I/F 12 /PAD CS PAD I/F 13 GND Ground 14 GND Ground 15 KEY OUT2 KEY I/F 16 KEY OUT1 KEY I/F 17 KEY OUT0 KEY I/F 18 KEY IN4 KEY I/F 19 KEY IN3 KEY I/F 20 KEY IN2 KEY I/F 21 KEY IN1 KEY I/F 22 KEY IN0 KEY I/F 23 GND Ground 24 GND Ground Connector pin numbers are different from pin assignment of connector itself.

1 24

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3.7.4. LCD Capturing Board Specifications

DCLK 23.8MHz Display pixels 800x480 pixels Display color 16777216 colors (R=8bits, G=8bits, B=8bits)

3.7.5. Capture Connector CN6: 54104-5096 (not implemented) LCD Capturing Board

PIN Name Description 1 NC Not Connected 2 NC Not Connected 3 NC Not Connected 4 NC Not Connected 5 NC Not Connected 6 NC Not Connected 7 NC Not Connected 8 B0 Data 9 B1 Data

10 B2 Data 11 B3 Data 12 B4 Data 13 B5 Data 14 B6 Data 15 B7 Data 16 G0 Data 17 G1 Data 18 G2 Data 19 G3 Data 20 G4 Data 21 G5 Data 22 G6 Data 23 G7 Data 24 R0 Data 25 R1 Data

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PIN Name Description 26 R2 Data 27 R3 Data 28 R4 Data 29 R5 Data 30 R6 Data 31 R7 Data 32 HSYNC H sync 33 VSYNC V sync 34 DCLK Dot Clock 35 GND Ground 36 NC Not Connected 37 3.3V Power 38 3.3V Power 39 NC Not Connected 40 NC Not Connected 41 NC Not Connected 42 NC Not Connected 43 NC Not Connected 44 NC Not Connected 45 NC Not Connected 46 NC Not Connected 47 NC Not Connected 48 DEN Data Enable 49 GND Ground 50 GND Ground Connector pin numbers are different from pin assignment of connector itself.

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3.8. UART0 (COM1)

communication method asynchronous, full duplex control method TXD,DTR,RTS,RXD,DSR,CTS,DCD,RI clock input(UARTCLK) 7.3728MHz speed 1200bps ～ 460800bps controller Cortex-A9 UART0 + MAX3243ECAI+ 3.8.1. COM1 Connector CN13: MX2C-0912-132

PIN Name Description 1 DCD Data carrier detect 2 RxD Serial input 3 TxD Transmit outputs 4 DTR Data terminal ready 5 GND Ground 6 DSR Data set ready. 7 RTS Request to send 8 CTS Clear to send 9 RI Ring detect indicator

3.9. Multiplexed AXI Master/Slave Interface Cortex-A9 port Frequency Notes

EXTMAXICLK 50 MHz OSC(3.3V) output is supplied via 3.3V to 1.8V level conversion. EXTMAXICLK2 100 MHz EXTSAXICLK 50 MHz EXTSAXICLK2 100 MHz

CPU master port is connected to HRDY connector, and slave port to HRDX connector, respectively. Some of the Master/Slave port are connected to HDRZ connector. All of the Tile port are configured at 1.8V.

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3.9.1.1. HDRX Connector CN9: QTH-090-05-F-D-A-K (not implemented)

PIN Name PIN Name 2 MARADDR_SP_12 1 MARADDR_SP_13 4 MARADDR_SP_11 3 MARADDR_SP_14 6 MARADDR_SP_10 5 MARADDR_SP_15 8 MARADDR_SP_9 7 MARID_SP_0

10 MARADDR_SP_8 9 MARID_SP_1 12 MARADDR_SP_7 11 MARLEN_SP_0 14 MARADDR_SP_6 13 MARLEN_SP_1 16 MARADDR_SP_5 15 MARSIZE_SP 18 MARADDR_SP_4 17 20 MARADDR_SP_3 19 MARPROT_SP_0 22 MARADDR_SP_2 21 MARBURST_SP 24 MARADDR_SP_1 23 MARLOCK_SP 26 MARADDR_SP_0 25 MARCACHE_SP_0 28 MBREADY_SP 27 MARCACHE_SP_1 30 MBVALID_SP 29 MARVALID_SP 32 MBRESP_SP 31 MARREADY_SP 34 33 MRDATA_SP_0 36 MBID_SP_1 35 MRDATA_SP_1 38 MBID_SP_0 37 MRDATA_SP_2 40 MAWREADY_SP 39 MRDATA_SP_3 42 MAWVALID_SP 41 MRDATA_SP_4 44 MAWCACHE_SP_1 43 MRDATA_SP_5 46 MAWCACHE_SP_0 45 MRDATA_SP_6 48 MAWLOCK_SP 47 MRDATA_SP_7 50 MAWBURST_SP 49 MRDATA_SP_8 52 MAWPROT_SP_0 51 MRDATA_SP_9 54 SP_nRST 53 MRDATA_SP_10 56 55 MRDATA_SP_11 58 MAWSIZE_SP 57 MRDATA_SP_12 60 MAWLEN_SP_1 59 MRDATA_SP_13 62 MAWLEN_SP_0 61 MRDATA_SP_14 64 MAWID_SP_1 63 MRDATA_SP_15 66 MAWID_SP_0 65 MRDATA_SP_16 68 MAWADDR_SP_15 67 MRDATA_SP_17 70 MAWADDR_SP_14 69 MRDATA_SP_18 72 MAWADDR_SP_13 71 MRDATA_SP_19 74 MAWADDR_SP_12 73 MRDATA_SP_20 76 MAWADDR_SP_11 75 MRDATA_SP_21 78 MAWADDR_SP_10 77 MRDATA_SP_22 80 MAWADDR_SP_9 79 MRDATA_SP_23 82 MAWADDR_SP_8 81 MRDATA_SP_24 84 MAWADDR_SP_7 83 MRDATA_SP_25 86 MAWADDR_SP_6 85 MRDATA_SP_26 88 MAWADDR_SP_5 87 MRDATA_SP_27 90 MAWADDR_SP_4 89 MRDATA_SP_28 92 MAWADDR_SP_3 91 MRDATA_SP_29

1

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94 MAWADDR_SP_2 93 MRDATA_SP_30 96 MAWADDR_SP_1 95 MRDATA_SP_31 98 MAWADDR_SP_0 97 MRID_SP_0 100 MWREADY_SP 99 MRID_SP_1 102 MWVALID_SP 101 MRRESP_SP 104 MWLAST_SP 103 MRLAST_SP 106 MWSTRB_SP_3 105 MRVALID_SP 108 MWSTRB_SP_2 107 MRREADY_SP 110 MWSTRB_SP_1 109 112 MWSTRB_SP_0 111 114 MWID_SP_1 113 116 MWID_SP_0 115 118 MWDATA_SP_31 117 120 MWDATA_SP_30 119 122 MWDATA_SP_29 121 124 MWDATA_SP_28 123 126 MWDATA_SP_27 125 128 MWDATA_SP_26 127 130 MWDATA_SP_25 129 132 MWDATA_SP_24 131 134 MWDATA_SP_23 133 136 MWDATA_SP_22 135 138 MWDATA_SP_21 137 140 MWDATA_SP_20 139 142 MWDATA_SP_19 141 144 MWDATA_SP_18 143 146 MWDATA_SP_17 145 148 MWDATA_SP_16 147 150 MWDATA_SP_15 149 152 MWDATA_SP_14 151 154 MWDATA_SP_13 153 156 MWDATA_SP_12 155 158 MWDATA_SP_11 157 160 MWDATA_SP_10 159 162 MWDATA_SP_9 161 164 MWDATA_SP_8 163 166 MWDATA_SP_7 165 168 MWDATA_SP_6 167 170 MWDATA_SP_5 169 172 MWDATA_SP_4 171 174 MWDATA_SP_3 173 176 MWDATA_SP_2 175 178 MWDATA_SP_1 177 180 MWDATA_SP_0 179

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3.9.1.2. HDRY Connector CN10: QTH-090-05-F-D-A-K (not implemented)

PIN name PIN name 2 MARADDR_MP_13 1 MARADDR_MP_12 4 MARADDR_MP_14 3 MARADDR_MP_11 6 MARADDR_MP_15 5 MARADDR_MP_10 8 MARID_MP_0 7 MARADDR_MP_9

10 MARID_MP_1 9 MARADDR_MP_8 12 MARLEN_MP_0 11 MARADDR_MP_7 14 MARLEN_MP_1 13 MARADDR_MP_6 16 MARSIZE_MP 15 MARADDR_MP_5 18 17 MARADDR_MP_4 20 MARPROT_MP_0 19 MARADDR_MP_3 22 MARBURST_MP 21 MARADDR_MP_2 24 MARLOCK_MP 23 MARADDR_MP_1 26 MARCACHE_MP_0 25 MARADDR_MP_0 28 MARCACHE_MP_1 27 MBREADY_MP 30 MARVALID_MP 29 MBVALID_MP(*1) 32 MARREADY_MP 31 MBRESP_MP 34 MRDATA_MP_0 33 36 MRDATA_MP_1 35 MBID_MP_1 38 MRDATA_MP_2 37 MBID_MP_0 40 MRDATA_MP_3 39 MAWREADY_MP 42 MRDATA_MP_4 41 MAWVALID_MP 44 MRDATA_MP_5 43 MAWCACHE_MP_1 46 MRDATA_MP_6 45 MAWCACHE_MP_0 48 MRDATA_MP_7 47 MAWLOCK_MP 50 MRDATA_MP_8 49 MAWBURST_MP 52 MRDATA_MP_9 51 MAWPROT_MP_0 54 MRDATA_MP_10 53 MP_nRST 56 MRDATA_MP_11 55 58 MRDATA_MP_12 57 MAWSIZE_MP 60 MRDATA_MP_13 59 MAWLEN_MP_1 62 MRDATA_MP_14 61 MAWLEN_MP_0 64 MRDATA_MP_15 63 MAWID_MP_1 66 MRDATA_MP_16 65 MAWID_MP_0 68 MRDATA_MP_17 67 MAWADDR_MP_15 70 MRDATA_MP_18 69 MAWADDR_MP_14 72 MRDATA_MP_19 71 MAWADDR_MP_13 74 MRDATA_MP_20 73 MAWADDR_MP_12 76 MRDATA_MP_21 75 MAWADDR_MP_11 78 MRDATA_MP_22 77 MAWADDR_MP_10 80 MRDATA_MP_23 79 MAWADDR_MP_9 82 MRDATA_MP_24 81 MAWADDR_MP_8 84 MRDATA_MP_25 83 MAWADDR_MP_7 86 MRDATA_MP_26 85 MAWADDR_MP_6 88 MRDATA_MP_27 87 MAWADDR_MP_5 90 MRDATA_MP_28 89 MAWADDR_MP_4 92 MRDATA_MP_29 91 MAWADDR_MP_3

180

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94 MRDATA_MP_30 93 MAWADDR_MP_2 96 MRDATA_MP_31 95 MAWADDR_MP_1 98 MRID_MP_0 97 MAWADDR_MP_0 100 MRID_MP_1 99 MWREADY_MP 102 MRRESP_MP 101 MWVALID_MP 104 MRLAST_MP 103 MWLAST_MP 106 MRVALID_MP(*1) 105 MWSTRB_MP_3 108 MRREADY_MP 107 MWSTRB_MP_2 110 109 MWSTRB_MP_1 112 111 MWSTRB_MP_0 114 113 MWID_MP_1 116 115 MWID_MP_0 118 117 MWDATA_MP_31 120 119 MWDATA_MP_30 122 121 MWDATA_MP_29 124 123 MWDATA_MP_28 126 125 MWDATA_MP_27 128 127 MWDATA_MP_26 130 129 MWDATA_MP_25 132 131 MWDATA_MP_24 134 133 MWDATA_MP_23 136 135 MWDATA_MP_22 138 137 MWDATA_MP_21 140 139 MWDATA_MP_20 142 141 MWDATA_MP_19 144 143 MWDATA_MP_18 146 145 MWDATA_MP_17 148 147 MWDATA_MP_16 150 149 MWDATA_MP_15 152 151 MWDATA_MP_14 154 153 MWDATA_MP_13 156 155 MWDATA_MP_12 158 157 MWDATA_MP_11 160 159 MWDATA_MP_10 162 161 MWDATA_MP_9 164 163 MWDATA_MP_8 166 165 MWDATA_MP_7 168 167 MWDATA_MP_6 170 169 MWDATA_MP_5 172 171 MWDATA_MP_4 174 173 MWDATA_MP_3 176 175 MWDATA_MP_2 178 177 MWDATA_MP_1 180 179 MWDATA_MP_0

(*1) pull-downed via 1KΩ at PCB

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3.9.1.3. HDRZ Connector CN8: QTH-150-05-F-D-A-K (not implemented)

PIN name PIN name 46 BOARDDET1 45 48 BOARDDET0 47 112 LTINT 111 140 AXICLK1 139 142 AXICLK2 141 154 nSYSPOR 153 156 nSYSRST 155 nTILE_DET 258 MARPROT_MP_1 257 260 MARID_MP_2 259 262 MARID_MP_3 261 264 MARID_MP_4 263 266 MARID_MP_5 265 268 MAWID_MP_2 267 270 MAWID_MP_3 269 272 MAWID_MP_4 271 274 MAWID_MP_5 273 276 MAWPROT_MP_1 275 278 MBID_MP_2 277 280 MBID_MP_3 279 282 MBID_MP_4 281 284 MBID_MP_5 283 286 MRID_MP_2 285 288 MRID_MP_3 287 290 MRID_MP_4 289 292 MRID_MP_5 291 294 MWID_MP_2 293 296 MWID_MP_3 295 298 MWID_MP_4 297 MAWPROT_SP_1 300 MWID_MP_5 299 MARPROT_SP_1 The table is only concerned about used ports.

300

299

2

1

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3.10. NOR Flash ROM Via SN74AVC16T45, two pieces of 64MB NOR Flash ROM are connected to compose 32 bits data width. BYTE# port, WP#/ACC port are cramped to High level. RY/BY# port is not used. Though 8, 16 and 32 bit data width are available for read access, write access is fixed to 32 bits data width.

NOR Flash FROMA

NOR Flash

FROMD

BYTE# 3.3V

RY/BY#

WP#/ACC 3.3V

3.3V

3.3V WP#/ACC

RY/BY#

BYTE#

24

32

NOR Flash circuit composition

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3.11. FPGA EPC1F400C8N 3.11.1. Functions

CPU system configuration setup CPU reset control CPU port setup CPU interrupt connections (CPUIRQ[0:42], EVENT_i, nFIQ[0:3], nIRQ[0:3]) Necessary signals generation from SMC0 bus address and control signals FPGA embedded logics FPGA configuration

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3.11.2. CPU System Configuration Setup

Executed before Cortex-A9 reset control after reset release. Configuration data coded in FPGA is written into CFGRW0, CFGW1, CFGRW2.

CFGCLK

CFGLOAD

CFGWnR

CFGDATA

nBOARDPOR

nCFGRESET

② ③ ② ③

CFG_DONE

① ④

⑤

② ③

④ ④

System Configuration

3.11.3. System Configuration Sequence

nCFGRESET set to Low during nBOARDPOR=Low Basic operation frequency: 25MHz/13 (frequency of CFGCLKx2) CFGCLK = 25MHz/13/2 = 961.5KHz (< max 1MHz) BaseAddress0 = 0x000 (12bit) CFGRW0 = setup data (32bit) BaseAddress1 = 0x004 (12bit) CFGRW1 = setup data (32bit) BaseAddress2 = 0x008 (12bit) CFGRW2 = setup (32bit)

nCFGRESET <= High nCFGWnR <= High, BaseAddress0 generated CFGRW0 generated CFGLOAD generated BaseAddress1 generated CFGRW1 generated CFGLOAD generated BaseAddress2 generated CFGRW2 generated CFGLOAD generated With CFG_DONE <= High, system configuration sequence finished.

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3.11.4. CPU Reset Control

By Reset input assertion, reset to CPU and whole board is executed after CPU System Configuration setup.

TCREFCLK

nPLLRESET

nTCPORESET

nSYSRESET

nBOARDPOR

B A 9 8 7 6 5 4 3 2 1 0

CFG_DONE

16384TCREFCLK

configuration

CPU Reset Control 3.11.5. Reset Sequence

At Reset port = Low, nPLLRESET, nTCPORESET, nSYSRESET, DB_nSRST <= Low

ST_POR After configuration finished, nPLLRESET <= High ST_STEP1 After TCREFCLK counted 16384x8 times, nTCRESET <= High ST_STEP2 After TCREFCLK counted 16384x4 times, nSYSRESET, DB_nSRST <= High (The reset of other devices are also released at this timing) ST_IDLE Holds reset release state

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3.11.6. CPU Port Configuration

Following ports need to be set to fixed input level.

Cortex-A9 port input level TESTMODE Low nBsTapEn High CRGBYPASS Low TMC1 Low TMC2 Low

3.11.7. CPU Interrupt Connection

Following table defines CPU Interrupt (CPUIRQ[42:0],EVENT_i,nFIQ[3:0],nIRQ[3:0]) connections:

Cortex-A9 port

Connected Signals Specifications

CPUIRQ42 PMUIRQ3 CPUIRQ41 PMUIRQ2 CPUIRQ40 PMUIRQ1 CPUIRQ39 PMUIRQ0 CPUIRQ38 nLTINT Becomes High, when the board exists at Tile Site.

Assuming the board is supporting this facility. CPUIRQ37 LCD_PAD_IRQ Inverse of interrupt signal LCD_PAD_nIRQ from LCD board

touch panel control IC. For detail, please refer to the specification of touch panel control IC on the LCD board.

CPUIRQ36 USB_DC_nIRQ Not Used Inverse of interrupt signal USB_DC_IRQ from USB controller LSI.

CPUIRQ35 USB_HC_nIRQ Inverse of interrupt signal USB_HC_IRQ from USB controller LSI. For detail, please refer to the specification of the USB controller LSI.

CPUIRQ34 LAN_nIRQ Inverse of interrupt signal LAN_IRQ from LAN controller LSI. For detail, please refer to the specification of the LAN controller LSI.

CPUIRQ33 LAN_nPME Inverse of interrupt signal LAN_nPME from LAN controller LSI. For detail, please refer to the specification of the LAN controller LSI.

CPUIRQ32 UART2_INTA Becomes High, at interrupt is asserted. For detail, please refer to specification of the UART2 controller. (UART2_INTD is not used.)

CPUIRQ31 UART2_INTB CPUIRQ30 UART2_INTC CPUIRQ29 UART2_INTD CPUIRQ28 UART2_TXRDY Inverse of interrupt signal UART2_nTXRDY from UART2

controller. For detail, please refer to specification of the UART controller. CPUIRQ27 UART2_RXRDY

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CPUIRQ26 SD_INT Inverse of interrupt signal SD_nINT from SD controller.

For detail, please refer to specification of the SD controller. CPUIRQ25 RTC_INTR Inverse of interrupt signal RTC_nINTR from RTC.

For detail, please refer to specification of the RTC. CPUIRQ24 LCD_PAD_DONE Becomes High, when serial communication between touch

panel control IC has finished. CPUIRQ23 I2C_DONE Becomes High, when control serial communication operation

with CODEC has finished. CPUIRQ22 I2S_DI_EMPTY Becomes High, when LR playing data FIFO to CODEC has

become empty. CPUIRQ21 I2S_DO_nEMPTY Becomes High, when LR recording data FIFO from CODEC

has data. CPUIRQ20 I2S_DI_INT Edge level interrupt is recommended.

However, there is some possibility that next rising edge fails to be detected , when the interrupt process takes more than one cycle of LRCK period. Becomes High at the write timing of LR playing data, and becomes Low after half cycle of LRCLK period. This is the timing to write one set of LR playing data to CODEC.

CPUIRQ19 I2S_DO_INT Edge level interrupt is recommended. However, there is some possibility that next rising edge fails to be detected , when the interrupt process takes more than one cycle of LRCK period. Becomes High when LR recording data is ready, and becomes Low after half cycle of LRCLK period. This is the timing to read one set of LR recording data from CODEC.

CPUIRQ18 RTC_DONE Becomes High, when communication to RTC has finished. CPUIRQ17 RTC_nBUSY Becomes Low during 62usec of period after RTC_DONE

becomes High. High level indicates that the communication is available to communicate successively with RTC.

CPUIRQ16 PEX_INTA Inverse of interrupt signal PEX_nINTA from PEX8616. For detail, please refer to specification of PEX8616.

CPUIRQ15 PEX_DONE Becomes High, when I2C communication between PEX8616 has finished.

CPUIRQ[14] I2S_UDF Edge level interrupt is recommended. This signal automatically changes depend on data number in FIFO. Becomes Hight, when playing data has been empty (FIFO becomes empty) during playing operation.

CPUIRQ[13] I2S_DI_nFULL Becomes High, when data number at playing FIFO to CODEC has become less than 256 sets. This signal automatically changes depend on data number in FIFO.

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CPUIRQ[12] I2S_DO_FULL Becomes High, when data number at recording FIFO from CODEC has become more than or equal to 256 sets. This signal automatically changes depend on data number in FIFO.

CPUIRQ[11:0] － Fixed to Low EVENT_i － Fixed to High nFIQ[0:3] － Fixed to High nIRQ[0:3] － Fixed to High

3.11.8. SMC0 Bus Control

This block generates necessary signals from SMC0 bus address and control signals, and reset output.

output signals, such as CS, WE and RE, to controller and ICs. output reset to controllers and ICs.

NOR control

CODEC communication

LAN control

USB control

UART2 IC control

SD control

RTC IC control

MiniCard connector

MPU port configuration

SMC0_A

ICE control

Tile Site control

FROMD

MPU reset

MPU SYS-CONF(*)

MPU IRQ

SCM0 control

SMC0 bus control

FPGA

* MPU SYS-CONF: System Configuration

FPGA bus control composition

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3.11.9. Control Logic in FPGA

Following functions are available at control logic implemented in FPGA. LCD board switch status capturing (LCD_KEY) LCD board touch panel coordinates capturing (LCD_PAD) I2C interface communication between CODEC (CODEC) Control playing operation to CODEC (PLAY_C) Playing data output to CODEC (PLAY_L) Control recording operation from CODEC (REC_C) Recoding data input from CODEC (REC_D) Serial communication between RTC (RTC) Serial communication between PEX8616 (PEX_C) USER DIPSW and HW DIPSW status capturing and USER LED light control (MISC_F)

3.11.9.1. FPGA Register Map

Offset(Hex) Register Name

Data Bus Width (bit)

Function

0280 0000 LCD_KEY 32 LCD board switch status capturing 0280 0004 LCD_PAD 32 LCD board touch panel coordinates capturing 0280 0008 CODEC 32 I2C interface communication between CODEC 0280 000C PLAY_C 32 Control playing operation to CODEC 0280 0010 PLAY_D 32 playing data output to CODEC 0280 0014 REC_C 32 Control recording operation from CODEC 0280 0018 REC_D 32 Recording data input from CODEC 0280 001C MISC_7 32 Reserved 0280 0020 MISC_8 32 Reserved 0280 0024 RTC 32 Serial communication between RTC 0280 0028 PEX_I2S 32 Serial communication parameter between PEX

(Reserved) 0280 002C MISC_B 32 Reserved 0280 0030 MISC_C 32 Reserved 0280 0034 MISC_D 32 Reserved 0280 0038 MISC_E 32 Reserved 0280 003C MISC_F 32 USER DIPSW and HW DIPSW status capturing USER

LED light control

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3.11.9.2. FPGA Register Detail

RW, RO and WO in table stands for read-write, read-only and write-only, respectively.

3.11.9.3. LCD Board Switch Status Capturing (LCD_KEY)

bit NAME R/W Function

31:9 X － Indefinite 8 LCD_FLON RW LCD board back-light control

0: OFF 1: ON

7 LCD_KEY_START RW Control scanning matrix switch at LCD board in a certain period. 0: stop scanning 1: start scanning, keeps on updating LCD_KEY_RET in a certain period.

6:0 LCD_KEY_RET RO Reflects scan value of LCD board matrix switch. bit 6 = left side switch (SW6) bit 5 = right side switch (SW4) bit 4 = center switch (SW5-CT) bit 3 = lower right (SW5-D) bit 2 = lower left (SW5-C) bit 1 = upper right (SW5-B) bit 0 = upper left (SW5-A) 0: not push down 1: push down

SW4, 5 and 6 at LCD_KEY_RET stands for switches at LCD board from Shimafuji Electric Incorporated. Function:Scanning matrix switch in LCD board periodically, and reflects the result to

LCD_KEY_RET value. Initialization: Set 1 to LCD_KEY_START Operation: Software can sense the matrix switch status by checking the LCD_KEY_RET value.

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3.11.9.4. Capturing touch panel coordinates in LCD board (LCD_PAD)

bit Name R/W Function 31 LCD_PAD_nIRQ RO Interrupt signal value from touch panel control IC.

Becomes Low, when touch panel has been touched. 31:25 X － Indefinite

24 LCD_PAD_START RW Starts communication between touch panel control IC at LCD board. 0: Stopped 1: Start communication or during communication

23 LCD_PAD_DONE RO Indicates communication termination between touch panel control IC at LCD board. Cleared by writing 0 at during terminating state. 0: Stopped 1: Terminated

22:20 LCD_PAD_A RW Sets coordinates code to be captured. 001: Y coordinate 101: X coordinate

19 LCD_PAD_MODE RW Please set value 1 (8bit) 18 LCD_PAD_SER RW Please set value 0 (DFR)

17:16 LCD_PAD_PD RW Please set value 00 (nPENIRQ Enable) 15:12 X － Indefinite 11:0 LCD_PAD_SDATA RO Captured X-coordinate or Y-coordinate value

Function: Capturing touch panel pen coordinates at LCD board Initialization: None Operation: Pen coordinates X and Y values are captured and processed by nPENIR interrupt.

Setting LCD_PAD_A, LCD_PAD_MODE, LCD_PAD_SER and LCD_PAD_PD value and writing 1 to LCD_PAD_START, then LCD_PAD_DONE becomes 1 capturing coordinate data specified coordinate code. Sets 0 to LCD_PAD_START after LCD_PAD_SDAT is read. The software organize pen coordinates by capturing X and Y coordinate. By capturing of X and Y coordinate plural times, correct pen coordinates can be determined.

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3.11.9.5. I2C Communication between CODEC (CDOEC)

bit Name R/W Function

31:24 X － Indefinite 23 EXEC RW Starts serial communication between CODEC

0: Stopped 1: Start communication or during communication

22 BUSY RO Indicates serial communication status between CODEC 1: During communication

21 DONE RO Indicates termination of communication between CODEC. 0: During communication or Stopped 1: Communication terminated. Cleared by writing 0 to EXEC.

20 ERR RO Indicates ACK and NACK at transmission in I2C communication.

19 X － Indefinite 18:16 MODE RW Communication mode 15:8 I2C_WD RW Write data 7:0 I2C_RD RO Read data

Function: I2C Communication between CODEC Initialization: Sets CODEC_nRESET bit at MISC_F register (CODEC reset release)

Within 10ms after reset release, set to software mode by setting 1 to PDN bit at Power Control 1 Register (0x02) in CODEC. (1) Chip Address + Write Operation

Starts communication by setting MODE=”000”, WD=”10010100" and EXEC=1 After DONE=1, stop communication (EXEC=0) confirming ERR=0.

(2) MAP byte write Sets MODE="010", WD="00000010"(0x02) and EXEC=1. After DONE=1, stop communication (EXEC=0) confirming ERR=0.

(3) Register Write MODE="011"、WD="00000001"(PDN=1)、EXEC=1 After DONE=1, stop communication (EXEC=0) confirming ERR=0.

(4) Please set required steps here after.

chip address : 1001010 Communication mode

MODE Function 000 Starts communication in succession, writing data (I2C_WD) continuously. 001 Starts communication by writing data (I2C_WD), then terminates. 010 Writes data, then communication continues. 011 Writes data, then communication terminates. 100 Reads data, then communication continues. 101 Reads data, then communication terminates. 110 Not used. 111 Reads data, then communication terminates with NACK response.

(To be used for some cases, such as forcibly terminating continuous reading.)

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3.11.9.6. Playing Operation Control to CODEC (PLAY_C)

bit Name R/W Function 31 I2S_DI_INT RO Becomes High at the timing of writing one set of playing

data LR, then returns to Low after half cycle period of LRCLK.

30 I2S_UDF RO Becomes High, when playing data has become empty during playing operation.

29:4 X － Indefinite 3 I2S_PLAY RW Start playing data transmission.

0: Stop 1: Start playing

2 I2S_PLAY_RUN RO Indicates playing operation. 0: Stop 1: During playing operation

1 I2S_DI_EMPTY RO Indicates data existing in playing data FIFO 0: data exists 1: no data

0 I2S_DI_FULL RO Indicates more than or equal to 256 sets of data existing in playing data FIFO. 0: less than 256 sets 1: more than or equal to 256 sets

3.11.9.7. Playing data output to CODEC (PLAY_D)

bit Name R/W Function 31:24 X － Indefinite 23:0 I2S_DI WO L/R playing data

Function: Outputs playing data to CODEC. Initialization: Setup for playing to CODEC Operation: The procedure to write LR playing data to FIFO by interrupt at rising edge of

I2S_DI_EMPTY, is shown. Set 1 to I2S_PLAY field in PLAY_C register, after setting CODEC to playing operation state and enable interrupt at rising edge of I2S_DI_EMPTY. At the interrupt of I2S_DI_EMPTY bit becoming 0 to 1 (rising edge), write playing data to PLAY_D register, in the order of L channel playing data and R channel playing data. Here after, write the playing data in LR order at each I2S_DI_EMPTY rising edge. To terminate playing, disable interrupt and set I2S_PLAY to 0. When I2S_PLAY_RUN becomes 0, playing terminates. (When I2S_PLAY_RUN becomes 0, remaining data in FIFO will be cleared, also.) Then stop the CODEC playing operation.

Notes: When starting and during playing, it is necessary to write the first L channel playing data to FIFO within half cycle period of sampling clock (LRCK) after I2S_DI_EMPTY becomes 1. And each write cycle of R, L and R, there after, also necessary to be written within half cycle period of LRCK.

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3.11.9.8. Write Timing of playing data FIFO to CODEC

LRCK

EMPTY

FIFO_RE

SDIN

WE ①

⑦

③

PLAY_RUN

⑥ ④

⑤

③ ⑧

②

④

DI_INT

⑨ DI_UDF

＜The case by storing LR playing data in FIFO＞

Set 1 to I2S_PLAY, after enabling I2S_DI_FULL (falling or Low level interrupt). (1) I2S_DI_FULL becomes Low. (2) Write 256 sets of LR playing data to FIFO. I2S_DI_FULL changes from Low to High. (3) I2S_DI_FULL changes from Hight to Low, when FIFO has become vacant for 256 sets of LR playing data. (4) Repeat from (2) when I2S_DI_FULL has become to Low. ＜The case by writing each LR playing data set, using I2S_DI_EMPTY as interrupt> ・From start playing to during playing

(Write 1 set of LR playing data at interrupt process of I2S_DI_EMPTY rising edge.) Write 1 to I2S_PLAY after enabling interrupt.

I2S_DI_EMPTY changes from 0 to 1 (rising edge). Write 1 set of LR playing data to FIFO. I2S_DI_EMPTY changes from 1 to 0. Write L channel playing data to CODEC. Write R channel playing data to CODEC. I2S_DI_EMPTY changes from 0 to 1.

Repeat from ・At start playing or during playing

In the case that R channel playing data is unable to be written within half cycle period of LRCLK, Write 000000h to CODEC. I2S_UDF becomes High. playing data written next will go to R channel.

・Stop playing To stop playing, set 0 to I2S_PLAY after disabling interrupt. Then playing stops with clearing FIFO, when I2S_PLAY_RUN changes to 0.

＜Playing data write by I2S_DI_INT rising edge (FYI)＞

Write 1 to I2S_PLAY after enabling I2S_DI_INT interrupt. I2S_DI_INT interrupt occurs. Write a set of LR playing data to FIFO. Write L channel playing data to CODEC. Write R channel playing data to CODEC.

Write one set of LR playing data at each interrupt from here after.

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3.11.9.9. Control Recording Operation from CODEC (REC_C)

bit Name R/W Function 31 I2S_DO_INT RO Becomes High when LR recording data is ready, then

becomes Low after half cycle period of LRCLK. This is the timing to read one set of LR recording data from CODEC.

30:4 X － Indefinite 3 I2S_REC RW Starts recording operation.

0: Stop 1: Start recording

2 I2S_REC_RUN RO Indicates recording operation. 0: Stop 1: during recording

1 I2S_DO_EMPTY RO Indicates data existence in recording data FIFO. 0: data exists 1: no data

0 I2S_DO_FULL RO Indicates the existence of more than or equal to 256 sets of recording data. 0: less than 256 sets 1: more than or equal to 256 sets

3.11.9.10. Recording data input from CODEC (REC_D)

bit Name R/W Function 31:24 X － Indefinite 23:0 I2S_DO RO L/R recording data

Function: Read recording data sampled from CODEC. Initialization: Setup for recording to CODEC. Operation: The procedure to read LR recording data from CODEC by interrupt at I2S_DO_INT rising edge, is shown.

Write 1 to I2S_REC field in REC_C register after setting CODEC to recording operation state and enabling I2S_DO_INT interrupt. At I2S_DO_INT interrupt process, read recording data from REC_D register in the order of L channel recording data and R channel recording data. After here, read one set of recording data in LR order at each I2S_DO_INT interrupt. To terminate recording, disable interrupt and set I2S_REC to 0. When I2S_REX_RUN becomes 0, recording terminates. (When I2S_REC_RUN becomes 0, remaining data in FIFO will be cleared, also.) Then stop the CODEC recording operation.

Notes: Though the recording data is stored into FIFO, FIFO becomes full and recoding data overflows if read out cycle becomes longer than half cycle period of sampling clock (LRCK). I2S_DO_FULL becomes High, when the data more than half of FIFO size is stored.

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3.11.9.11. Read Timing of sampled data FIFO from CODEC

LRCK

EMPTY

FIFO_WE

SDOUT

RE

① ②

④

REC_RUN

DO_INT

③

① ① ② ②

③ ③

④

＜The case by storing LR recording data in FIFO＞

Write 1 to I2S_PLAY, after enabling I2S_DO_FULL (rising edge or High level interrupt). (1) I2S_DO_FULL changes from Low to High, when FIFO has stored more than or equal to 256 sets of LR recording data. (2) Read the 256 sets of LR recording data from FIFO, then I2S_DO_FULL changes from High to Low. (3) Repeat from (2), when I2S_DI_FULL becomes High.

＜The case by reading each LR recording data using I2S_DO_INT as an interrupt.> ・From start recording to during recording

(Read one set of LR recording data at interrupt processing for I2S_DO_INT rising edge.) Set 1 to I2S_REC, after enabling I2S_DO_INT interrupt.

L channel sampling data is stored to FIFO. R channel sampling data is stored to FIFO. I2S_DO_INT interrupt is generated. Read from FIFO, in the order of L channel recording data and R channel recording data.

Repeat from ・Stop recording

To stop recording set 0 to I2S_REC after disabling interrupt, when I2S_REC_RUN changes to 0. Then recording stops with clearing FIFO, when I2S_REC_RUN changes to 0.

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3.11.9.12. Serial Communication between RTC (RTC)

bit Name R/W Function 31:24 X － Indefinite

23 RTC_START RW Starts serial communication between RTC. 0: Stop 1: Start communication

22 RTC_BUSY RO Indicates the communication is busy. 0: not busy 1: busy

21 RTC_DONE RO Indicates termination of serial communication. 0: Stop, communicating if RTS_START equals to 1. 1: Terminated. Cleared if RTS_START is set to 0.

20 RTC_RW RW Transmission form 0: 1 byte write 1: 1 byte read

19:16 RTC_A RW Access register address 15:8 RTC_WD RW write data 7:0 RTC_RD RO read data

Function: RTC with battery back-up Initialization: register configuration Operation: Starts communication between RTC by setting RTC_RW, RTC and RTC_WD (for write

operation) then setting 1 to RTC_START, when RTC_BUSY=0. RTC_DONE changes to 1, when the communication has finished. For RTC_RW=1 (1 byte read), data can be read out from RTC_RD. The communication terminates by setting 0 to RTC_START. RTC_BUSY changing to 1 during RTC_DONE is 1, is indicating that RTC is busy and the communication between RTC is not available. When that duration has passed, RTC_BUSY changes to 0.

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3.11.9.13. PEX Serial Communication Parameter

bit Name R/W Function 31:24 X － Indefinite

23 EXEC RW Start serial communication between PEX 0: Stopped 1: Started communication, during communication

22 BUSY RO Indicates PEX communication is busy 1: busy

21 DONE RO Indicates PEX communication has terminated. 0: During communication or Stop 1: Communication has terminated Cleared by setting 0 to EXEC field.

20 ERR RO Indicates transmission response at I2C communication. 0: ACK 1: NACK

19 X RO Indefinite 18:16 MODE RW Communication mode 15:8 PEX_WD RW Write data 7:0 PEX_RD RO Read data

Function: I2C communication between PEX Initialization: none Operation: none

Please do not write operation as this register is for diagnostics purpose.

3.11.9.14. Timer Counter

bit Name R/W Function 32 DONE RO 1: Stopped

0: Counting 31:0 VAL RW Count value

Function: Counter for timer Initialization: none Operation: none

Please do not write operation as this register is for diagnostics purpose.

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3.11.9.15. USER DIPSW, HW DIPSW Status Capturing and USER LED Control (MISC_F)

bit Name R/W Function 31 CODEC_nRESET RW Release CODEC reset

0: Set CODEC hardware to reset state 1: Release CODEC hardware reset

30:20 X RO Indefinite 19:16 HW_DIPSW RO Indicates the status of hardware configuration switch.

0: ON (short) 1: OFF (open)

15:8 USER_DIPSW RO Indicates the status of User DIP switch. 0: ON position 1: OFF position

7:0 USER_LED WO Control User LED light on/off

0: light off 1: light on

bit

0

1

2

3

4

5

6

7

silk

0

1

2

3

4

5

6

7

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Function: Release CODEC reset, Control USER LED/DIPSW Initialization: none Operation: For USER_DIPSW and USER_LED, write data goes to USER_LED and read data comes from USER_DIPSW status.

3.11.10. FPGA Configuration For FPGA configuration, EEPROM(EPC1S) and FPGA-CFG connector are implemented. As FPGA-CFG connector is connected to FPGA via JTAG signals, FPGA configuration and writing to EEPROM configuration data are available.

FPGA

FPGA CFG

EEPROM

FPGA Configuration block composition

bit

0

1

2

3

4

5

6

7

silk

0

1

2

3

4

5

6

7

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3.12. UART2,3,4 Connector Communication method asynchronous, full duplex Control method TXD,DTR,RTS,RXD,DSR,CTS,DCD,RI Clock frequency 7.3728MHz Communication speed 1200bps ～ 460800bps use device TL16C554APNG4 + MAX3243ECAI+ 3.12.1. COM2,3,4 Connector CN14, CN15, CN16: HTST-105-01-L-DV

1 2

3 4

5 6

7 8

9 10

PIN Name Description PIN Name Description 1 DCD Data carrier detect 2 DSR Data set ready 3 RxD Serial input 4 RTS Request to send 5 TxD Transmit outputs 6 CTS Clear to send 7 DTR Data terminal ready 8 RI Ring detect indicator 9 GND Ground 10 NC Not Connected

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3.13. USB HOST

Indicator VBUS2, VBUS3: light on when power is supplied. use device ISP1761BE controller Cortex-A9 SMC0 + FPGA

Port port1: PCI Express Mini Card port2: USB 2 port3: USB 1

DP and DM signal at each port has an external pull-down register.

3.13.1. USB HOST-IF Connector CN11: 5787745-2

PIN Name Description 1 VBUS POWER 2 D- DATA- 3 D+ DATA+ 4 GND GND

USB 2

USB 1

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3.14. LAN

Indicator SPEED_100 and LINK_ACK status displays are available. use device LAN9118-MT controller Cortex-A9 SMC0 + FPGA 3.14.1. LAN-IF Connector CN12: J0026D21BNL

PIN Name Description 1 TX+ Transmit data+ 2 TX- Transmit data- 3 RX+ Receive data+ 4 5 6 RX- Receive data- 7 8

Yellow Green

1 8

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3.15. SD Card

use device TE4301PF controller Cortex-A9 SMC0 + FPGA CLK_IN 50MHz (external clock input), with STOP control 3.15.1. SD-CARD Connector CN17: DM1AA-SF-PEJ

PIN Name Description 1 CD/DAT3 Data3/Card Detect 2 CMD Command 3 Vss Ground 4 Vdd Power 5 CLK Clock 6 Vss Ground 7 DAT0 Data0 8 DAT1 Data1 9 DAT2 Data2

CD CD Card Detect WP WP Write Protect

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3.16. AUDIO CODEC

use device CS42L51-CNZ AUDIO DATA I2S, CS42L51 master mode control I2C

MCLK 12.288MHz Available Sampling Frequency(Fs) MCLKDIV2 SPEED[1:0] Fs 0 00 96KHz 1 01 48KHz 1 10 24KHz 1 11 12KHz Please do not use other combination shown above.

controller FPGA 3.16.1. Connector CN4: JA33331-H21P-4F

Pin Name BLUE LINE IN AINA(L)/AINB(R)(*2)

GREEN PHONE/LINE OUT(*1) AOUTA(L)/AOUTB(R)(*2) RED MIC IN MICIN1/BIAS

*1 PHONE/LINE OUT is switched by JP1 and JP2 configuration. *2 L:Left channel, R:Right channel

LINE IN

PHONE OUT

MIC IN

BLUE

GREEN

RED

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3.17. RTC

use device RV5C348B-E2-F battery backup BTS1: 74-2032LF (holder) button cell CR2032 controller FPGA

3.18. Switch 3.18.1. POWER SW SW1: JB-15HFBP2

Power ON/OFF switch, valid when 5VSB is supplied via ATX POWER connector. By every pushing, Board power supply ON/OFF is toggled.

3.18.2. RESET SW SW3: JB-15HFBP2 Reset switch for resetting whole board state, reset function is identical with power on reset.

3.18.3. USER DIPSW SW2: CHS-08TA1 DIP switch, the status can be captured by software.

3.18.4. HW DIPSW SW4: CHS-04TA1 DIP switch for board configuration. Please do not change the setting.

01234567

0123

silk

silk

POWER

RESET

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3.19. Jumper Post

JP1, JP2 Change PHONE OUT/LINE OUT at AUDIO output JP3 Change CORE_1.0V power supply 3.19.1. JP1 R Voice Channel XJ8B-0311

1

2

3

JP1 Setting Specification 1 - 2 SHORT PHONE OUT(*) 2 - 3 SHORT LINE OUT

(＊) Default Setting 3.19.2. JP2 L Voice Channel XJ8B-0311

1

2

3

JP2 Setting Specification 1 - 2 SHORT PHONE OUT(*) 2 - 3 SHORT LINE OUT

(＊) Default Setting

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3.19.3. JP3 CPU Core Power Supply XJ8C-0611

1 2

3 4

5 6

JP3 Setting Specification 1 - 2 3 - 4 5 - 6

SHORT SHORT SHORT

supply

1 - 2 3 - 4 5 - 6

OPEN OPEN OPEN

not supply (*)

(*) Please never set the power ON without supplying power to CPU core.

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3.20. Indicators Following indicators (LED) are implemented on PCB.

Indicator (LED) Overview VBUS2(LED4), VBUS3(LED5)

USB bus power ON/OFF display light on: with power supply light off: without power supply

SPEED_100(GREEN) For detail, please refer to LAN controller data sheet.

LINK_ACK(YELLOW)

SB POWER(LED12) Indicates 5VSB power supply state light on: with power supply light off: without power supply

3.3V POWER(LED13) Indicates 3.3V power supply state light on: with power supply light off: without power supply

5V POWER(LED14) Indicates 5V power supply state light on: with power supply light off: without power supply

USER LED (LED6,7,8,9,10,11,15, 16)

light on/off by software control light on: set 1 to corresponding bit in FPGA light off: set 0 to corresponding bit in FPGA (the state after reset)

JTAGnSW(LED17) Indicates JTAGnSW state light on: nSW light off: JTAG

lighting color: pure green

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3.21. Debugger Connector JTAG-ICE connector and TRACE-A connector cannot be used at the same time.

3.21.1. JTAG-ICE Connector CN18: XG4C-2031

PIN Name PIN Name 1 VTref 2 Vsup 3 nTRST 4 GND 5 TDI 6 GND 7 TMS 8 GND 9 TCK 10 GND 11 RTCK 12 GND 13 TDO 14 GND 15 nSRST 16 GND 17 DBGRQ 18 GND 19 DBGACK 20 GND

1

2

19

20

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3.21.2. TRACE-A Connector CN23: 2-5767004-2

PIN Name Description PIN Name Description 1 NC NC 2 NC NC 3 NC NC 4 NC NC 5 GND GND 6 CLK TRACECLK 7 DBGRQ DB_DBGRQ 8 DBGACK DB_DBGACK 9 nSRST DB_nSRST 10 EXTTRIG NC 11 TDO DB_TDO 12 VTRef 1.8V 13 RTCK DB_RTCK 14 Vsupply (3.3V or 1.8V) 15 TCK DB_TCK 16 DATA7 TRACEDATA7 17 TMS DB_TMS 18 DATA6 TRACEDATA6 19 TDI DB_TDI 20 DATA5 TRACEDATA5 21 nTRST DB_nTRST 22 DATA4 TRACEDATA4 23 DATA15 TRACEDATA15 24 DATA3 TRACEDATA3 25 DATA14 TRACEDATA14 26 DATA2 TRACEDATA2 27 DATA13 TRACEDATA13 28 DATA1 TRACEDATA1 29 DATA12 TRACEDATA12 30 GND GND 31 DATA11 TRACEDATA11 32 GND GND 33 DATA10 TRACEDATA10 34 VCC 1.8V(10K-PU) 35 DATA9 TRACEDATA9 36 CTL TRACECTL 37 DATA8 TRACEDATA8 38 DATA0 TRACEDATA0

1

2

37

38

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3.21.3. TRACE-B Connector CN24: 2-5767004-2 (not implemented)

PIN Name Description PIN Name Description 1 NC NC 2 NC NC 3 NC NC 4 NC NC 5 GND GND 6 CLK TRACECLK 7 NC NC 8 NC NC 9 NC NC 10 NC NC 11 NC NC 12 VTRef 1.8V 13 NC NC 14 NC (3.3V or 1.8V) 15 NC NC 16 DATA23 TRACEDATA23 17 NC NC 18 DATA22 TRACEDATA22 19 NC NC 20 DATA21 TRACEDATA21 21 NC NC 22 DATA20 TRACEDATA21 23 DATA31 TRACEDATA31 24 DATA19 TRACEDATA19 25 DATA30 TRACEDATA30 26 DATA18 TRACEDATA18 27 DATA29 TRACEDATA29 28 DATA17 TRACEDATA17 29 DATA28 TRACEDATA28 30 GND GND 31 DATA27 TRACEDATA27 32 GND GND 33 DATA26 TRACEDATA26 34 3V3 1.8V 35 DATA25 TRACEDATA25 36 GND GND 37 DATA24 TRACEDATA24 38 DATA16 TRACEDATA16

3.21.4. DB_DBGACK, TC_EDBGRQ process

Some of ETM Connector port signals have following logic in FPGA.

Cortex-A9 port Configuration DB_DBGACK TC_DBGACK(3) and TC_DBGACK(2) and TC_DBGACK(1) and

TC_DBGACK(0) TC_EDBGRQ DB_DBGRQ

37

38

1

2

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3.22. Power On Reset

Power Management IC activates reset output for a certain duration after finishing FPGA configuration at power up time.

TLC7733 3.3V

PFGA_CONF_DONE

FPGA_INIT_DONE

RESET SW

/BOARDPOR

Power On Reset circuit

3.23. Panel Connector Panel connector is available to route following indicators and switches to outside of PCB. Signal Name Overview

POWER LED Indicates 5V power supply state light on: with power supply light off: no power supply

POWER SW Power ON/OFF switch Power supply is toggled at every pushing.

STANBY LED 5VSB power supply stat light on: power supplied light off: no power supply

RESET SW Reset switch By pushing, PCB is reset.

3.23.1. Panel Connector CN20 : XJ8C-1011

1 2

3 4

5 6

7 8

9 10

PIN Name PIN Name

1 POWER LED + 2 POWER SW1 3 POWER LED + 4 POWER SW2 5 POWER LED GND 6 NC 7 STANBY LED + 8 RESET SW 9 STANBY LED GND 10 RESET SW RETURN

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3.24. Power Supply Connector

3.24.1. Connector CN19: 44206-0007

PIN Name PIN Name 13 +3.3V 1 +3.3V 14 -12V 2 +3.3V 15 COM 3 COM 16 PS_ON# 4 +5V 17 COM 5 COM 18 COM 6 +5V 19 COM 7 COM 20 NC 8 PWR_OK 21 +5V 9 +5VSB 22 +5V 10 +12V 23 +5V 11 +12V 24 COM 12 +3.3V

3.24.2. Connector CN21: HEC0470-01-630

PIN Name 1 GND 2 5V 3 NC

13

1 12

24

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3.25. Cooling Fan Connector 3.25.1. Connector CN26: 0039276023 (not implemented)

1

2

PIN Name 1 5V 2 GND

Cortex-A9 MPCore Evaluation Board KZM-CA9-01 Operation Manual

Revision 1, Issued September 2009 Kyoto Microcomputer Co., Ltd.

Copyright 2009 Kyoto Microcomputer Co., Ltd.

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