cost-based tradeoff analysis of standard cell designs
DESCRIPTION
Cost-Based Tradeoff Analysis of Standard Cell Designs. Peng Li Pranab K. Nag Wojciech Maly Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, PA 15213 {pli, pkn, maly}@ece.cmu.edu. Motivations. Necessity for Evaluation of Designs’ Cost Effectiveness - PowerPoint PPT PresentationTRANSCRIPT
Cost-Based Tradeoff Analysis of Cost-Based Tradeoff Analysis of Standard Cell DesignsStandard Cell Designs
Peng LiPranab K. NagWojciech Maly
Electrical and Computer EngineeringCarnegie Mellon University
Pittsburgh, PA 15213{pli, pkn, maly}@ece.cmu.edu
2 P. Li, SLIP’2000
MotivationsMotivations Necessity for Evaluation of Designs’ Cost Effectiveness
– Tendency of Manufacturing Cost Increase
– Selection of Technology Which Yields the Least Cost
Emergence of Fabless Design Houses
– Choice of Manufacturing Technologies
– Consideration of Manufacturing from Design Perspective
Importance of Early-Stage Predictions
– Reduction of Number of Design Iterations
– Facilitation of Early-Stage Decision
3 P. Li, SLIP’2000
ObjectiveObjective
Cost Prediction for Standard Cell Designs
– Quickly Predict Die Size & Interconnect Yield
As a Function of Number of Metal Layers
Based On a Given Placement
– Predict Die Cost Based on a Wafer Cost Model
– Forecast Optimal Selection of Number of Metal
Layers In Terms Of Die Cost
4 P. Li, SLIP’2000
Why Number of Metal Layers MattersWhy Number of Metal Layers Matters Affect Die Size and Yield An Important Cost Factor
Die Area
1.50
2.50
3.50
4.50
5.50
# of Metal Layers
Are
a
Cost of Die
0.0020.0040.0060.0080.00
100.00
# of Metal LayersD
ie c
ost
5 P. Li, SLIP’2000
ApproachApproach
Given PlacementGiven Placement
Stochastic Pseudo-Routing(Routing Estimation)
Stochastic Pseudo-Routing(Routing Estimation)
Die Height EstimationDie Height Estimation
Die Width EstimationDie Width Estimation
Size Estimate Stable?
Size Estimate Stable?
Interconnect Critical Area Analysis
Interconnect Critical Area Analysis
Interconnect Yield Prediction
Interconnect Yield Prediction
Cost PredictionCost Prediction
6 P. Li, SLIP’2000
Stochastic Pseudo RoutingStochastic Pseudo Routing
Stochastic Pseudo-Routing
Defects
Expanded/Compacted Placement
Given Placement
Estimated Routing Utilization
Interconnect Yield Prediction
Wafer Cost Model
7 P. Li, SLIP’2000
Layout Representation Layout Representation Grid Routing Model
– Horizontal Routing Layers: Metal1, Metal3, Metal5 etc.
– Vertical Routing Layers: Metal2, Metal4, Metal6 etc.
Cell height defined by cell library
Channel GridsCell-Row Grids
Channel height to be estimated
Chip width to be estimated
Grid width
8 P. Li, SLIP’2000
Stochastic Pseudo Routing of Two-terminal NetsStochastic Pseudo Routing of Two-terminal Nets Restrict routing estimation within
the bounding box of the net.
Only consider Manhattan paths
having no more than two vias.
There are totally PNUM =
(M+N-2) path candidates.
Assume each path candidate
has a probability of 1/PNUM of
being selected.
N
M
9 P. Li, SLIP’2000
Stochastic Pseudo Routing of Two-terminal NetsStochastic Pseudo Routing of Two-terminal Nets From Probabilities To Routing Utilization Estimates
p1
p2
p1
p2p3
p4
p1
p2
p1
p2
p4p3
10 P. Li, SLIP’2000
Extension of Pseudo Routing of Two-Terminal Nets– Find A Minimum Spanning Tree
– Pseudo Route Each Edge of The MST
– Consider wiring sharing among MST Edges Assume Pseudo-Routing of MST edges are independent of each
other:
Stochastic Pseudo Routing of Multi-Terminal NetsStochastic Pseudo Routing of Multi-Terminal Nets
Pin1
Pin5
P4
Pin2
Pin3
)0.1(0.1 iPP
Merged Segment
Merged Region
p1
p2
p4
p5
p3
11 P. Li, SLIP’2000
Die Size EstimationDie Size Estimation
Stochastic Pseudo-Routing
Defects
Expanded/Compacted Placement
Given Placement
Estimated Routing Utilization
Interconnect Yield Prediction
Wafer Cost Model
12 P. Li, SLIP’2000
Die Height EstimationDie Height Estimation Lower Bound of Total Channel Density
– Based on horizontal routing utilization estimation.– “Switchable Routing Demand”
Analogy to switchable net segments
– Assign “switchable routing demand” to proper channels to minimize total channel density.
Channel Density: 4
ChannelsCell Rows
13 P. Li, SLIP’2000
Die Width EstimationDie Width Estimation Expand/Compact based on difference between
routing demand and capacity.
Iterate on updated cell locations.
Compaction
Expansion
Estimated Vertical Routing Utilization
14 P. Li, SLIP’2000
Interconnect Yield PredictionInterconnect Yield Prediction
Stochastic Pseudo-Routing
Defects
Expanded/Compacted Placement
Given Placement
Estimated Routing Utilization
Interconnect Yield Prediction
Wafer Cost Model
15 P. Li, SLIP’2000
Interconnect Yield PredictionInterconnect Yield Prediction Traditional Methods
– Layout Based Critical Area Extraction Requires final layouts Accurate but time consuming: Mapex, Dracula
– High-Level Interconnect Model Relates the yield to netlist characteristics
Our Approach– Based On Routing Utilization Estimation
Empirical Routing Heterogeneity Model Closed-Form Critical Area Expression
– Linear Time Algorithm
16 P. Li, SLIP’2000
Cost PredictionCost Prediction
Stochastic Pseudo-Routing
Defects
Expanded/Compacted Placement
Given Placement
Estimated Routing Utilization
Interconnect Yield Prediction
Wafer Cost Model
17 P. Li, SLIP’2000
Cost PredictionCost Prediction Wafer Cost Model of 0.25 m CMOS Process Prediction of Cost As Function of Number of
Metal Layers– Number of Good Dies Per Wafer:
Ngood(M) = Awafer / Adie(M) ·Yield(M)
– Cost of A Good Die:
Cdie(M) = Cwafer(M) / Ngood(M)
18 P. Li, SLIP’2000
Experimental ResultsExperimental Results Experiment Setup
– Six Standard Cell Designs Portions of Industrial DSP circuits
Design Name # of Cells # of Nets1 Sync2 3440 34672 Cdgc2 2751 34033 Fifo2 2390 24294 Ifagc2 382 5345 Prescale 2021 28266 Hnyq 2608 3806
– Comparison With Data Based On Layouts 2-4 metal layers Our method : die size, routing utilization and yield Cadence tools: layout generation, critical area
extraction(Dracula) and yield calculation
19 P. Li, SLIP’2000
Experimental ResultsExperimental Results Die Size Estimation
32 4 65
-0.1 -5.5
5.0
-7.9
3.1
6.6
-5.5 -19.7
13.4
17.0
3.714.0
2.8 -1.7
3.6
6.2
3.5-0.3
Design
Area CadenceEstimated% Error
2 Metal3 Metal4 Metal
1 2 3 4 5 6
20 P. Li, SLIP’2000
Experimental ResultsExperimental Results
Estimated Routing Distribution
Distribution Generated by Route Tool
Heavily Routed Areas
Routing Utilization Distribution
21 P. Li, SLIP’2000
Experimental ResultsExperimental Results Yield Prediction
Design
CadenceEstimated2 Metal
3 Metal4 Metal
1 2 3 4 5 6
Yield
22 P. Li, SLIP’2000
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
1 2
2 Metal3 Metal4 Metal
Experimental ResultsExperimental Results
Optimal Number of Metal LayersDesign Est. Optimal Number of Metal Layers Est. Optimal Cost($)
1 4 2.512 3 2.473 3 2.134 2 .2255 4 2.156 4 2.34
Design3 Design5
Cost As a Function of Metal Layers
Cost($)
23 P. Li, SLIP’2000
SummarySummary Fast Routing Estimation Technique
– Die Size– Routing Utilization Distribution– Interconnect Yield Prediction
Cost Prediction– Prediction of Optimal Number of Metal Layers
Directions– A Priori Wire Distribution/Placement Estimation
Standard cell design style Realistic wiring density distribution
– Consideration of Circuit Performance Issues