cut the ps bs - t&vs...why waste your life writing and debugging tests? design 32% verification:...

The Leader in Portable Stimulus

Cut the PS BS Practical Test Synthesis For Your

SoC & UVM Environments

© Breker Verification Systems, Inc. All rights reserved. Breker Confidential

Adnan Hamid, Breker President & CEO DVClub Europe, September 2018

A Brief History of Portable Stimulus

1990 1994 2008 2018 2015

© Breker Verification Systems, Inc. All rights reserved. Breker Confidential 2

2020

Undergraduate work on AI Machine Problem Solving

ST Display Controller • eRM Unit Bench • C SoC Bench

Accellera PSWG Started

Accellera PSS 1.0 release

Accellera PSS 2.0 release ?

AMD x86 Testing • Simulation • Quickturn • Custom Boards ( 1B cyc/day )

Why Waste Your Life Writing and Debugging Tests?

Design 32%

Verification: Other 13%

Verification: Test Development

30%

Source: Wilson Research / Mentor 2016

Project Resource Deployment

Verification: Debug

25%


• Verification Planning • Scenario Decomposition • Abstracted Implementation

• Test Case Synthesis • Correct by composition • High Level Debug

Realizing the Breker Verification Vision

© Breker Verification Systems, Inc. All rights reserved. . Breker Systems Confidential 4

SD

Sys

DC

PP

Cam

Scenario Model

TrekDesigner TrekApps

Cache Coherency Power Mngt

ARMv8

TrekUVM TrekSoC-Si TrekSoC

TrekGen

• Graph-based Simplified decomposition of complex scenarios, leveraging enhanced Portable Stimulus to generate effective test sets

• Portable Accelerated deployment of self-checking test cases into existing UVM & SoC environments

• Shareable Enhanced, revolutionary test space analysis, reuse and global cooperation, aided by Breker-lead Accellera standardization

PSS Test Synthesis

Optimization &

Deployment

PSS Describes Graphs


component T { action A { output Buf out; }; action B { input Buf in; }; action C { input Buf in; }; pool Buf p; bind p *; action E { B b; C c; activity { schedule { select { b, c } select { b, c } } } } }

A B P

C A P

A B P

C A P

UART Parity even

UART VIP mode_A

mode_B

in out

Parity odd

Parity on

Parity off

Simple Scenario Generation Example

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Simple Example: UART Parity Check Test Graph-based

Testbench

SoC RTL

CPU0 Memory

Fabric

Fabric

UART

UART VIP

UART Embedded in larger SoC

Graph segment: Data transfer and parity check

Tests pieced together by walking graph and solving random variables

class UartParityEven : public action { PSS_CTOR(UartParityEven, action); // Action_UartParityEven uart_block& blk { *sys.uarts.at(0) }; hsi::status_e status; void body() { blk.UART_LCR.PARITY_EVEN.set(1); } };

Each action has respective code segment

uart_block& blk { *sys.uarts.at(0) }; action UartParityEven { exec body { blk.UART_LCR.PARITY_EVEN.set(1); } };

C++

DSL Config DUT

Config VIP

Send Tx Data

Check VIP Data

http://sys.uarts.at/

Test Case Optimization, Deployment & Analysis UVM, SoC, Final Silicon: Breker Targets Noted Engineering Pain Points

Testbench

DUT

Simplified, synchronized UVM

test-bench synthesis

UVM Agent

UVM Agent

TrekUVM

Synthesized, self-checking diagnostics for prototyping & silicon

TrekSoC-Si

test.c test.c test.c

Compiler

test.c test.c test.tbx Tr

ekB

ox

event id

Multi-threaded, simulation & emulation software-driven SoC test generation

OS or Bare Metal

Multi-threaded tests

TrekSoC

VIP VIP

Cache-Coherent Switching Fabric

CPU CPU CPU CPU

L1 L1 L1 L1 L2

CPU CPU CPU CPU

L1 L1 L1 L1 L2

…

GPU

Cache

L3 Cache

Memory Controller

Memory Controller I/O I/O Offload


Portable

TrekGen

Path Analysis and Reachability

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Reason about which paths have been exercised

Size of overall search space

Node not reachable

Some paths to node are not reachable

High-level Test Debug Driving Issue Resolution


Portable 4 processors, 1 thread per processor

Green nodes have finished

Yellow nodes are running

Blue nodes are waiting to run

Memory Usage by Region Data used/changed by a task

Software Driven Test Source

Test Execution Log

Failing Node

Tight integration to Verdi

Various verification planners

Coverage Closure and Export

Scenario coverage reported on graph and in test list

Auto-coverage closure: push button test completion

Reporting: coverage detail output to third party verification planners


Portable

With Coverage Closure

Without Coverage Closure

Practical Application of Portable Stimulus

PSS: powerful way to generate tests from abstract, randomized scenarios

Practical test deployment into testbenches requires additional capability

PSS plus optimizing solutions will revolutionize SoC and UVM verification


cut the ps bs - t&vs...why waste your life writing and debugging tests? design 32% verification:...

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