D. Goren, R. Gordin, M. Zelikson

Modeling Methodology for Modeling Methodology for On-Chip Coplanar On-Chip Coplanar

Transmission Lines over the Transmission Lines over the Lossy Silicon SubstrateLossy Silicon Substrate

Problem definition:Problem definition:Critical wiring must be precisely designed Critical wiring must be precisely designed

and modeledand modeled

A&MS design methodology is not adequate A&MS design methodology is not adequate State of the art in interconnect extraction is mostly RC. State of the art in interconnect extraction is mostly RC.

Even around 1GHz, inductance starts to impact longer Even around 1GHz, inductance starts to impact longer lines behaviorlines behavior

Fully automated inductance extraction is impossible Fully automated inductance extraction is impossible without exact knowledge of the return paths, which is without exact knowledge of the return paths, which is not always practical at post layout extractionnot always practical at post layout extraction

Post layout extraction for high frequency design is Post layout extraction for high frequency design is usually too lateusually too late

Microwave design methodology is not Microwave design methodology is not adequate as welladequate as well Traditional microwave concepts (Impedance matching, S Traditional microwave concepts (Impedance matching, S

- Matrix) are not applicable for most A&MS designs - Matrix) are not applicable for most A&MS designs Fully nonlinear, large signal transient SPICE simulations Fully nonlinear, large signal transient SPICE simulations

requiredrequired Mixed signal simulations requiredMixed signal simulations required

Existing IBM interconnect-aware design flow Existing IBM interconnect-aware design flow

(patent filed)(patent filed)

Sorting wires into 2 groups: Sorting wires into 2 groups: criticalcritical, small group, small group non-critical,non-critical, most of the wires most of the wires

Design of critical wires:Design of critical wires: Predefined set of parametrized Predefined set of parametrized

T-line T-line structures as structures as design design componentscomponents

Pcell based: Pcell based: T-line device =T-line device = symbol+schematic+layout symbol+schematic+layout views views

DRC and LVS clean layoutDRC and LVS clean layout Monitoring T-line parameters Monitoring T-line parameters

is enabledis enabled Smart extractionSmart extraction

UseUse T-line modelsT-line models for for critical critical wireswires

Use Use RC extractRC extract for for non-critical non-critical wiringwiring - sufficient accuracy - sufficient accuracy

Back-annotate final T-lines Back-annotate final T-lines parametersparameters

Schematic design including T-line models

Smart Extraction

Physical Design. T-lines as p-cells

Final Simulation

High Level Design

FloorplanArchitecture

Identify critical interconnect

Production level Production level T-line cross sections (1)T-line cross sections (1)

Microstrip T-lines

S

G

S2S1

G

GG S

G

via

via

GG S2S1

G

via

via

Silicon substrate Silicon substrate

Lossless oxide dielectric

Lossless oxide dielectric

Production level Production level T-line cross sections (2)T-line cross sections (2)

Coplanar T-lines

GG S GG S2S1

Modeling technique:Modeling technique:high level descriptionhigh level description

T-line structure

T-line: R(f), L(f), C(f)

Equivalent RLC

network

Based on multi-segment RLC networks – inherent Based on multi-segment RLC networks – inherent passivity and migratability between circuit simulatorspassivity and migratability between circuit simulators

Comprehensive methodology for RLC network Comprehensive methodology for RLC network constructionconstruction

Semi-analytical explicit expressions for all RLC network Semi-analytical explicit expressions for all RLC network parametersparameters

Covers both skin & proximity effects, as well as silicon Covers both skin & proximity effects, as well as silicon substrate effectssubstrate effects

Covers full bandwidth of interest: from DC till the given Covers full bandwidth of interest: from DC till the given chip technology transistors cut-off frequencychip technology transistors cut-off frequency

Model order reduction usually not required due to the Model order reduction usually not required due to the small number of critical linessmall number of critical lines

Modeling technique:Modeling technique:ZY-networkZY-network

Tline segment

G(f) C(f)

R(f) L(f)

~20 equal segments per wavelength

ZY

ZY

ZY

Z-element: longitudinal current in metal and substrate

T-line segment

ZY

Y-element:transverse current in metal and substrate

Modeling the Z-element:Modeling the Z-element:problem descriptionproblem description

R(f)

f

L0

L∞

ftr

f << ftr :the current is uniformly distributed in all the metal cross-sectionsf >> ftr :the current is non uniformly distributed at the surface of the metals

L(f)

fR0

R(f)~f

ftr : transition frequency, at which the skin depth is comparable with relevant cross-section dimensions

Modeling the Z-element:Modeling the Z-element:previous approachesprevious approaches

Analytical results for ∆L and ∆G exist only for ideal parallel plates case

R(f)L(f)

10 L + G elements per one frequency decade – too many

∆G

∆G

∆G

L∞∆L

∆L

∆L

Complicated expressions for R(f) and L(f) from the network– hard to fit to asymptotic frequency conditions Other approaches: less elements using non-uniform ladders (e.g. geometric series for ∆Gi: S.Kim, D.Neikirk, MTT-S 1996)

Wheeler’s original approach (1942)

Modeling the Z-element:Modeling the Z-element:suggested approachsuggested approach

Simple expressions for R(f) and L(f) – enable convenient fitting to asymptotic frequency conditions Only one basic element required per each frequency decade

Parameters of basic elements are calculated from R0 , L0 ,L∞ , and R high freq = kf using Wheeler’s incremental rule

L∞

∆L1

∆R1

∆Ln

∆Rn

One basic element for each freq. decade

Ro

Modeling the Y-element:Modeling the Y-element:problem descriptionproblem description

G(f) C(f)

f

G∞

0frel f

C0

0

C∞

frel

s

s

π21

relf

f << frel :the substrate behaves as an ideal metal

f >> frel :the electric field in the silicon substrate is the same as it would be for an ideal dielectric

Modeling the Y-element:Modeling the Y-element:previous approachesprevious approaches

Exact model only for ideal parallel plate capacitor filled with silicon, for which electric field is uniform and frequency independent

In real coplanar cases, electric field is non-uniform and frequency dependent

G(f) C(f)Gs Cs

Cox

Cside

s

s

s

s

CG

Signal to metal ground

Modeling the Y-element:Modeling the Y-element:suggested approachsuggested approach

Fitting is possible using: {C0, G0=0}, {C∞, G∞}, plus n-1 {C(fk), G(fk)} values

G(f) C(f)

s

s

si

si

CG

∆Gs1 ∆Cs1

∆Cox1Coxo

∆Gs1 ∆Csn

∆Coxn

n basic networks

The Y-element catches the substrate induced effects: Signal attenuation Impedance frequency dependence Slowing of wave propagation

Coplanar T-line cross sections Coplanar T-line cross sections

Lossy silicon substrate

Lossless oxide dielectric

Lossless oxide dielectric

GG S

Lossy silicon substrate

GG S2S1

Odd mode Even mode

and working operation modesand working operation modes(matching the measurements setup)

Single lineSingle line Coupled lineCoupled line

T-line length: 100 um - several mm

(several-tenths) microns

several micronshundreds of microns

metal ~5*107 1/Ohm*m, sub ~(5-100) 1/Ohm*m

=

Silicon substrate longitudinal Silicon substrate longitudinal current in coplanar T-lines: main current in coplanar T-lines: main

casescases

Dielectric

GG S

GG S2S1

Single lineSingle line Coupled lineCoupled line

Floating substrate (no substrate Floating substrate (no substrate contacts)contacts)

Coupled T-line at odd modeCoupled T-line at odd mode

- no longitudinal current- no longitudinal current Substrate “grounded at infinity”Substrate “grounded at infinity”

Substrate contacts at both T-line Substrate contacts at both T-line endsends

- a real life example:- a real life example:

Substrate contact

p+ Substrate (p) Substrate

contact

p+

Silicon substrate longitudinal Silicon substrate longitudinal current in coplanar T-lines:current in coplanar T-lines:

real life examplereal life example

p+

δ(f)

GG S

Substrate

contact

p+

1um 1um

0.5um

0.5um

p+ 0.2um

(1x1)um

length=300um

ρsilicon

Silicon substrate longitudinal current appears when:

2f*L*length ~ Rsilicon Rsilicon = spreading resistance + metal contact resistanceL = Inductance of coplanar structure without substratef = operation frequency

Note: spreading and metal contact resistances may be comprarable!

Silicon substrate longitudinal Silicon substrate longitudinal current in coplanar T-lines:current in coplanar T-lines:

real life examplereal life example

p+

δ(f)

GG S

Substrate

contact

p+

1um 1um

0.5um

0.5um

p+ 0.2um

(1x1)um

length=300um

ρsilicon

Note: length < quarter wavelength - to avoid resonances on chipL -> L∞ = time-of-flight2/Capacitance-without-substrate

Results:Spreading resistance ~6k OhmMetal-silicon contact resistance~5k OhmAt f=100 GHz, the onset of silicon substrate longitudinal current Is when: ρsilicon~0.1 Ohm-cm – very low! Real values are (1-15) Ohm-cm !

Assume: f=100 GHz

IBM T-line test cage IBM T-line test cage with coplanar lineswith coplanar lines

coupled coplanar Tline, MA/sub

single coplanar Tline, MA/sub

S-parameters S-parameters of a single coplanar T-line, MA/subof a single coplanar T-line, MA/sub

Solid: 40GHz VNA measurement, dotted: model

S11(magnitude) S11(phase)

S12(phase)S12(magnitude)

S-parameters of a coupled coplanar S-parameters of a coupled coplanar T-line, MA/sub, odd modeT-line, MA/sub, odd mode

S11(magnitude) S11(phase)

S12(phase)S12(magnitude)

Solid: 20GHz VNA measurement, dotted: model

S-parameters of a coupled coplanar S-parameters of a coupled coplanar T-line, MA/sub, even modeT-line, MA/sub, even mode

S11(magnitude) S11(phase)

S12(phase)S12(magnitude)

Solid: 20GHz VNA measurement, dotted: model