david merodio codinachs esa (estec, tec-edm)e7%f5es/31/31out2012%20-… · •fpgas: where are they...

David Merodio Codinachs

ESA (ESTEC, TEC-EDM)

31 May 2010 IV WERICE 1

• Introduction of ESA

• FPGAs: where are they used?

• FPGAs introduction

– General

– Architecture introduction

• Which FPGAs are used in space?

• FPGA development flow and standard

• Radiation and design for Space

– Mitigation techniques

• Examples of tools use (XTMR, Ukube)

• Conclusion 31 May 2010 IV WERICE 2




– General









http://www.esa.int/SPECIALS/ESTEC/index.html

European Space Research and Technology Centre (ESTEC)


“To provide for and promote, for exclusively peaceful purposes, cooperation among European states in

space research and technology and their space applications.”

Article 2 of ESA Convention

ESA has 19 Member States: 17 states of the EU (AT, BE, CZ, DE, DK, ES, FI, FR, IT, GR, IE, LU, NL, PT, RO, SE, UK) plus Norway and Switzerland.

Eight other EU states have Cooperation Agreements with ESA: Estonia, Slovenia, Poland, Hungary, Cyprus, Latvia, Lithuania and the Slovak Republic. Bulgaria and Malta are negotiating Cooperation Agreements.

Canada takes part in some programmes under a Cooperation Agreement.


• Over 40 years of experience

• 19 Member States

• Five establishments in Europe, about 2200 staff

• 4 billion Euro budget (2012)

• Over 70 satellites designed, tested and operated in flight

• 17 scientific satellites in operation

• Six types of launcher developed

• Celebrated the 200th launch of Ariane in February 2011



• Space science

• Human spaceflight

• Exploration

• Earth observation

• Launchers

ESA is one of the few space agencies in the world to

combine responsibility in nearly all areas of space activity.

• Navigation

• Telecommunications

• Technology

• Operations




– General









Sentinel-1

Earth observation

Sentinel-2

Earth observation

Herschel

Space science

ATV

Human spaceflight

Hylas-1

Telecommunications

Ariane5

Launchers

• Structures

• Power

• Thermal Control

• Attitude Control

• Guidance

• Command and Data Handling

• Propulsion

• Harness

• Payload

• Life Support

• Launcher

• Ground Segment


• SpaceCraft subsystems:

Some examples:

• On Board Computer

• Mass memory

• Remote Terminal Units

• Data interfaces

• etc …

FPGAs used in many of the subsystems

• Sentinel-2 example:


IC type Where Quantity

ASIC P/F 59

ASIC P/L 0

FPGA P/F 112 FPGA P/L 37 uP P/F 21

uP P/L 0

Std ASIC P/F 10

Std ASIC P/L 0

P/L: Payload

P/F: Platform TOTAL: 249 high complexity integrated

circuits




– General








• Integrated Circuit – Manufacturing Flow overview:

Silicon Ingots

Processed Wafer Dies Component

Foundry: Silicon Wafers SiO2 (Sand)

Courtesy: Boris Glass

Requirements/Spec GDSII Circuit Design


• FPGA – “Manufacturing Flow” overview

FPGA “general”

Component

FPGA with user Application Functionality

Program/

Configure

FPGA: Integrated Circuit designed to be configured/programmed by the customer/designer after manufacturing (i.e. Field Programmable)

IC Manufacturing Requirements/Spec

Bitstream

Circuit Design


• Programming/ configuration technologies:

Antifuse SRAM Flash

One-time programmable

Reprogrammable (fast, unlimited)

Reprogrammable (slower, “limited”)

Requires external NVM

(Antifuse example) (SRAM 6 transistor example) ProASIC3/E Flash Based Switch


• FPGA selection includes several aspects (not exhaustive list):

– Capacity and performance (frequency and power consumption)

• Related to the internal architecture and technology node used

• Related to Mass and Volume, as it enables miniaturization

– Radiation hardness

• Addressed at different levels:

– Process

– Transistor/ Standard Cell

– Register Transfer (RTL)

– System

– Reconfigurability

– Quality, Packaging, Assembly

– Others:

• ITAR (International Traffic in Arms Regulations)

The regulations are described in Title 22 (Foreign Relations), Chapter I

(Department of State), Subchapter M of the Code of Federal Regulations.

• Cost


• The problems

– SEU

– SET

– SEFI

– SEL (*)

– TID (*)


• The solutions

– Device-level solutions

• Make the device design rad tolerant

– Design-level solutions

• Make your design rad tolerant (Mitigation techniques)

Courtesy: Massimo Violante

(*) Device-level only

• FPGA related disciplines

– Microelectronics digital design • Implement the functionality inside the FPGA

– Radiation • Components hardness & Space radiation (mission dependent)

• Mitigation techniques to be taken into account by the microelectronics designer/s

– Power conditioning

– Packaging

– Evaluation and qualification





– General








• FPGA Architectural features (general):

Logic fabric

Inter- connection

Internal memory

Arithmetic (Multipliers, DSP, …)

Flexible IOs

High speed serial links

Clock generation (PLLs, DLLs,…)

Embedded processors

Other hard-macros (PCIe, …)

• Logic Fabric

– The basis of the generic functionality • Lookup table (LUT)

– Implements any logic function of its k-inputs

• FA (or adder capabilities)

• DFF

(Simplified view of a logic cell) 31 May 2010 IV WERICE 23

• LookUp Table (LUT):

– LUT: Another way of implementing a function. For instance, for 3-inputs:

a

b

c

fc(a,b,c)=not(a) and b and c a b c fc

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 0

fc


• Functions implemented in the Logic Cell, example:

fc(a,b,c)=not(a) and b and c

Implementation of the

function (including the

DFF) in the Logic Cell

fc


• Logic Cell example, conceptual views:

Note: For conceptual views representation; Neither exhaustive nor accurate

“Functional

View”

“Implementation

View”

“Configuration

Memory View”

fc(a,b,c)=not (a) and b and c





– General








• RTSX (RTSX32SU, RTSX72SU)

– ITAR

– Rad Hardening techniques

• User FFs SEU hardened

• LETTH in excess of 40 MeV-cm2/mg

– TID 100Krad; Packages: CQFP-84/208/256

• RTAX (RTAX250-4000S/SL)

– ITAR

– Radiation characteristics

• User FFs SEU hardened

• LETTH in excess of 37 MeV-cm2/mg

• Cross-section < 1E-9 cm2

• Embedded block RAM not rad-hard:

Mitigation technique required

• TID 300 Krad

– Packages: CQFP-208/352, CCGA/LGA-624/1152, 1272


• Xilinx Q-Pro family (SRAM-based) • Virtex (V): XQRV300/600

• Virtex 2 (V2): XQR2V3000/6000

• Virtex 4 (V4): XQR4VLX200, XQR4VLX200, XQR4VSX255, XQR4VFX140

– ITAR

– 0.22um (V), 0.15um (V2), 90nm technologies (V4)

– Advanced architecture including embedded Hard IPs (depending on the family and device)

• DSP Slices/Multipliers; Ethernet MAC Blocks; HSSL

• PowerPC Processor Blocks

– Radiation characteristics

• Configuration memory, BRAM and FFs are not

rad-hard: mitigation techniques required

• TID: 100 Krad (V); 200 Krad (V2); 300 Krad (V4)

– Packages: CB228 ; CG717; CF1144/1140/1509


• Other Microsemi FPGAs:

– RTAX-DSP FPGAs

– ProASIC3 (Flash-based)

• TID limits its use

• SET mitigation might be required (addressed in the previous talk)

• Other Xilinx FPGAs:

– Virtex-5QV (SIRF)

– Packages FF665/1136/1738: BIG CHALLENGE (addressed in the previous talk)


• The Atmel ATF280E

• Non-ITAR (European)

• It has hardened – Configuration memory

– User FFs

– User memory

• TID tested upto 300Krad

• Packages: CQFP-84/208/256

• Development tools: IDS (improvements ongoing)


• Future FPGA of the AT40K family:

– 450 Kgates FPGA/SOI

• Multi-Chip Package solutions:

– 280 Kgates FPGA + 4 Mbit EEPROM in one package

– Reprogrammable Computer in one package: LEON2 AT697F + 280 Kgates FPGA in one package

• Next challenge:

>1Mgates European space reprogrammable FPGA

(ITAR free)



http://spacefpga.atmel-nantes.fr/spacefpga/


Note: Figure to be updated


vendor

Device type

datasheet QPro™

Virtex™-II

Virtex-5QV RTproASIC3 RTAX-S/SL AT40KEL040

TID (Krads(Si)) 200 >1000 >100; >45 if

reprogramming

300 300

SEL (MeV/mg/cm2)

> 160 >125 >64 > 117 80

SEU sat cross

section

(cm2/bit)

Or

GEO

(Errors/Bit-

Day)

GEO upsets <

1.5E-6 per device

day (with TMR+

SRAM scrubbing)

Conf. bits 4.85

Upsets/Device/Ye

ar ; SEFI static

9,930 U/D/Y

BlockRAM ~2.5E-

11 U/D/D ;

dynamic blocks

~2.7E-4 U/b/day

2E-7 cm2 per flip-

flop; 4E-8 cm2 per

SRAM memory

bit; none for

FLASH

< 1E-10 Worst-

Case GEO

2.5E-8 (*)

2.5E-7 (**)

SEU LETth (MeV/mg/cm2)

Very low >96 (FLASH),

>6(FF),

>1(SRAM)

>37 16 (*)

15 (**)

SET 2E-6 cm2 per

global clock

network, per IO

bank, low LETth

No Anomalies up

to 150 MHz

As MH1RT ASICs

http://klabs.org/richcontent/MAPLDCon03/logos/xilinx_logo.gif

• Today, ESA missions use mainly FPGAs from Microsemi.

• Xilinx FPGAs are used seldom, in “non critical” applications.

• Atmel space FPGAs are starting to be used slowly, and expected to grow in capacity, but resource-sharing is sub-optimal.





– General








Architecture Definition

RTL implementation

Synthesis

Place & Route

Bitstream Generation

VHDL

Bitstream

Constraints

FPGA Library STA

Gate-Level simulations

Netlist

P&R Netlist

- Technology (FPGA type)

- Environment (Voltage,

IOs types,

In/Out delays …)

- Performance (MHz, …)

- Radiation…

Radiation?

RTL sims.

Requirements/Spec (Note: Simplified view)



• The European Cooperation for Space Standardizationis an initiative established to develop a coherent,single set of user-friendly standards for usein all European space activities.

• ECSS-Q-ST-60-02C is a Space product assurance standard for ASIC and FPGA development

http://www.ecss.nl

• Milestones defined in the ECSS-Q-ST-60-02C standard are (with general comments, non exhaustive):

– SRR: System Requirements Review • Requirements, feasibility and risk analysis finalized

– PDR: Preliminary Design Review • Architecture definition, full verification finalized

(=> all VHDL has to be already implemented !)

– DDR: Detailed Design Review • Netlist finalized and verified, including timing (i.e. Synthesis&STA

completed)

– CDR: Critical Design Review • Layout generation and verification finalized

– QR/AR: Qualification and Acceptance Review 31 May 2010 IV WERICE 40


RTL implementation

Synthesis

Place & Route


VHDL

Bitstream

Constraints

FPGA Library

STA Gate-Level simulations

Netlist

P&R Netlist

RTL sims.

Requirements/Spec

(Note: Simplified view)





– General








• Single Event Latchup (SEL)

• Single Event Transients (SET)

– in clocks and resets

• Glitches on clocks → change of state,

functional fault

• Asynchronous resets are clock-like

signals

– Single Event Transients (SET) in combinatorial logic

• SEE glitches in combinatorial logic behave like cross-talk effects

• Causes SEU when arriving at flip-flop/memory D-input during clock edge

• Sensitivity increases with clock frequency

• Synchronous resets are (normal) combinatorial signals

• Single Event Upset (SEU) in Flip-Flops and SRAM

– SEE glitch inside the bistable feedback loop of storage point

– Immediate bit flip → loss of information, change of state, functional fault


• Validate mitigation techniques:

– Using the programmed/ configured FPGA:

• Ground Accelerated radiation testing

• Laser testing


Program/

Configure

Requirements/Spec

Bitstream

Circuit Design

• Implement and Verify the mitigation techniques:

– Tools to assist the designer during the “Circuit Design” to design, verify and possibly quantify the mitigation techniques. FOCUS of the Talk

Programmed/Configured FPGA


RTL implementation

Synthesis

Place & Route


VHDL

Bitstream

Constraints

FPGA Library STA

Gate-Level simulations

Netlist

P&R Netlist

- Technology (FPGA type)

- Environment (Voltage,

IOs types,

In/Out delays …)

- Performance (MHz, …)

- Radiation…

Radiation?

RTL sims.

Requirements/Spec (Note: Simplified view)


RTL implementation

Synthesis

Place & Route


VHDL

Bitstream

Netlist

P&R Netlist

(X)TMR manipulation

STAR (SUSANNA-JONATHAN)

RoRA/VPLACE

SETA

SET-aware P&R

• Tools related to SEE protection insertion, analysis and optimization:

In orange tools developed totally or partially with

R&D ESA (TEC-EDM)

INFAULT (Formality)

Fault Injection


RTL implementation

Synthesis

Place & Route


VHDL

Netlist

P&R Netlist

RTL sims.

Requirements/Spec

𝜀𝑘

• Tools related to SEE dynamic assessment:

(*) Relevant Application Stimuli

(**) Design in one of the formats

(*) (**)

FI Tools examples:

FT-UNSHADES/2,

FLIPPER

The above mentioned tools are developed totally or partially with

R&D ESA (TEC-EDM)


Tool Name Developer Tech

SE

U

injectio

n

SE

U sim

at

SW

speed

SE

U em

u at

HW

speed

Mo

nito

r fault

pro

pag

ation

SE

U w

eak

areas find

ing

Reco

gn

ize &

check

TM

R

SE

U in

FP

GA

Co

nf m

em

Imp

rov

e P&

R

of S

RA

M-

FP

GA

FT-

UNSHADES U. Seville (E) all yes yes yes yes yes

SST ESA (NL) / U.

Antonio Nebrija (E) all yes yes yes yes

FLIPPER INAF (I) Xilinx

FPGA yes yes yes yes yes

STAR/VPLACE

/RoRA P. Torino (I)

Xilinx

FPGA yes yes yes

INFAULT ESA (NL) all yes yes

SUSANNA/

JONATHAN P. Torino (I) / ESA

(NL)

Atmel

FPGA yes yes yes

Virtex 2 Virtex 4 Virtex 5

STAR/RoRA/VPLACE

Available Available Starting

FLIPPER Available Almost available

Pending





– General








• Use of XTMR

– Benefits of using XTMR

– What about STAR/RoRA/VPLACE?


• Device: – XQR3V3000

Die size ~16x16 mm2

• Results: – 2 clock: XTMR not

active

– 3 clock: XTMR active


Clear added value when

using XTMR ….

BUT, is it enough?


Original netlist SEE-corrupted netlist

Domain 1

Domain 2

Domain 1

Domain 2

The SEE modifies the same signal in two domains

SEE is producing multiple effects not masked by

voters

Courtesy: Massimo Violante

• In spite of (X)TMR, single point failures (SPF) still exist – Optimization during layout leads to close-proximity implementation

• Flipping one bit may create a short between two voter domains

• Flipping one bit may change a constant (0 or 1) used in two domains

– Malfunction in two domains at a time can not be voted out any more

• The Reliability oriented place & Route Algorithm (RoRA) – Disentangles the three voter domains

– Reduces the number of SPF (bits affecting several resources)

– Besides giving additional fault tolerance to (X)TMR designs, RoRA is applicable also to non- or partial-TMR designs


• Ukube

– Use of STAR

– Use of FT-UNSHADES

– Potential use of FLIPPER


• UKube is a Nanosatelite

– Janus payload • The FPGA has a design without

mitigation (the goal is to get events, not to mitigate them)

– FPGA: XQR4VSX55 • UMC 90nm copper

• CF1140 ceramic flip-chip

• 55296 Logic Cells

• 5760 Kb BRAM

• 8 DCMs


• Goal:

– SEU rates calculation (i.e. Radiation hardness quantification)

– Steps:

• (Step A) Device rate calculation – From Radiation Data of Architectural Elements, the number

of architectural elements and the Orbit Data

• (Step B) Design-dependent (i.e. application) rate calculation

– During the Design Phase, detailed information from P&R of the design in the FPGA



Simulation

CREME96

Radiation Data Orbit, Env Data

Device SEE rates

Design Specifications, Constrains

Synthesis

P&R STAR

FTUNSHADES Flow

Sensitive Cfg Memory

Sensitive user FFs, BRAM

Design Dependent Rates

Rad Effects on SRAM FPGA designs| Sotiris Athanasiou | ESTEC,NL| Data doc | Presentation| Pag. 58

Step A Step B

STEP A, Radiation Data:

• SEU:

– Configuration Memory

– Block RAM

– Flip Flops

• SEFI

– Power-on-Reset

– Select Map

– Global Signal

• Radiation testing to extract these data


VIRTEX-4QV STATIC SEU CHARACTERIZATION SUMMARY,

Gregory Allen Jet Propulsion Laboratory Pasadena, California Gary Swift

and Carl Carmichael Xilinx, Inc. San Jose, California


Rad Effects on SRAM FPGA designs| Sotiris Athanasiou | ESTEC,NL| Data doc | Presentation| Pag. 60

STAR Discovery Results -------------------------------------------------------------------------------

Total Sensitive Bits: 892060 ------------------------------------------------------------------------------- Bit Type Programmed : 497104 Not Programmed : 394956 ------------------------------------------------------------------------------- Resource Bits LUT : 439552 MUX : 224688 CLB Config : 14122 ------------------------------------------------------------------------------- ALONE PIP : 0 OPEN PIP : 57552 SHORT PIP : 5995 INTRASHORT PIP : 152 ANTENNA PIP : 149999 TOTAL PIP : 213698 ------------------------------------------------------------------------------- 1 Intrashort : 152 1 Short : 5995 1 Antenna : 149999 1 Open : 57552 -------------------------------------------------------------------------------

Reads Design after mapping

STAR reads .xdl netlist (ncd2xdl command) inst "G3[6].wide_larger_shift/G1[10].larger_shift/G1[15].large_shift/q<1>" "SLICEL",placed

CLB_X13Y76 SLICE_X18Y153 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF DXMUX::X DYMUX::Y F:G3[6].wide_larger_shift/G1[10].larger_shift/G1[15].large_shift/Mxor_q_1_xor0000_Result1:#LUT:D=(A2@A1) F5USED::#OFF FFX:G3[6].wide_larger_shift/G1[10].larger_shift/G1[15].large_shift/q_1:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:G3[6].wide_larger_shift/G1[10].larger_shift/G1[15].large_shift/q_0:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:G3[6].wide_larger_shift/G1[10].larger_shift/G1[15].large_shift/Mxor_q_0_xor0000_Result1:#LUT:D=(A2@A4) GYMUX::#OFF REVUSED::#OFF SRINV::SR_B SYNC_ATTR::ASYNC XBUSED::#OFF XMUXUSED::#OFF XUSED::#OFF YBUSED::#OFF YMUXUSED::#OFF YUSED::#OFF " ;

Report of Violations: Output is number of cfg memory sensitive bits

Total TMR Failure: 0 ------------------------------------------------------------------------------- | Multiple Open | Short | TMR Failure | 0| 0| Warning One Domain | 0| 0| Warning Different Partition | 0| 0| TMR Warning Same Signal | 0| 0| ------------------------------------------------------------------------------- TMR FAILURE Detailed Nets | ------------------------------------------------------------------------------- | Multiple Open | Short | Ground (GND) | 0| 0| Power (VCC) | 0| 0| Clock (CLK) | 0| 0| Reset (RST) | 0| 0| ------------------------------------------------------------------------------- Time to perform the analysis: 959 seconds


STARbitsbit

CR=app

cfgSEU

cfgSEU

BRAMdevice

CR=app BRAM

SEU

BRAMSEU %*

FFsdevice

CR=app FFs

SEU

FFsSEU %*

CRSEU

cfg

bit

CRSEU

BRAM

device

CRSEU

FFs

device

CREME96 SEU rate results for cfg memory

CREME96 SEU rate results for BRAM

CREME96 SEU rate results for FFs


SEUs/dev/day SEFI/dev/day

No power conditioning taken into account.

Device/day Application/day


http://www.bis.gov.uk/ukspaceagency/missions/ukube-pilot-programme

• DRPM: Dynamically Reconfigurable Processing Module

• Radiation testing of ProASIC3 FPGA

• Software Defined Radio


http://www.esa.int/TEC/OBDP/SEMM6K5OJCG_0.html

• A general introduction of ESA has been presented

• FPGAs are widely used in electronic equipment across many different space applications

• Internal architecture of FPGAs has been introduced. Currently, the antifuse-based are predominant in space equipment

• The ECSS-Q-ST-60-02C standard has been introduced and mapped to the engineering FPGA space development flow

• The mitigation techniques and the associated tools have been introduced. Some examples have been presented.


• To all colleagues, specially to: – Agustin Fernandez-Leon

– Boris Glass

– Roland Weigand

– Christian Poivey

– Jorgen Ilstad

– Sotiris Athanasiou

• And former colleagues: – Francisco Tortosa

– Fredrick Sturesson


• To all collaborators, specially to: – Massimo Violante

– Luca Sterpone

– Monica Alderighi

– Fabio Casino

– Miguel A. Aguirre Echanove and all FT-UNSHADES team

• And to all referenced authors


Workshop on Fault Injection &

Fault Tolerance in space FPGAs

(2009)

The first edition of the Workshop

on Fault-Injection and Fault

Tolerance of Reprogrammable

FPGAs took place in ESTEC on

September 11th 2009.

The workshop was a first get-

together of FPGA designers,

groups that have developed and

used these FI/FT tools, and FPGA

vendors.

http://www.esa.int/TEC/Microelectronics/SEMV57KIWZF_0.html


SEFUW: SpacE FPGA Users

Workshop, 1st Edition (2012)

6, 7 November 2012

Exchange highly valuable

information and experience among

FPGA users, CAD vendors and

FPGA vendors.

Presentations will be available

online.

http://www.esa.int/TEC/Microelectronics/SEMFNSDRI7H_0.html

• “ECSS Handbook” on Mitigation

Techniques against Radiation

Effects for ASICs and FPGAs

• GOAL: help system and IC designers to

choose and apply the best mitigation

techniques depending on project

requirements. Practical compendium of

techniques known to date.

• Start: March 2010

• Status: 1st draft finished,

Presented at ESTEC in Dec 2011: http://microelectronics.esa.int/handbook/HB_Radiation_Hardening_2011-12-02.pdf

To be optimised by TEC-EDM experts,

then to enter ECSS review & approval


http://microelectronics.esa.int/handbook/HB_Radiation_Hardening_2011-12-02.pdf






THANK YOU


David Merodio Codinachs

[email protected]

http://www.esa.int/TEC/Microelectronics/

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