debugging uart buses in uart (universal asynchronous … uart... · 2012. 4. 15. · trigger level:...
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TD. All rights reserved. Publication Release:Copyright 2006 Zeroplus technology CO., LCwww.zeroplus.com.tw TEL:+886 2-66202225 FAX:+886 2-66202226
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Debugging UART Buses in Embedded System Designs
UART (Universal Asynchronous Receiver-Transmitter)UART stands for universal asynchronous receiver and transmitter; pronounced “you-art.”, is for any serial port communication. The UART is framing the data byte by setting “Data bits”、”Parity bits”、”Stop and start bits”、”Baud Rate” and “LSB or MSB”.
UART Sampling Received Data
UART Data Bits FrameStart Bit: a bit indicates the start of a byte.Data Bits: numbers of data bits are used in a frame. Eight bits of data is the most common.Parity bit: check the even or add numbers of 1 are received. (Even = true when even number of 1s) Stop bit: a bit indicates the stop of a byte.Baud: sampling bits per second. (9600 is usually applied on serial terminals)LSB: data bits started from left to right direction.MSB: data bits started from right to left direction.
RS-232 is defined in early 1960, the well know data byte frame of UART. It is widely used in PC serial ports and embedded systems for serial communication between two devices over a short distance.
RS-232 ConnectorsThe RS-232 connectors have got two models, 9 pins and 25 pins as the figure below:
RS232 Signals & DTE-to DCE DB-9 connection (Straight cable)
RS-232
12345
12345
6789
DCE(Female)
DTE(Male)
9-Pin D-sub (DE-9, often called DB-9)
123456789
10111213
123456789
10111213
141516171819202122232425
DCE(Female)
DTE(Male)
25-Pin D-sub (DB-25)
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TD. All rights reserved. Publication Release:Copyright 2006 Zeroplus technology CO., LCwww.zeroplus.com.tw TEL:+886 2-66202225 FAX:+886 2-66202226
Best Measure . Best Quality2007/10
Debugging RS-232 Buses By Using Oscilloscope vs. Zeroplus PC based Logic Analyzer
Example:Measure an RS-232 Bus was generate from 8051 micro controlSignal stats: Baud rate :9600 bps Data bit: 8 bit Stop bit: 1 bit Parity Check : Yes
Debugging UART Bus by Using Oscilloscope Debugging UART Bus by Using Zeroplus PC Based Logic Analyzer
1st Step: 1st Step:
Set trigger condition as below:A0: rising edge
Setup conditions of oscilloscope to catch UART signal.
Trigger level: CH2 ring edge.Frequency:
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TD. All rights reserved. Publication Release:Copyright 2006 Zeroplus technology CO., LCwww.zeroplus.com.tw TEL:+886 2-66202225 FAX:+886 2-66202226
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1 1 1 11 0 0 00 10 0 1 1 1 10 100
0 0 0 00 1 1 11 01 1 0 0 0 01 111
Startbit
Paritybit(1bit)
Stopbit(1bit)
Startbit
Data bit
Count data direction from LSB to MSB
90(10) / 16 = 5.......10
104 us
104 us
104 us
104 us
104 us
104 us
104 us
104 us
104 us
104 us
104 us
104 us
104 us
104 us
104 us
104 us
104 us
104 us
104 us
104 us
Step 1.
Step 2.
Step 3.
Step 4.
Step 5. Ceck ASCII List to find out 5A equal to "Z"
invest step1 data
Baud Rate=9600bpsTime to transfer1bit=1/9600=0.0001041=104us
(8bit)
= (0X27) + (1X26) + (0X25) + (1X24) +(1X23) + (0X22) + (1X21) + (0X20)= 90(10)
0 1 0 11 0 1 0 ( 2 )
5A (16)
2nd Step: 2nd Step:
Enlarge screen, and the data can’t be recognized.
Set up UART Bus self-definitions. Parity: none parity,Data Bit = 8Data Direction = MSB -> LSBBaud Rate = 9600Stop bit = 1Sample Rate = 70%
Setup frequency to re-sampling.
Operating time consumed : 2~5 seconds.
3rd Step: 3rd Step:
Re-setup oscilloscope at right sampling to catch UART signal.
Enlarge UART signals caught to view and analysis the signals clearly and easily.
Operating time consumed : 8~10 munutes are consumed to decode an Address & 8 bits data.
Operating time consumed : 20~30 seconds.
Operating time consumed : about 5 seconds.
Decoding UART signal manually.
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TD. All rights reserved. Publication Release:Copyright 2006 Zeroplus technology CO., LCwww.zeroplus.com.tw TEL:+886 2-66202225 FAX:+886 2-66202226
Best Measure . Best Quality2007/10
ConclusionTransfer parallel buses into serial buses are widely applied in embedded systems design, but it is difficult to be diagnosed problems by using tra-ditional oscilloscopes. Zeroplus LAP-A series PC based logic analyzers provide the economical solution with powerful trigger, decode and search capabilities to design engineers solving embedded system design issues with exceptional efficiency.
4th Step: 4th Step:
Only few data of “ address bus & data bus “ could be captured per right sampling implemented.
Shift roll bar to view more data depending on LAP-A series model provided.
Operating time consumed : 5~7 days to decode & debug a project.
Operating time consumed : 2~3 days to debug a project.