design and process development of cmos image sensors with ... · amos fenigstein, assaf lahav,...

CPIX14Workshop on CMOS Active Pixel Sensors for Particle Tracking

Bonn University15‐17 September 2014

Design and process development of CMOS

image sensors with TowerJazz

Dr Renato Turchetta

Rutherford Appleton Laboratory (RAL)Oxfordshire, UK

E-mail: [email protected]

Jamie Crooks, Nicola Guerrini, Iain Sedgwick, Dipayan Das, Bindu

Velagapudi, Ben Marsh, Giulio Villani, Steve McMahon (STFC-RAL)

Amos Fenigstein, Assaf Lahav, Tomer Leitner, Adi Birman

(TowerJazz Semiconductor)

Wai Chan, Keith Taylor (Specialised Imaging)

Mark Brouard, Claire Vallance, Richard Nickerson, Andrei

Nomerostki, JayaJohn John et al. (Oxford University)

… and many others

Acknowledgments2

Deep P-well PImMS: example of a Hyper Active Pixels Sensor (HAPS) Kirana: CCD-in-CMOS for ultra-high speed imaging CMOS sensors for Atlas tracker Conclusion

3 Outline


4 Outline

CMOS Image Sensor for a digital calorimeter at the International Linear Collider Requirements:

Pixel size = 20-60 µmS/N = MIPS detection with a noise hit rate < 10-5 noise ~ 20-30 e- rmsTime stamping with 150 ns resolution (6.7MHz), over 16 bitsLarge area to be covered MAPS sensor …

… but need a HAPS type pixel: HAPS = Hybrid Active Pixel Sensor or Hyper-Active Pixel Sensor

STFC patent on the deep P-well: how to integrate CMOS electronics in a pixel without compromising performance

Which foundry? Start working with Tower Semiconductor in 2006 to develop a

deep P-well module

Introduction5

NMOS

P-Well N-Well P-Well

N+ N+

P-substrate

N+ N+

Diode NMOS

--

- +++

- +P-epitaxial layer

Passivation layers and routing (SiO2 + metal) A few μm

~1 μm

up to a few tens of μm

A few hundred μm

Sensitive volume

6

N-Well

P+ P+

PMOS

Particle detection in CMOS

NMOS

P-Well N-Well P-Well

N+ N+

P-substrate (~100s m thick)

N+ N+

N-Well

P+ P+

Diode NMOS PMOS

Deep P-Well

Standard CMOS with additional deep P-well implant. Quadruple well technology.

100% efficiency and CMOS electronics in the pixel.

Optimise charge collection and readout electronics separately!

7 Deep P‐well

• Gain 136uV/e• Noise 23e-• Power 8.9uW • 150ns “hit” pulse

wired to row logic• Shaped pulses

return to baseline

• 50um pixel• 4 diodes• 160 transistors• 27 unit capacitors• 1 resistor (4Mohm)• Configuration SRAM

• Per Pixel Mask• Comparator trim (6

bits)

DPWNW

M1PO

8 Image Sensor for Calice

TPAC = Tera Pixel Calorimeter

• Amplitude results• With/without deep pwell• Qualitative comparison

• Simulations “GDS”• Measurements “Real”

0

10

20

30

40

50

60

0 10 20 30 40 50

% to

tal s

igna

l

Position in cell (microns)

Profile B; through cell

GDS+DPW

GDS-DPW

Real+DPW

real-DPW

0

10

20

30

40

50

60

0 10 20 30 40 50

% to

tal s

igna

l

Position in cell (microns)

Profile F; through cell

GDS+DPW

GDS-DPW

Real+DPW

real-DPW

F

B

Pixel profiles

9 Measured vs Simulation Results

Charge collection

17μmTiming

measurement(30mV threshold)

TCADSimulation

(Q=90%)

0

50

100

150

200

250

300

350

50 60 70 80 90 100

Tim

e de

lay

(ns)

X Position (microns)

Charge collection time: Measurements vs Simulation

Sim Profile C

Sim Profile B

Measurements

Measured timing includes a fixed laser-fire delay

BC

M

10


11 Outline

It stands for Pixel Imaging Mass Spectrometry, a project developing a fast imaging sensor for use in a next-generation time-of-flight mass spectrometer (TOF-MS) with unique imaging capabilities

Specifications fairly close to the ones of the TPAC sensor

Needs spatial and time resolution

http://pimms.chem.ox.ac.uk

PImMS12

PImMS

PImMS – Pixel Imaging Mass Spectrometry

13

PImMS pixel layout

Over 600

transistors

Modified process

developed with

TowerJazz: deep P-

implant for 100%

fill factor and true

CMOS

14

PImMS1

72 by 72 pixel array

PImMS2

324 by 324 pixel array

PImMS family

70 μm x 70 μm pixel size

Time-code resolution= 12.5 demonstrated

4 event stored in each pixel

12 bit time-code resolution

Analogue readout of intensity information

With a conventional imager, same performance achieved by taking

4,096 frames at 80 million frames per second

15

Perpendicular 1D alignment and Coulomb explosion imaging

Coulomb explosion imaging

Neutron tomography


18 Outline

(Ultra)‐High speed imaging19

Frame rate (fps)

Reco

rd le

ngth

(fra

mes

) The camera resolution

is proportional to the

shaded area

CCD in CMOS technology

CMOS for ease of use and readout speed

CCD for in-pixel storage

Start from Tower 180 nm CIS process with

dual gate oxide: 3nm + 10nm

Optimise process for high-speed, high-

efficiency charge transfer

Developed by STFC with TowerJazz, see SPIE Digital Imaging 2013,

IISW 2013

20

Sensor requirements

Ultra-high speed (>1MHz) with high frame

depth (~200 cells)

High resolution (~Megapixel)

High-speed (~kfps) for continuous readout

10 bit resolution

Flexible trigger (pre/post/center)

35mm format

21

Charge storage

Photodiode

Memory bank- A vertical entry (VEN)

bank with 10 cells- Ten rows of lateral (LAT)

banks, each with 16 cells- A vertical exit (VEX) bank

with 10 cells

VEN

Photodiode

VEX

LAT

N+ Guard ring

Deep P-implant

22

A. Lahav, J. Crooks, B. Marsh, R. Turchetta, A. Fenigstein, “CMOS Image Sensor Pixel with 2D CCD Memory Bank for Ultra High Speed”, ISSW 2013

Diode.

‘W effect’ W1 W2

W1

W2

23

CCD in CMOS

Single poly process

Poly space: 250 nm

3-phase CCD

10nm thick gate oxide

Buried channel under gates

P-implant

24

Kirana pixel

Highly scalable architecture:- Number of memory cells- Number of pixels

- Low power

25

Kirana. Burst mode26

Kirana. Continuous mode27

Performance summary

Parameter Unit ValuePixel pitch (X) um 30Pixel pitch (Y) um 30

Pixel format (X) 924Pixel format (Y) 768Number of pixels 709,632

Frame rate (burst mode) fps 5,000,000Frame rate (continuous mode) fps 1,180

Pixel rate (burst mode) Pixel/sec 1.42 TPixel rate (continuous mode) Pixel/sec 0.84 G

Noise e- rms <10 e- rmsFull well capacity e- 11,700

Camera gain µV/e- 80Dynamic range >1,170

dB 61.4bit 10.2

Fill Factor 11%

Quantum efficiency Without microlens

2.3% (red)2.2% (blue)

28

High resistivity silicon

Microlenses

Stress in steel rod29

Longer video on YouTube: “Ultra high speed imaging of fracture”

Daniel Rittel, Dynamic Fracture Lab.

www.youtube.com/watch?v=ERhvhWogysw

Glass breaking30

5 millions fps31

Pixel rate in Image Sensors

PImMSKirana

32


33 Outline

Rad‐hard sensors34

Goal: to achieve radiation hardness in excess of 100Mrad and 1015 n cm-2

Can we use CMOS Image Sensor technology?

Different types of diodes, several options for starting material, flexibility in MPW running, stitching, …

… but needs fully depleted CMOS and backbias to counteract change in resistivity and trapping

Status35

Work in progress

1st tape out being completed

Different starting material: Resistivity up to 25umHigh resistivity >~ 1kOHm cmP epi on P substrate and P epi on N substrate wafers

Basic TCAD work done on average CMOS conditions

Electric field36

P-epi

N-sub

Deep N-well

P-well

Charge collection. 137

Charge collection. 238

10V backbias and 10um lateral position

15V backbias and 20um lateral position


39 Outline

Start working with TJ 180nm CIS in 2006

Deep P-well implant 100% fill factor and full CMOS in the pixel

Hyper/Hybrid Active Pixel Sensor electronics demonstrated in

the PImMS sensor, currently used for TOF MS

High resistivity wafers

CCD-in-CMOS for ultra-high speed imaging

Rad-hard sensors for Atlas tracker: just started the development

… also Single Photon Avalanche Detectors (SPAD, not shown)

and many other sensors (e.g. Percival presentation, tomorrow)

Conclusions40

The world of CMOS (Hyper)Active Pixel Sensor is

very exciting and offers plenty of opportunities.

Come and join us!

Recruiting designers now: e-mail me ([email protected])

or browse jobs in STFC at www.topcareer.jobs

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design and process development of cmos image sensors with ... · amos fenigstein, assaf lahav,...

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