design consideration of an mmc hvdc system based on 4500 v:4000a emitter turn-off (eto) thyristor

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Design Consideration of an MMC-HVDC System based on 4500V/4000A Emitter Turn-off (ETO) Thyristor Ghazal Falahi, Alex. Q. Huang FREEDM Systems Center/Department of Electrical and Computer Engineering North Carolina State University FREEDM Systems Center Raleigh, NC, 27695, USA Abstract—Excessive power loss is a major concern in high voltage and high power applications and is considered one of the main drawbacks of VSC-HVDC system when compared with traditional HVDC system based on thyristor technology. This is primarily caused by high switching loss associated with switching devices used in the VSC-HVDC. This issue can be largely addressed by using the emerging MMC-HVDC topology, which requires much lower switching frequency than traditional VSC-HVDC. Emitter turn-off thyristor (ETO) is one of the best high power switching devices packed with many advanced features. ETO thyristor based MMC-HVDC system is therefore an extremely attractive choice for ultra-high voltage and high power HVDCs. This paper discusses the operation principle of ETO based MMC-HVDC as well as its design and loss comparison with other solutions. I. INTRODUCTION Losses of MMC-HVDC system are lower than the two-level converter based HVDC systems but they are still higher than the classic thyristor based HVDC systems. Switching losses of conventional converters such as two level converters can be calculated with high accuracy because switching occurs at predictable instants and DC link voltage does not change significantly from cycle to cycle. MMC switching is less predictable and makes the loss calculation more complex. MMC operates with low switching frequencies sometimes as low as the fundamental frequency so switching loss is not a significant portion of losses in this topology. However conduction and switching losses both should be calculated to estimate the accurate system losses. Switching events are typically assumed to be equally distributed over the cycle to make the switching loss calculations easier. Loss is an important concern in high power applications such as HVDC and a small percentage of loss reduction leads into hundreds of kilowatts of power saving. Some publications have reviewed the losses of HVDC systems and proposed different solutions to calculate the losses. There are also some standards that categorize the losses and present some equations for loss calculation. However most of them simplify the loss calculations by averaging the losses over a cycle or present some off-line loss calculation based on analytical equations. This paper proposes using ETO thyristors for MMC-HVDC system to reduce the overall losses and to boost the HVDC system capacity. Since the ETO is proposed to reduce the semiconductor losses in the MMC-HVDC system, it is very important to calculate the losses accurately. Some publications have discussed the loss calculation of MMC and proposed different techniques to calculate the valve losses [1-5]. This paper aims to design an MMC based on the 4500V/4000A ETO for HVDC applications and presents detailed loss calculation for the MMC that uses instantaneous values of gating signals based on the converter operation principles and analytical equations. II. EMITTER TURN-OFF THYRISTOR (ETO) ETO shown in Figure 1 is a MOS-GTO hybrid device, which improves the characteristics of GTO devices to accommodate the needs of high power conversion applications. One of the key advantages over the GTO is that it can be turned off without a snubber at 4kA. The latest version of ETO (Gen-4 ETO) is more intelligent and reliable. Beside the combined advantages of GTO and IGBT, Gen-4 ETO has some unique features such as built in voltage, current and temperature sensors and protection function, control power self-generation to remove external auxiliary power supply for control, and light trigger interface to simplify the connection with external control [6- 7]. All the features of ETO allow reduced cost and simplified design of high power converters, which makes it a good candidate for MMC-HVDC application discussed below. 978-1-4673-7151-3/15/$31.00 ©2015 IEEE 3462

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  • Design Consideration of an MMC-HVDC System based on 4500V/4000A Emitter Turn-off (ETO) Thyristor

    Ghazal Falahi, Alex. Q. Huang FREEDM Systems Center/Department of Electrical and Computer Engineering

    North Carolina State University FREEDM Systems Center Raleigh, NC, 27695, USA

    AbstractExcessive power loss is a major concern in high voltage and high power applications and is considered one of the main drawbacks of VSC-HVDC system when compared with traditional HVDC system based on thyristor technology. This is primarily caused by high switching loss associated with switching devices used in the VSC-HVDC. This issue can be largely addressed by using the emerging MMC-HVDC topology, which requires much lower switching frequency than traditional VSC-HVDC. Emitter turn-off thyristor (ETO) is one of the best high power switching devices packed with many advanced features. ETO thyristor based MMC-HVDC system is therefore an extremely attractive choice for ultra-high voltage and high power HVDCs. This paper discusses the operation principle of ETO based MMC-HVDC as well as its design and loss comparison with other solutions.

    I. INTRODUCTION

    Losses of MMC-HVDC system are lower than the two-level converter based HVDC systems but they are still higher than the classic thyristor based HVDC systems. Switching losses of conventional converters such as two level converters can be calculated with high accuracy because switching occurs at predictable instants and DC link voltage does not change significantly from cycle to cycle. MMC switching is less predictable and makes the loss calculation more complex. MMC operates with low switching frequencies sometimes as low as the fundamental frequency so switching loss is not a significant portion of losses in this topology. However conduction and switching losses both should be calculated to estimate the accurate system losses. Switching events are typically assumed to be equally distributed over the cycle to make the switching loss calculations easier. Loss is an important concern in high power applications such as HVDC and a small percentage of loss reduction leads into hundreds of kilowatts of power saving. Some publications have reviewed the losses of HVDC systems

    and proposed different solutions to calculate the losses. There are also some standards that categorize the losses and present some equations for loss calculation. However most of them simplify the loss calculations by averaging the losses over a cycle or present some off-line loss calculation based on analytical equations. This paper proposes using ETO thyristors for MMC-HVDC system to reduce the overall losses and to boost the HVDC system capacity. Since the ETO is proposed to reduce the semiconductor losses in the MMC-HVDC system, it is very important to calculate the losses accurately. Some publications have discussed the loss calculation of MMC and proposed different techniques to calculate the valve losses [1-5]. This paper aims to design an MMC based on the 4500V/4000A ETO for HVDC applications and presents detailed loss calculation for the MMC that uses instantaneous values of gating signals based on the converter operation principles and analytical equations.

    II. EMITTER TURN-OFF THYRISTOR (ETO) ETO shown in Figure 1 is a MOS-GTO hybrid device, which improves the characteristics of GTO devices to accommodate the needs of high power conversion applications. One of the key advantages over the GTO is that it can be turned off without a snubber at 4kA. The latest version of ETO (Gen-4 ETO) is more intelligent and reliable. Beside the combined advantages of GTO and IGBT, Gen-4 ETO has some unique features such as built in voltage, current and temperature sensors and protection function, control power self-generation to remove external auxiliary power supply for control, and light trigger interface to simplify the connection with external control [6-7]. All the features of ETO allow reduced cost and simplified design of high power converters, which makes it a good candidate for MMC-HVDC application discussed below.

    978-1-4673-7151-3/15/$31.00 2015 IEEE 3462

  • Figure 1. Principal circuit and picture of Gen-4 ET

    III. ETO BASED MMC STRUCTURE APRINCIPAL

    The equivalent circuit of a three-phase MMthe ETO based sub-module is shown in based sub-module is basically a half bridgeETO switches and a clamp circuit. Equatioarm voltage of MMC based of sub-moduand their switching states.

    The arm current in MMC is derived from DC current and the AC current. Also the rearm voltage is derived from (3) assumodulation [2, 3].

    Figure 2. Modular multilevel converter, ETO

    Where is the current phase angle. Switchmodule depends by the arm current and

    TO 4.5KV/4KA

    AND OPERATION

    MC converter and Figure 2. ETO

    e converter using on (1) defines the ules DC voltages

    (1)

    (2) based on the ference value for

    uming a cosine

    (2)

    (3)

    sub-modules hing state of sub-d reference arm

    voltage. The upper arm current dpoints of zero crossing in one cyclet3. When the arm current is positivediode D2 can conduct and when thet2 to t1, switch S2 or diode D1 can convoltage will define the active deviceIf arm current is positive and refereis decreasing, t3 to 0, sub-module conducts and when the reference ar0 to t2, sub-module is inserted Similarly when the arm current is inserted when the reference arm vo(t1+t2)/2, so diode D1 conducts and when the reference arm voltage is dso switch S2 conducts. The sconduction intervals change fomodulation index (m) and angle ( ).

    IV. MODULATION AND CBALANCING

    A modified nearest level modulatioto operate ETO based MMC. To iof fundamental frequency basecalculation of switching angels hmethod. The algorithm inputs thwaveform from the system contrswitching angels such that the gMMC is very close to the reference Figure 3 shows a zoomed in pwaveform and discrete steps genmodules. Real-time modulation hasis the generation of the switching anis the capacitor voltage balancincapacitor voltage balancing, indivare measured at each controller ticontroller. The measured voltagesswitching instant ( i) and the swiwith respect to the index of sorted c

    Sub-modules are inserted or bswitching state of two switching devTwo switches are complementary aeach device depends on the directioreference modulation waveform. diode (S1 or D1) conduct the s

    defined by (2) has three e referred to as t1, t2, and , t3 to t2, only switch S1 or

    e arm current is negative, nduct. The reference arm e in each interval. ence value of arm voltage is bypassed so diode D2 rm voltage is increasing, so switch S1 conducts. negative, sub-module is

    oltage is increasing, t2 to sub-module is bypassed

    decreasing, (t1+t2)/2 to t1, switching instants and or different values of

    (4)

    CAPACITOR VOLTAGE G

    n (NLM) method is used mprove the performance ed NLM, a real-time has been added to the

    he reference modulation oller and calculates the generated waveform by waveform.

    ortion of the reference nerated by MMC sub-s two parts; the first part ngels and the second part

    ng. In order to achieve vidual capacitor voltages ime-step and sent to the are sorted and at each tching decision is made

    capacitor voltage matrix.

    ypassed based on the vices in each half bridge.

    and the switching state of on of the arm current and When upper switch or

    sub-module capacitor is

    3463

  • inserted in the arm and conduction of the lor D2) results in bypassing the sub-module c

    The sub-modules are in charging or daccording to the direction of current flowsub-module. When the upper device is conmodule capacitor is inserted into the arm Figure 4 when D1 is conducting the sub-mwill be in charging state. The sub-moduldischarge when S1 conducts. Thus to acwhen the sub-modules are in charging stalowest capacitor voltages have to turn discharging condition the capacitors withhave higher priority.

    Figure 5 summarizes the operation of the prmodulation technique. In the proposed coremaining sub-modules are considered at eto reduce the equivalent switching frequexcessive switching losses. The circulatingalso added to the modulation reference sigcapacitor balancing faster. Number of active sub-modules is calcuaverage measured capacitor voltages instconstant value to increase accuracy.

    Figure 3. Output and reference voltage of the propo

    Figure 4. Switching state of sub-modu

    D1

    D2

    S1

    S2

    ipaVc

    S1

    S2

    Vc

    D1

    D2

    S1

    S2

    ipaVc

    S1

    S2

    Vc

    ower devices (S2 capacitor.

    discharging state wing through the nducting the sub-and as shown in

    module capacitor le capacitor will chieve balancing ate the ones with

    on first and in highest voltage

    roposed real-time onfiguration only each discrete step uency and avoid g current error is gnal to make the

    ulated by using tead of using a

    osed NLM method

    ules

    Figure 5. Real-time NLM with capa

    V. DETAILED LOSS

    The main part of power device lMMC-HVDC system is conductiolosses. The conduction loss mainlydiode conduction losses. Accordiresults of Gen-4 ETO, the turn-offtemperature under 2.5kV dc-bus vowhich yields the turn-off energy inAmpere. The ETO on-state voltagtemperature is expressed by (6) whein Volts and current I is in Ampelosses are given by (7).

    Conduction losses of four devices calculated during four intervals dexplained before. The magnitude ochange with time hence the accuratand modulation is required to closses precisely. During each inconduction loss of the active deviceFirst the conduction interval isintervals. Number of small intervdefined by changes in the number interval by (8).

    D1

    D2

    ipa

    D1

    D2

    ipa

    Vdc1 Vdc2 . . . Vdcn

    Sorting

    Vdcmax . . . Vdcmin

    + (Index)

    1

    2 . . .

    n

    + Nactive (number of active SMs)

    NLM criteria

    Varm,ref 1Vdc 2Vdc . . . nVdc ( Discrete Voltage Steps)

    Vdcmin . . . Vdcmax

    + (Index)

    citor voltage balancing

    CALCULATIONS

    losses in an ETO based on losses and switching y includes the ETO and ng to experimental test

    ff loss at 125C junction oltage is expressed by (5) n Joule and current is in ge under 125C junction ere the on-state voltage is eres [7]. The conduction

    (5) (6)

    (7)

    in each sub-module are defined in Figure 6 and of current and modulation te information of current

    calculate the conduction nterval in Figure 6 the e is calculated as follows: s divided into smaller vals or discrete levels is of active devices in each

    S1 S2 . . . Sn (Switching signals)

    x

    )

    3464

  • Where tup is the upper time limit of the interlower time limit. The conduction loss is thsmall intervals and added together for the ncells in to find the total conduction loss oMMC arm. Losses are calculated usinmodulation for MMC. The arms of MMCthe losses are calculated for one arm and Reduced switching frequency nearest le(NLM) is used in this design, which is basethe required number of the sub-modulesoutput waveform that follows the referewaveform.

    As mentioned before, the sub-modules are oonce during each switching cycle and switceach discrete step is made by considerinsub-modules to avoid excessive switchiswitching loss is calculated for ETO and the four regions with respect to switchindevices. To calculate the number of deviceor off during each interval nactive must be cbeginning and end of the time interval.equation as an example shows the numbduring (t3, 0) time interval.

    Where nSW is the total number of devices toff that occur during each region assuminstatus of only one of the sub-modules chadiscrete step. Similarly, nSW and switchcalculated for D2, S2, S1 during the time int(t1+t2)/2) and ((t1+t2)/2, t1).

    Adding the calculated losses for four reswitching losses for reduced switching modulation used in this design. The devicincludes turn-on loss and turn-off loss. Duedi/dt inductor, ETO turn-on loss is smneglected. Therefore the switching losses pETO and diode turn-off losses.

    Figure 8 shows the overall diagram Reference modulation waveform generacontroller is the input to capacitor voltagloss calculation systems. Loss calculationthe individual device losses for all sub-modu

    (8)

    rval and tlow is the hen calculated for number of active

    of each device in ng nearest level C are identical so

    multiplied by 6. evel modulation ed on calculating s to generate an ence modulation

    only switched on ching decision at

    ng the remaining ing losses. The diode in each of ng status of the es that switch on calculated at the . The following ber of switching

    (9)

    that switch on or ng that switching ange during each hing losses are tervals (0, t2), (t2,

    egions results in frequency NLM

    ce switching loss e to the use of the

    mall and can be primarily include

    (10)

    of the system. ated by system ge balancing and n system outputs ules.

    Figure. 6 Proposed loss estimation metho

    switching state

    Accurate individual device losses ausing the proposed loss calculatioshows the power losses of S1, D1, module in the upper arm for morexample and the same waveforms cdevices in other sub-modules.technique swaps sub-modules and losses amongst sub-modules. Table 1 summarizes the device and500MW ETO based MMC-HVDoperating conditions. The DC linksystem is 320KV and there are 1arm of the converter. Conventionahave around 1% semiconductor lototal semiconductor loss of the pro16% less than conventional MMC-H

    Figure 7. Proposed modulation and re

    od, arm voltage, current and es

    are calculated and plotted on technique. Figures 8 S2 and D2 the first sub-

    e than 100 cycles as an can be plotted for all four . Capacitor balancing

    will eventually balance

    d sub-module losses of a DC system for different k voltage of the modeled 28 sub-modules in each

    al MMC-HVDC systems sses per station [1]. The oposed system is around HVDC systems.

    eal time loss calculation

    3465

  • Figure 8. Real time loss of the four devices in the first sub-module

    I. THERMAL ANALYSIS

    Each sub-module of MMC has two ETOs and two diodes and the losses of the switching components need to be removed out by a cooling system. The heat pipe based air cooling system can be used to remove the heat from ETO stacks. Use of heat pipe helps with cost, reliability and comact structure and allows us to avoid the drawbacks of conventional water cooling systems such as the need of good electrical isolation. A basic pricipal in optimal design of ETO stacks is to use the stray inductance to limit the turn on current.

    Figure 10 shows heat pipe based cooling and ETO based MMC sub-module structure. The cooling system of half-bridge MMC sub-module is first designed for the MMC-HVDC system at 500MW operation and the junction

    temperatures are still much lower than 100C.

    Table II shows the individual device losses for designed 500MW operation. Since the junction temperature of all sub-module devices is well below 125C the ETO based system is capable to operate at higher powers. The possibility of 1000MW operation is examined and losses are calculated, table III shows the junction temperature of four devices. Device temperatures are still lower than 125C which indicates that the proposed system has potential to reach 1000MW which is much higher than IGBT based MMC-HVDC systems.

    TABLE I. LOSS CALCULATION FOR A 500MW ETO BASED MMC-HVDC SYSTEM

    Figure 9. Average device losses over 200 cycles

    Figure 10. Heat pipe based cooling (left), MMC sub-module (right)

    0 10 20 30 40 50 60 70 80 90 100 1100

    50

    100

    150

    200

    250

    300

    Number of cycles (N)

    Diod

    e D1 (

    SM1)

    loss

    es (W

    att)

    0 10 20 30 40 50 60 70 80 90 100 1100

    200

    400

    600

    800

    Number of cycles (N)

    Switc

    h S1

    (SM

    1) lo

    sses

    (Wat

    t)

    0 10 20 30 40 50 60 70 80 90 100 1100

    200

    400

    600

    800

    1000

    1200

    Number of cycle (N)

    Diod

    e D2

    (SM

    1) lo

    sses

    (Wat

    t)

    0 10 20 30 40 50 60 70 80 90 100 1100

    50

    100

    150

    200

    250

    300

    Number of cycles (N)

    Switc

    h S2 (

    SM1)

    losse

    s (W

    att)

    Device Loss (PF= -0.95) Loss (PF= 1) Loss(PF=+0.95)

    D1 155 132 181

    D2 310 705 632

    S2 446 167 162

    S1 816 596 719

    Each sub-module losses 1727 1600 1694

    Each sub-module losses [1] design with IGBT

    (400 MW, Vdc=200KV, nsm=200) 2330 1850 2167

    0

    500

    1000

    1500

    2000

    D1 D2 S2 S1 SM loss

    PF=-0.95

    PF=+0.95

    PF=1

    c

    D1c

    c

    c

    S1

    S2

    D2

    ETO

    Heat pipe

    Antiparallel diode

    cc

    cc

    S1

    S2

    D1

    D2

    3466

  • TABLE II. DEVICE TEMPERATURE FOR DESIGNED 500MW MMC-HVDC

    Device Junction temperature (C)D

    2 61.9

    S2 67.4

    S1 81.6

    D1 54.4

    TABLE III. DEVICE TEMPERATURE FOR A POTENTIAL 1000MW MMC-HVDC

    Device Junction temperature (C)D

    2 82.9

    S2 90.6

    S1 109.2

    D1 70.1

    II. CONCLUSION

    This paper proposed a new ETO based MMC-HVDC system and discussed modulation, capacitor voltage balancing and detailed valve loss calculation based on reduced switching frequency NLM for the proposed system. The MMC-HVDC system loss is more than 1% per station [1], yet proposed MMC-HVDC system based on the 4500V/4000A ETO thyristor has higher capacity and more than 16% lower losses per station compared to IGBT based MMC-HVDC. Besides, the system has the controllability of the VSC based HVDC systems. Thermal analysis shows that power capacity of ETO based MMC-HVDC can reach higher than 1000MW which is more than power capacity of conventional MMC-HVDC systems.

    REFERENCES

    [1] Jones, P.S. and C.C. Davidson. Calculation of power losses for MMC-based VSC HVDC stations. in Power Electronics and Applications (EPE), 2013 15th European Conference on. 2013. IEEE.

    [2] Rohner, S., et al., Modulation, losses, and semiconductor requirements of modular multilevel converters. Industrial Electronics, IEEE Transactions on, 2010. 57(8): p. 2633-2642.

    [3] Zhang, Z., Z. Xu, and Y. Xue, Valve Losses Evaluation Based on Piecewise Analytical Method for MMCHVDC Links. 2014.

    [4] Oates, C. and C. Davidson. A comparison of two methods of estimating losses in the Modular Multi-Level Converter. in Power Electronics and Applications (EPE 2011), Proceedings of the 2011-14th European Conference on. 2011. IEEE.

    [5] Yang, L., C. Zhao, and X. Yang. Loss calculation method of modular multilevel HVDC converters. in Electrical Power and Energy Conference (EPEC), 2011 IEEE. 2011. IEEE.

    [6] Li, Y., A.Q. Huang, and K. Motto, Experimental and numerical study of the emitter turn-off thyristor (ETO). Power Electronics, IEEE Transactions on, 2000. 15(3): p. 561-574.

    [7] Li, J., et al. ETO light multilevel converters for large electric vehicle and hybrid electric vehicle drives. in Vehicle Power and Propulsion Conference, 2009. VPPC'09. IEEE. 2009. IEEE.

    [8] TEWARI, K., Investigation of High Temperature Operation Emitter Turn Off Thyristor (ETO) and Electro Thermal Design of Heatpipe Based High Power Voltage Source Converter Using ETO, in ECE North Carolina State: 2006.

    [9] Etemadrezaei, M., et al. "Precise calculation and optimization of rotor eddy current losses in high speed permanent magnet machine." Electrical Machines (ICEM), 2012 XXth International Conference on. IEEE, 2012.

    [10] Falahi, Ghazal. PhD Dissertation, "Design, Modeling and Control of Modular Multilevel Converter based HVDC Systems." North Carolina State University, (2014).

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