design of 8-bit shift register using power pc-style flip flop · 445 b. gowthami et al.,...

ADVANCES in NATURAL and APPLIED SCIENCES

ISSN: 1995-0772 Published BYAENSI Publication EISSN: 1998-1090 http://www.aensiweb.com/ANAS

2017 June 11(8): pages 440-448 Open Access Journal

ToCite ThisArticle: B. Gowthami, C. Maheswari, V. Navya., Design of 8-Bit Shift Register using Power Pc-Style Flip Flop. Advances in Natural and Applied Sciences. 11(8); Pages: 440-448

Design of 8-Bit Shift Register using Power Pc-Style Flip Flop

1B. Gowthami, 2C. Maheswari, 3V. Navya

1Assistant professor, Sree vidyanikethan engineering college, Ttirupathi, A.P, Iindia. 2Assistant professor, Sree vidyanikethan engineering college, Ttirupathi, A.P, Iindia. 3Assistant professor, Sree vidyanikethan engineering college, Ttirupathi, A.P, Iindia. Received 28 March 2017; Accepted 7 June 2017; Available online 12 June 2017

Address For Correspondence: B.Gowthami, Assistant professor, Sree vidyanikethan engineering college, ECE Department, Ttirupathi, A.P,Iindia, phone:918897071908; E-mail: [email protected]

Copyright © 2017 by authors and American-Eurasian Network for ScientificInformation (AENSI Publication). This work is licensed under the Creative Commons Attribution International License (CC BY). http://creativecommons.org/licenses/by/4.0/

ABSTRACT The use of multiple non-overlap delayed pulsed clock signals solves the timing problem when compared to conventional clocking scheme i.e., single pulsed clock signal. Also the pulsed latches prove to be area efficient and power efficient. Further the area and power consumption in flipflops can be reduced by using pulsed latches. The 8-bit shift register is designed by using small number of the pulsed clock signals by grouping the latches to several sub shift registers and with additional temporary storage latches. The Designs are coded in SPICE and simulated using HSPICE Tools. The Power Delay Product of pulsed latch is found to be improved by 67.45% in pulsed latch and master slave flip flop. The Power Delay Product of SSASPL is found to be improved by 85.6% than PPCFF. The Power Delay Product is found to be improved by 36.5% from design1, 39.74% and 41.19% from design3 respectively. KEYWORDS: Flip-Flops, Pulsed Clock, Pulsed Latches, Shift registers, HSPICE, SSASPL, PPCFF.

INTRODUCTION

The modern digital systems impose constraints low power, less area occupation and high speed circuits. The

design of clock plays a major role in communication system. The pulsed clock signal is used to increase the data

rate of the system designed.

In literature, the design of various Latches and Flip-Flops is performed. The basic difference between the

latch and flip-flop lies at the enable signal and the clock signal. The enable signal is used to trigger the latch that

is level sensitive. While the clock signal is used to trigger the Flip-Flop, which is edge triggered. The edge

triggering can be done by using rising edge or falling edge. But most practical circuits use positive or rising

edge triggered flip-flops.

The basic design of the flip-flop is shown in fig.1[1], where two latches are used to design the flip-flop. The

output signal is given to a delay circuit for generation of pulsed clock signal to derive the short width pulses.

Fig. 1: Design of Flip-flop using two latches and for the design of pulsed latch.

441 B. Gowthami et al., 2017/Advances in Natural and Applied Sciences. 11(8) June 2017, Pages: 440-448

Fig. 2: Design model for generic Pulsed latch and Multi-bit pulsed latch.

The fig.2 shows the design of generic and multi-bit pulsed latch. From the generic pulsed latch structure,

the pulses can be easily distorted since the pulse generator and Latches are placed apart. In multi-bit pulsed

latches, the pulse generator and latches are placed and hard-wired together in a compact and symmetric form.

Also the pulse distortion and clock skew can be well controlled.

Fig. 3: (a) The existing design of Pulsed clock signal. (b) The existing pulsed flip-flop design

In fig.3.(a), when the applied clock signal, CLK is 0, the PMOS transistor P1 and the NMOS transistor N1

turn on which causes pulse clock PCK to be 0. Also the pull-down network is enabled after N2 is turned on at

the rising edge of CLK, and hence the PCK signal at the output is driven high. Both the transistors N3 and P2

are subsequently turned on, which drives the PCK signal back to 0.

Hence, the pulse width is determined by the inverter chain delay. And if the clock gating, driven by signal

EN (enable) is embedded in the circuit, the enable signal EN is not allowed to change while the PCK signal is 1,

which occurs briefly, and can be realized by a simple transmission gate. This signal is utilized in the fig.3 (b) for

the implementation of pulsed Flip-Flop.

The 8-bit shift register uses the D-Flip Flop driven a clock pulse signal. The shift registers are used in

applications like digital filters, communication systems and image processing ICs. The Design of Flip Flop

plays a crucial role in the storage buffers. The proven ways used to design a memory element are shown in fig.4.

Fig. 4: (a) Master Slave Flip Flop (b) Pulsed Latch

In fig.4.(a), the master slave flip flop is designed by using two latches driven by synchronous clock. In

fig.4.(b), the pulsed latch is driven by a pulse generation circuit as shown in fig.5.

Fig. 5: Delayed Pulsed Clock Generator


The fig.5, the delayed pulsed clock generator is designed by using CMOS technology with the standard

W/L ratio as 3:1. For delayed pulsed clock generator includes a delay element, two inverters and a AND gate.

latch and Flip-Flop:

This paper utilizes a the Power PC Style Flip Flop(PPCFF) and static Differential Sense Amplifier Shared

Pulse Latch (SSASPL). The novel SSASPL with 9 transistors 6] is adapted to the SSASPL with 7 transistors as

shown in Fig.3 by removing an inverter to generate the complementary data input (Db) from the data input (D).

The SSASPL uses the minimum number of transistors (7 transistors) and it consumes the lowest clock power

because it has a single transistor driven by the pulsed clock signal. Three NMOS transistors are used to update the

data which holds the data with four transistors in two cross-coupled inverters [11]. Two differential data inputs

(D and Db) and a pulsed clock signal is required. Data is updated when the pulsed clock signal is in high position

According to the input data (D and Db) the node Q or Qb is pulled down to ground. The pull-up current of the

PMOS transistors is lesser than the Pull-down current of the NMOS transistors in the inverters.

Fig. 6: Static Differential Sense Amplifier Shared Pulse Latch (SSASPL)

Fig. 7: Power Pc-Style Flip Flop (PPCFF)

The PPCFF uses 16 smallest number of transistors which are among the flip-flops [10]-[15]. The schematic

of the PPCFF, shows in Fig.4. Which is a master-slave flip-flop composed of two latches. The PPCFF contains 16

transistors, in addition 8 transistors are used to driven clock signals. PPCFF uses the minimum size of transistors

for a fair comparision.

shift register design:

For small area and low power consumption, shift register uses pulsed latch as an striking solution [8]. Due

to the timing problem, pulsed latch cannot be used in shift registers as shown in Fig.8. The shift register in Fig

8(a) contains several latches and a pulsed clock signal(CLK pulse). The timing problem in the shift register is

shown in the operation waveforms in Fig 8(b). The input signal of the first latch (IN) is constant due to this the

output signal of the first latch(Q1) changes correctly [12]. The input signal (Q1) varies during the clock pulse

width due to this reason the second latch has an uncertain output signal(Q2).

Fig. 8: Shift register with latches and a pulsed clock signal. (a) Schematic. (b) Waveforms.


To minimize the timing problem, the best solution is to add delay circuits between latches, as shown in Fig.

9(a). latch’s output signal is delayed and reaches next latch after the clock pulse. During the clock pulse width,

the output signals of the first and second latches (Q1 and Q2) changes. Due to this effect, the input signals of all

latches during clock pulse remains constant and also no timing problem occurs between the latches. Even-though,

the delay circuits cause large area and power overheads [16].

Fig. 9: Shift register with latches, delay circuits, and a pulsed clock signal. (a) Schematic. (b) Waveforms.

The possible solution is to use multiple non-overlap delayed pulsed clock signals, as shown in Fig 10(a).

when a pulsed clock signal goes through delay circuits, the delayed pulsed clock signals are generated. Every

latch utilizes a pulsed clock signal which is delayed from the pulsed clock signal used in the next latch [9]. So,

every latch updates the information after its next latch updates the information. End result, each latch has a

constant input during its clock pulse and there is no timing problem arises between latches [13]. Many delay

circuits are also required for this solution [14]. The respective waveforms are as shown in fig. 10(b)

Fig. 10: Shift register with latches and delayed pulsed clock signals. (a) Schematic. (b) Waveforms.

The proposed shift register is an example which is shown in Fig. 11(a). To reduce the number of delayed

pulsed clock signals, the proposed shift register is divided into sub M shift registers. Five latches are present in

the 4 BIT Shift register with five non-overlap delayed pulsed clock signals (CLK_pulse<1:4> and

CLK_pulse<T>) [10]. Four latches store 4-bit data i.e.,(Q1-Q4),in the 4-bit sub shift register #1, and the 1 bit

temporary data (T1) stores in the last latch [15]. The resustored in the first latch(Q5) of the 4 bit sub shift

register #2. Fig 11(b) shows the proposed shift register with operation waveforms.


Fig. 11: Proposed Shift Register (a) Schematic (b) Waveforms

RESULTS AND DISCUSSION

All the corresponding designs of Flip-Flops, latches and Shift registers are designed in SPICE and verified

in Synopsys HSPICE Tools. Avan waves is used to visualize the simulated outputs. The designs are compared

for power, delay and power Delay Product. The delayed pulsed clock generator produced a overall delay of

0.1952nS with a overall power consumption of 75.566mW.

Fig. 12: Simulation Result of Master Slave Flip Flop


Fig. 13: Simulation Result of Pulsed Latch

The simulated waveforms are shown in figs. 12 and 13 for the Master Slave Flip Flop and Pulsed Latch. As

per the requirement the signals are generated. In fig.12, the master-slave Flip Flop results in the output with

minimum delay even though two latches are used to develop it. While the clock is rising, with the help of latch,

the pulsed clock is generated as shown in fig.13. When compared to Master Slave Flip Flop, the pulsed latch has

better shape of waveform and performance.

The Table I shows the comparison result of Master Slave Flip Flop and Pulsed Latch. The delay is

decreased by 47.4% in Pulsed Latch. The power consumption is improved by 6.9%. The Power Delay Product

of pulsed latch is found to be improved by 67.45% in pulsed latch when compared with master slave flip flop.

Also the area is improved by 42.1% in pulsed latch than in Master Slave D-Flip Flop.

Table I: Comparison Of Master Slave Flip Flop And Pulsed Latch

Latch

Parameters Measured

Delay (nS) Power Consumption (mW) Power Delay

Product Area (µm2)

Master Slave D-FlipFlop 8.1422 2.4662 34.8559 76

Pulsed latch 4.2809 2.6495 11.3422 44

The simulated waveforms are shown in figs. 13 and 14 for the SSASPL and PPCFF. The output of the

SSAPL flip-Flop is degraded as the logic levels are not clearly distinguishable. But in PPCFF, the output has

minimum delay with good shape of waveform and desired performance.

Fig. 14: Simulation Result of SSASPL

Fig. 15: Simulation Result of PPCFF


The Table II shows the comparison result of SSASPL and PPCFF. Even though the delay is increased and

the power consumption is decreased, the Power Delay Product of SSASPL is found to be improved by 85.6%

than PPCFF. As Trade-off exists for area and figure of merit, the increase in area is acceptable.

Table II: Comparison of SSASPL and PPCFF Memory Elements

Latch

Parameters Measured

Delay (nS) Power Consumption (mW) Power Delay Product (pW-S)

Area (µm2)

SSASPL 0.17703 20.441 3.6186 11

PPCFF 3.6596 0.14236 0.5209 32

The simulated waveforms are shown in figs. 16, 17, 18 and 19 for 8-bit Shift Registers for the circuits in figs.

8,9,10 and 11 respectively. Among these the output is in good shape and clear for logic levels for proposed 8-bit

shift register. The Table III shows the comparison result of various combinations of 8-bit shift register

Fig. 16: Simulation Result of Shift register with latches and a pulsed clock signal

Fig. 17: Simulation Result of Shift Register with latches, delay circuits and a pulsed clock signal

Fig. 18: Simulation Result of Shift Register with latches and Delayed pulsed clock signals


Fig. 19: Simulation Result of Proposed Shift Register

The Table.III shows the comparison results of the all combinations of 8-bit shift registers. The Power Delay

Product is found to be improved by 36.5% from design1, 39.74% and 41.19% from design3 respectively. Due to

Trade-off between the Area and figure of merit, the increase in area occupied by transistors is acceptable and

further if compensation is required scaling of transistor size can be done.

Table III: Comparison Of 8-Bit Shift Register Combinations

Latch

Parameters Measured

Delay (nS) Power Consumption

(mW)

Power Delay

Product Area (µm2)

Shift register with latches and a pulsed clock signal 0.10007 2.6531 0.2655 116

Shift Register with latches, delay circuits and a

pulsed clock signal 0.10602 2.6392 0.2798 132

Shift Register with latches and Delayed pulsed

clock signals 0.10743 2.6689 0.2867 132

Proposed Shift register 0.51950 0.32451 0.16858 360

Conclusion:

The shift registers prove to be the essential components of Digital Filters, image processing ICs etc. The

timing problem in the conventional shift registers is overcome by multiple non-overlap delayed pulsed clock

signals. The pulsed latches used in the design are area and power efficient. The 8-bit shift register is designed by

grouping the latches to several sub shift registers and with additional temporary storage latches. The Designs are

developed in SPICE and verified in Synopsys HSPICE Tools. The Power Delay Product of pulsed latch is found

to be improved by 67.45% in pulsed latch and master slave flip flop. The Power Delay Product of SSASPL is

found to be improved by 85.6% than PPCFF. The Power Delay Product is found to be improved by 36.5% from

design1, 39.74% and 41.19% from design3 respectively.

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design of 8-bit shift register using power pc-style flip flop · 445 b. gowthami et al.,...

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