development of a system-on-chip extensible network processor and debugging using identify

Extensible Networking Platform 1 1 - Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking

Development of a System-On-Chip Extensible Network Processor and debugging using Identify

John W. Lockwood and Chris Zuver

Applied Research Laboratory : Reconfigurable Network Group

http://www.arl.wustl.edu/projects/fpx/reconfig.htm

[email protected]@arl.wustl.edu


FPX Hardware Platform

PR

OM

Cache

Program

FlowB

uffer

Route

Filter

ExtensibleM

odules

Layered Protocol Wrappers

Switch

SD

RA

MS

RA

M

SD

RA

MS

RA

M

Config

NID (FPGA)

Memory

Network Interface

RAD (FPGA)

FPX Block Diagram FPX Photo

PR

OM

Cache

ProgramC

acheP

rogram

FlowB

uffer

Route

Filter

ExtensibleM

odules


Switch

SD

RA

MS

RA

M

SD

RA

MS

RA

M

Config

NID (FPGA)

Memory

Network Interface

RAD (FPGA)

FPX Block Diagram FPX Photo


FPX Hardware in WUGS-20 Switch


FPX Hardware in GVS-1000 Chassis


System-On-Chip Firewall


Interfaces to Off-Chip Memories

PayloadScanner

TCAMFilter

FlowBuffer

Queue Manager

Datainputfrom

GigabitEthernet

or SONET

Line Card

Free List Manager

SRAM 1Controller

SDRAM 1Controller

PacketScheduler

Dataoutput

To switch,Gigabit

Ethernet,or

SONETLine Card

Payload Match Bits Flow ID

ExtensibleModule(s)

SDRAM 2Controller

Xilinx XCV2000E FPGA


Interfaces to Off-Chip Memories

PayloadScanner

TCAMFilter

FlowBuffer

Queue Manager

Datainputfrom

GigabitEthernet

or SONET

Line Card

Free List Manager

SRAM 1Controller

SDRAM 1Controller

PacketScheduler

Dataoutput

To switch,Gigabit

Ethernet,or

SONETLine Card

Payload Match Bits Flow ID

ExtensibleModule(s)

SDRAM 2Controller

Xilinx XCV2000E FPGA


Content Matching Module

regex_app(given)

32dataen_out_appl

d_out_applsof_out_appleof_out_applsod_out_appltca_out_appl

clkreset_l

enable_l

dataen_appl_ind_appl_insof_appl_ineof_appl_insod_appl_intca_appl_in

Matched

ready_l

32

8To extended Bits of CAM

To existingMP1 circuit

FromProtocol

Wrappers

wrapper_module.vhd


Packet matching w/ Content Addressable Memory

• Sample Packet:• Source Address = 128.252.5.5 (dotted.decimal)• Destination Address = 141.142.2.2 (dotted.decimal)• Source Port = 4096 (decimal) • Destination Port = 80 (decimal)• Protocol = TCP (6)• Payload = “Consolidate your loans. CALL NOW”

– Payload Lists = { General SPAM (0), Save Money SPAM (1) }– Content Vector = “00000011” (binary) = x”03” (hex)

7103 3971

Src IP (hex) =80FC0505

Dest IP (hex) =8D8E0202

SrcPort = 1000

Dest Port =0050

Proto= 06

084072

All values shown In hex

Con-tent= 03

111 104


Sample Filter• Source Address = 128.252.0.0 / 16 • Destination Address = 141.142.0.0 / 16• Source Port = Don’t Care• Destination Port = 80• Protocol = TCP (6)• Payload includes general SPAM (List 0)

7103 3971

Src IP (hex) =80FC0505


SrcPort = 1000

Dest Port =0050

Proto= 06

084072

Src IP value =80FC0000


SrcPort = 0000

Dest Port =

50

Proto= 06

Src IP (hex) =FFFF0000

Dest IP (hex) =FFFF0000

SrcPort = 0000

Dest Port =FFFF

Proto= FF

Value

Mask: 1=care0=don’t care

IP Packet

Con-ten t=

01

Con-ten t=

01

Con-tent== 03

DROP the packet : It matches the filter


Packet Classifier with FlowIDCAM MASK [1]

CAM VALUE [1]

CAM MASK [2]

CAM VALUE [2]

CAM MASK [3]

CAM VALUE [3]

CAM MASK [N]

CAM VALUE [N]

Flow ID [1]112 bits

Flow ID [2]

Flow ID [3]

Flow ID [N]

Flow ID

. . .. . .

. . .

16 bits

Value Comparators

Mask Matchers

Priority Encoder

Resulting Flow

Identifier

Flow List

Source Address Destination Address

16 bits

Payload Match Bits

Source Port

Dest.Port

Protocol

- - CAM Table - -

Bits in IP Header


Other Modules Implemented• IPv4 CAM Filter

– 104 Bit header matching

• Fast IP Lookup (FIPL)– Longest Prefix Match– MAE-West at 10M

pkts/second

• Packet Content Scanner– Reg. Expression Search

• Data Queueing– Per-flow queue in SDRAM

• IPv6 Tunneling Module– Tunnels IPv6 over IPv4

• Statistics Module– Event counter

• Traffic Generator– Per-flow mixing

• Video Recoder– Motion JPEG

• Embedded Processor– KCPSM


Use of Identify in the FPX Design Flow• Identify is natural

additional to the current design flow

• Adds two new steps– Instrument– Debug

Compile

Simulate

Bit File

Synthesis

Map

Place n’ Route

Verify

Instrument

Debug


Two Part Solution• Instrumenter

– Assigns signals to monitor/trigger– Modifies existing VHDL

• Does not change original vhdl (create copies)– Streamlines synthesis

• Debugger– Communications to hardware via JTAG– Uses trigger setup– Includes waveform viewer– Creates VHDL simulation model


Instrumenter : Step 1

– Import Synplicity Project File– File >> Import Synplicty Project ….


Instrumenter : Step 2– Choose Signals to Monitor– Right-click glasses symbol near signal to

• Sample and Trigger • Sample Only• Trigger Only


Instrumenter : Step 3– Set Options– Click Edit IICE Options


Device Family

JTAG portBuiltin – Using RJ-45 Port

on FPXSyn – Adds four JTAG

I/O to toplevel (map rad_test)

Name of Clock in VHDL

Physical Resource Usage


BufferTypeDeviceram – Block RAMLogic – Flip-Flops

Number of Sample(Trade-Off: Resources)


Triggering OptionsSelf-Explanatory


Instrumenter : Step 4– INSTRUMENT DESIGN– Click “Save and Instrument Current Project”


Synthesis • Open Synplicty • RUN >> Run TCL Script…• Locate Synplicity.tcl in syn_projectname

folder


Synthesis

VHDL Files Containing Instrumented Design

Synplicity Synthesis Directory (.edf file here after running Synthesis)

TCL Script for Importing to Synplicity

Note: New Directory created by Instrumenter in

Folder where imported Synplicity Project is

located


Continue Design Flow• Add .edf file to build directory

• Generate Bitfile like usual

• Load Bitfile to FPX using NCHARGE– Make sure JTAG cable is unplugged

• Connect JTAG Cable to FPX and PC running IDENTIFY (Parrallel JTAG)

• Open IDENTIFY Debugger


IDENTIFY DEBUGGER• File >> Open

Project– Locate the

Instrumenter Project File

– Should be in same directory as Synplicity Project file


IDENTIFY DEBUGGER

• Trigger– Locate and set Trigger Event– Right Click Signal


IDENTIFY DEBUGGER

– Setup Project Options


IDENTIFY DEBUGGER

Xilinx JTAG Cable


IDENTIFY DEBUGGER

RUN

STOP

Relative Trigger Event(Trigger Beginning,

Middle, End of Sample)

Locate Trigger Signals

Waveform


IDENTIFY DEBUGGER• Waveform


IDENTIFY DEBUGGER• RTL View


References • Debugging of an Internet Packet Scheduler Using the Identify

Software, by Christopher K. Zuver and John W. Lockwood, The Syndicated, Volume 4, Issue 4, 2004.

• An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall, by John W. Lockwood, Christopher Neely, Christopher Zuver, James Moscola, Sarang Dharmapurikar, and David Lim; Field Programmable Logic and Applications (FPL), Lisbon, Portugal, pp. 859-868 (Paper 14B), Sep 1-3, 2003.

• Automated Tools to Implement and Test Internet Systems in Reconfigurable Hardware, by John W. Lockwood, Chris Neely, Chris Zuver, Dave Lim; SIGCOMM Computer Communications Review (CCR), vol 33, no 3, July 2003, pp 103-110.

development of a system-on-chip extensible network processor and debugging using identify

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