digital led boost

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A Digital Boost Converter to Drive White LEDs

Wei-Hsu Chang, Dan Chen*, Hung-Shou Nien and Chih-Hung Chen

RichTek Technology Corp.5F, No. 20, Taiyuan Street, Chupei City,

Hsinchu, Taiwan, R. O. C.

E-mail: [email protected]

Tel: 886-3-5526789 ext 2630

*

Department of Electrical EngineeringNational Taiwan University

Taipei, Taiwan, R. O. C.

E-mail: [email protected]

Tel: 886-2-33663542

Abstract-- A constant off-time boost converter

with digital control was proposed and imple-

mented with a field-programmable-gate-array

(FPGA) to power white light emitting diodes(WLEDs) for hand-held applications. In the

application, a lithium-ion battery with voltage

ranging from 3.3 V to 4.2 V was used to light a

serial connection of 4 WLEDs drawing current

levels from 2 mA to 20 mA. A constant

off-time digital PWM controller was chosen to

increase the dimming resolution. For the com-

pensator design, a small-signal control model

for the constant off-time converter was pre-sented. A digital PI compensator with pro-

grammable gain was used to stabilize the con-

trol loop for different LED current levels. Ex-

perimental results are presented. Same design

considerations apply to other applications if a

digitally-controlled boost or buck/boost con-

verter with high conversion gain is used.

I. INTRODUCTIONThe subject of DC power converters with

digital control schemes has been a hot research

area in recent years [1-6]. The present paper

focuses on issues of a digitally-controlled in-

ductor-based boost converter for white light

emitting diode (WLED) applications in

hand-held devices. A serial connection of 4

WLEDs with approximately 13.5 Volts total

drop was powered by a lithium-ion (Li-ion)

battery with voltage in the range of 3.3 V to 4.2

V. In the circuit, dimming of the light level isaccomplished by controlling the LED current.

In the paper, a comparison of the three

controller types, constant frequency, constant

on-time and constant off-time will be given

first. A constant off-time controller was pro-

posed and implemented for this application us-

ing an FPGA. A small-signal S-domain model

of a constant off-time boost converter will be

given for the purpose of digital compensatordesign. Experimental waveforms and control

loop gains of the breadboard will be shown.

II. DIGITAL PULSE-WIDTH MODULATORS

Fig. 1 shows the circuit diagram of a digi-

tally-controlled boost converter powering 4

WLEDs. The feedback operation is described

in the following. The output voltage of the

converter, vo, is connected to the load which

includes the WLED string and the sensing re-

sistor Rs. The sensed voltage vs(t) is discretized

and quantized to vs[n] by the analog-to-digital

converter (ADC). The subtraction of the sam-

pled voltage vs[n] from the reference voltage

Vref results in the error signal, err[n]. The digi-

tal compensator picks up err[n] and generates a

978-1-4244-1874-9/08/$25.00 2008 IEEE 558
mailto:[email protected]:[email protected]:[email protected]:[email protected]


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command/duty ratio d[n] to digital

pulse-width-modulator (DPWM) block which

generates a pulse, d(t), in continuous-time do-

main at the next switching cycle. To avoid limit

cycle oscillation in a digital control circuit [7,8],

the per-unit increment of the sensed voltagecaused by one least significant bit (LSB)

change in the DPWM duty cycle output has to

be smaller than the analog equivalent of the

LSB of the analog-to-digital converter. That is,

the relationship between per-unit change of

ADC and per-unit change of DPWM should

satisfy Eq. (1).

H

Sg

s

vv M

> (1)

Sv and are, respectively, the per-unit

change analog voltage of the ADC, and the

per-unit change of voltage conversion gain

when the DPWM duty cycle is changed by

one-unit. Hs is the output voltage sensing gain,

D is the duty cycle of the switching, and vg is

the input voltage. The DPWM block can be

implemented with a constant-frequency, con-

stant on-time, or constant off-time control.However, a comparison of the three control

schemes will be made in the following.

Fig.1. Block diagram of a voltage-mode digital boost

converter.

Constant-Frequency ControlThe voltage conversion gain, M, of a boost

converter with a constant-frequency control is

given by Eq. (2).

D

DM

=

1

1)( . (2)

By taking the differential on both sides of Eq.

(2) and setting D to be one unit, one can get

Eq. (4).

2)1(

1)(

DDM

= . (4)

Eq. (4) expresses the per-unit change of con-

version gain due to per-unit change of duty cy-

cle. It can be seen from Eqs. (1) and (4) that its

more difficult to satisfy Eq. (1) at higherDvalue. For a boost converter with high conver-

sion gain, D is relatively large and therefore

more difficult to satisfy Eq. (1) unless Sv is

increased. This means the resolution of the

dimming control would be reduced or a

higher-number-of-bit ADC is required. SinceD

varies with input voltage and load current, and

the fact that )(DM depends on D with high

nonlinearity, a constant-frequency controller isnot a good choice for such an application.

Constant On-Time ControlWith a constant on-time control, Eq. (3)

substituted into Eq. (2) can be rewritten as Eq.

(5).

off

onoff

T

TTM += 1)( , (5)

where

ckonon TNT = (6)

ckoffoff TNT = . (7)

Where Non and Noff are integers, and Tck is the

DPWM clock period. Since the on-time is fixed,

Eq. (5) can be expressed as

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2)(

off

onoff

N

NTM = . (8)

From Eq. (8), depends on Noff with high

nonlinearity. The problem associated with

dimming resolution encountered in a con-stant-frequency controller also applies in a con-

stant on-time controller.

Constant Off-Time ControlTaking the differential of both sides of Eq.

(5) with a constant Toff, the per-unit change of

Mcan be expressed as in Eq.9.

off

onN

TM1

)( = . (9)

From, Eq. (9), is independent of control

variable Ton. Once Noff is selected in a design,

dimming resolution is independent of operating

condition of the converter. This also often leads

to smaller ADC bit requirement. For this reason,

the constant off-time controller is chosen for

this application.

III. SMALL-SIGNAL MODEL AND

COMPENSATOR

DESIGN FOR A

CONSTANT OFF-TIME CONTROLLER

For feedback compensator design, a digi-

tal small-signal S-domain model for boost

converter was developed, as shown in Fig. 2.

The model of each major block in the system is

described in this section.

A. Control-to-Output Transfer Function Gvd(s)

The control-to-output voltage transfer

function of a boost converter is shown in Eq.

(10) [9].

2

00

)(1

)1)(1(

)(

s

Q

s

ss

KsG azvdvd+

+

+

= , (10)

where

2)1( D

VK

g

vd

= . (11)

Where Kvd denotes a DC gain, z is capacitor

ESR zero and a is the inductor zero, 0 is

resonance-frequency pole and Q is the quality

factor. D can be calculated under certain DCoperating condition.

B. Load Model and Sampling GainHS

The load consists of a sensing resistor and

WLED string, as shown in Fig. 3(a). A WLED

model was obtained from [10]. The

small-signal model of a WLED string series

with a sensing resistor is depicted in Fig. 3(b).

From Fig. 3(b), the transfer function of sam-

pling gainHS(s) can be expressed as Eq. (12).

o

sS

v

vH

(s) =

01

01

bsb

asa

+

+= , (12)

where

WDoWD CiRRba == )(S11 , (13)

S0 Ra = , (14)

)(S0 oWD iRRb += . (15)

WhereRWD is equivalent resistance of a WLEDstring, CWD is equivalent capacitance of a

WLED string, io is the load current through

WLED string, and RS is the sensing resistance.

Fig. 4 shows the frequency response of the

sampling gain HS(s). Notice that there is a no-

ticeable phase-shift in the gain due to the fact

that RWD varies with io, and a resonant peak in

the phase due to CWD effect, indicating that the

LED is not purely resistive. For a convenientdesign, the sampling gain can be simplified as

Eq. (16) under worse case (light load).

)(

min,S oWD

S

o

sS

iRR

R

v

vH

+== , (16)

where io,min is the minimum load current.

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C. ADC and DPWM Transfer Function, GADC(s)

and GDPWM(s)

Using the S-domain approach [6] to model

the digital control, the ADC transfer function is

shown in Eq. (17). The transfer function of a

constant off-time control can be obtained byusing the results from [11] and the approach of

[6]. The result is shown in Eq. (18).

ADC

ADC)(sT

ADC eKsG

= (17)

.)()( SsDT

offDPWM esGsG

= (18)

Where

2/

2

)(sin

)(

2sin

)( onsT

offon

offons

off

off e

j

sTTTTm

j

T

sG++= , (19)

whereKADC is the ADC sampling gain, msis the

up-slope of the ramp signal, Tonand Toff are the

on- and off-time at steady-state, respectively.

ADCsTe

and SsDT

e

are respectively the ADC

conversion delay time and the DPWM sam-

pling delay time in the digital control.

C. Digital CompensatorGC(s)

In a WLED driver application, fast tran-

sient response is not a critical issue. Therefore,

a first-order digital PI (Proportional and Inte-

gration) compensator was used as the compen-

sator. The transfer function represented by

z-transform is

11)(

)()(

==

z

A

zerr

zdzGcomp . (20)

For the design of the compensator in continu-

ous-time domain, Eq. (20) was transformed by

bilinear transform, and the result is shown in

Eq. (21).

dsTs

s

c es

T

s

T

AsG

+

=

)1/2

(

)( , (21)

where Ts is the sampling frequency which is

equal to switching frequency,A is the compen-

sator constant gain, and Td is the compensator

calculation time. The open-loop gain of the

converter is shown in Eq. (22).

)()()()( sGsGsGsT DPWMADCvd =

sc HsG )( , (22)

where the total delay time in the digital control

is equal to TADC+Td+DTS. More details about

delay time contribution are described in [6].

ovd

s

v

ssDTe

dsTeref

V

[n]s

vADCsTe

Fig. 2. Small-signal behavior model for digital boost

converter.

oi

oo vv +

ss vv +

(a)

ov

sv

(b)

Fig. 3. (a) Circuit configuration and (b) small-signal

model of WLEDs series with sensing resistor.

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Fig. 4. Frequency response of sensing gain Hs, in which

load condition is 4 WLEDs and Rs=25.

IV. SIMULATION AND EXPERIMENTAL RESULTS

A Xilinxs SPARTAN-3E FPGA was used

to implement the proposed digital constant

off-time pulse-width modulator. Table 1 shows

the breadboard parameters. Resolution bits of

DPWM and ADC are 11 bits and 8 bits, respec-

tively. A PI compensation was used in the ex-

periment to meet the stability criterion. Fig. 5

shows design concept of the constant off-time

DPWM, in which the related parameters are

shown in Table 2. In this digital implementation,

the switching frequency varies from 117K to

195 KHz with the constrained on-time between

3.41 s and 6.82 s. Fig. 6 shows the output

voltage (vo), inductor current (iL) and DPWM

signal (d) waveform under regulation with

WLEDs as load, in which off-time clock-cycles

is fixed at 256(~1.7 us). The voltage conversion

ration (M) varies linearly with on-time (Ton), as

shown Fig. 7. Fig. 8 shows the Bode plots of

)()( sGsG DPWMc for both the measured and the

theoretical results. They agree well with each

other. Fig. 9 shows the comparison of the

measured and the theoretical model of the

loop-gain Bode plots, from which one can be

seen that bandwidth and phase margin (PM) are

400 Hz and 60 degree. This controller has been

demonstrated to work satisfactorily with the

WLED load.

Table 1. Hardware parameter values.

Specifications

Switching Frequency (fs) 117~195 kHz

Input Voltage (vg) 3.3 V

Output Voltage (vo) 3.3~16 V

Output Current (io) 2 ~20 mA

Parameters

Inductance (L) 440 uH

ESR of L (RL) 64 mCapacitance (C) 390 uF

ESR of C (RC) 40 m

Controller (FPGA) Xilinx Spartan-3E

Resolution bits of DPWM 11 bits

DPWM clock rate(1/Tck) 150 MHz

Resolution bits of ADC (AD9057) 8 bits

Calculation Clock Frequency 4.68 MHz

ADC Sample Rate (1/TADC) 12.5 MHz

Table 2. Parameter values for DPWM implementation

with different duty cycle.

Toff(s) Ton (s) Duty

Seg. 1 6.82 0~3.41 0~0.33

Seg. 2 6.82 (0~3.41)+3.41 0.33~0.5

Seg. 3 3.41 (0~3.41)+3.41 0.5~0.66

Seg. 4 1.70 (0~3.41)+3.41 0.66~0.8

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(a)

(b)

Fig. 5. (a) Implementation of digital constant off-time

pulse-width modulator and (b) associated wave-

forms.

Fig. 6. Waveforms of a breadboard under

closed-loop regulation control. Circuit working

conditions: output voltage: 13.1 V (4 WLEDs)

input voltage: 3.3 V, load current: 20 mA.

Fig. 7. Voltage conversion ratio (M) vs. on-time (Ton).

103

104

105

106

-50

0

50

Frequency(Hz)

Gain(dB)

103

104

105

106

-400

-300

-200

-100

0

100

Frequency(Hz)

Phase(degree)

Theory data

Measurement data

Fig. 8. Bode plots of )()( sGsG DPWMc , measured vs.

theoretical.

102

103

104

105

10-80

-60

-40

-20

0

20

Frequency(Hz)

Gain(dB)

102

103

104

105

10-400

-300

-200

-100

0

Frequency(Hz)

Phase(degree)

Measurement data

Theory data

Fig. 9. Bode plots of the loop gain )(sT , measured vs.

theoretical. Converter working conditions: same

as Fig. 6.

V. CONCLUSIONS

A constant off-time digital controller was

proposed and demonstrated for a boost con-

verter of high-conversion gain ratio for WLED

applications. Compared to the other two con-

troller types, a constant off-time controller pro-

vides better light dimming resolution or re-

quires ADC converters with less number of bits.

A digital control model was proposed and veri-

fied in the paper.

For a typical DC voltage source applica-

tion using a digitally-controlled boost or

buck/boost converter with high conversion gain,

similar considerations apply.

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ACKNOWLEDGEMENT

This work was supported by Taiwan Gov-

ernment Industrial Bureau contract

#95-EC-17-A-01-I1-0051 to Richtek Technol-

ogy Corp. and National Taiwan University.

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[5] L. Peng, et al., A Novel PWM Technique in DigitalControl, IEEE Transactions on Industrial Elec-

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