digital logic design -course materials-fall 2008

MIDDLE EAST COLLEGE OF INFORMATION TECHNOLOGY

DEPARTMENT OF ELECTRONICS & COMMUNICATION

SUBJECT: DIGITAL LOGIC DESIGN

SUBJECT CODE: ELEC 0302

COMPILED BY

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

MIDDLE EAST COLLEGE OF INFORMATION TECHNOLOGY

SULTANATE OF OMAN

ACADEMIC YEAR: 2006-2007

Digital Logic Design- ELEC 0302 of 63 Instructor: Ms. J.Jenila

UNIT- I

LOGIC GATES

1.1. Number Systems and Codes

1.1.1. Introduction

• Digital circuits have only two states. • The two digital states can be given various names: ON/OFF, true/false, high/low, 1/0, etc. • The 1 and 0 notation naturally leads to the use of binary (base 2) numbers. • Octal (base 8) and hexadecimal (base 16) numbers are also used since they provide a

condensed number notation. Decimal (base 10) numbers are not of much use in digital electronics.

1.1.2. Binary Number System

• Consider a decimal number with digits a b c. We can write abc as :

(a b c)10 = a x 102 + b x 101 + c x 100

• Similarly, in the binary system a number with digits a b c can be written as

(a b c)2 = a x 22 + b x 21 + c x 20

• Each digit is known as a bit and can take on only two values: 0 or 1. The left most bit is the highest-order bit and represents the most significant bit (MSB), while the lowest-order bit is the least significant bit (LSB).

• Conversion from “decimal to binary” and from “binary to decimal” can be done using a set of rules.

• One popular rule to convert “decimal numbers into binary numbers” is by continuous division by 2 and keeping track of the remainders for converting integers and converting fractions is done by continuous multiplication by 2 and keeping track of the integers generated.

• Conversion from “binary to decimal” can be done by expanding the binary number in base 2.

Home Work Examples

1. Convert the following decimal numbers into their binary equivalents.

1. (44)10

2. (25)10

3. (58)10

4. (10.675)10

5. (17.125)10


2. Convert the following binary numbers into their decimal equivalents.

6. (10101110)2

7. (11011110) 2

8. (100.1011)2

9. (0.00110)2

10. (11011.0010)2

1.1.3. Octal Number System

• In this system the base is 8. The eight symbols used to write the numbers are 0, 1,2,3,4,5,6,7. • Conversion from “decimal to octal” can be done by continuous division by 8 and keeping

track of the remainders for converting integers and converting fractions is done by continuous multiplication by 8 and keeping track of the integers generated.

• Conversion from “octal to decimal “can be done by expanding the octal number in base 8. • Conversion from “binary to octal” can be done by grouping 3 bits (triplet) starting from the

LSB and converting each triplet into its equivalent octal number. • Conversion from “octal to binary” can be done by writing 3-bit binary equivalent of each

octal digit.

Home Work Examples

1. Convert the following decimal numbers into their octal equivalents.

1. (56)10

2. (632.405)10

3. (45.98)10

2. Convert the following octal numbers into their decimal and binary equivalents.

1. (74)8

2. (225)8

3. (707.53)8

3. Convert the following binary numbers into their octal equivalents.

1. (10111011110)2

2. (10001001.1001000111)2


1.1.4. Hexadecimal Number System

• In this system the base is 16. The sixteen symbols used to write the numbers are 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F.

• Conversion from “decimal to hexadecimal” can be done by continuous division by 16 and keeping track of the remainders for converting integers and converting fractions is done by continuous multiplication by 16 and keeping track of the integers generated.

• Conversion from “hex to decimal “can be done by expanding the hex number in base 16. • Conversion from “binary to hex” can be done by grouping 4bits (1nibble) starting from the

LSB and converting each nibble into its equivalent hex number. • Conversion from “hex to binary” can be done by writing 4-bit binary equivalent of each hex

digit.

Home Work Examples

1. Convert the following decimal numbers into their hex equivalents.

1. (576)10

2. (948)10

2. Convert the following hex numbers into their decimal and binary equivalents.

1. (A25C)16

2. (2589)16

3. Convert the following binary numbers into their hex equivalents.

1. (111111011110)2

2. (10001001.1001000111)2


Table 1.1 Decimal, binary, hexadecimal and octal equivalents.

1.1.5. Binary Arithmetic Home Work Examples 1.1.5.1 Binary Addition: 1) 1 0 1 2) 1 1 1 3) 1 0 1 1 4) 1 1 0 0 1 1 5) 1 1 1 1 +1 1 0 + 1 1 0 + 1 0 0 1 + 1 0 1 1 0 1 + 1 1 1 1 ------- ------- ----------- --------------- ----------- ------- ------- ----------- --------------- ----------- 6) 1 0 1 1 . 0 1 7) 0 . 0 0 1 1 8) 1 1 1 1 + 1 0 0 1 . 1 1 + 0 . 1 1 1 0 1 1 1 ------------------ ------------------ + 1 1 1 1 ------------------ ------------------ ------------- ------------- 1.1.5.2 Binary Subtraction: 1) 1 1 1 0 2) 1 0 0 0 3) 1 0 0 1 4) 1 0 1 1 0 - 0 1 0 1 - 0 0 0 1 - 0 1 1 1 - 0 1 0 1 1 --------- ------- ----------- --------------- --------- ------- ----------- ---------------


1.1.5.3 2’s complemental subtraction: 1) 1101 – 1010 2) 1000 – 0101 3) 1010 - 1101 1.1.5.4 Binary Multiplication: (1) 111 X 101 (2) 1101 X 1100 (3) 1111 X 0111 (4) 1101 X 111 (5) 1010 X 1101 (6) 1. 01 X 1. 01 (7) 101.01 X 1 1 1.1.5.5 Binary Division: (1) 11001 / 101 (2) 11000110 / 100 (3) 1111001 / 1001

1.2. Binary Codes

The usual way of expressing a decimal number in terms of a binary number is known as pure binary coding and is discussed in the Number Systems section. A number of other techniques can be used to represent a decimal number. These are summarized below.

1.2.1. BCD (8421) Code

In the 8421 Binary Coded Decimal (BCD) representation each decimal digit is converted to its 4-bit pure binary equivalent.

For example: (57)10 = (0101 0111) BCD

1.2.1.1 8421 BCD Addition:

Addition is the same as decimal addition with normal binary addition taking place from right to left. For example,

Eg.1 Eg.2

6 0110 (BCD for 6) 42 0100 0010 (BCD for 42)

+3 0011 (BCD for 3) +27 0010 0111 (BCD for 27)

____ __________

1001 (BCD for 9) 0110 1001 (BCD for 69)


In BCD addition, the number 6 (0110) must be added to the sum:

• when the result of any addition is greater than 9(1001) (i.e. an invalid BCD number) • Or if a carry is produced from the MSB.

This is to account for the six invalid BCD codes that are available with a 4-bit number. This is illustrated in the example below:

Eg.3 8 1000 (BCD for 8)

+7 0111 (BCD for 7)

1111 exceeds 9 (1001) so

+

0110 add six (0110)

Ans: 0001 0101 (BCD for 15)

Note that in the last example the 1 that carried forward from the first group of 4 bits has made a new 4-bit number and so represents the "1" in "15". In the examples above the BCD numbers are split at every 4-bit boundary to make reading them easier.

This is not necessary when writing a BCD number down. This coding is an example of a binary coded (each decimal number maps to four bits) weighted (each bit represents a number 1, 2, 4 and 8 respectively) code.

Decimal 8 4 2 1

0 0 0 0 0

1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 0 0 0 1 0 0 0 0 11 0 0 0 1 0 0 0 1 12 0 0 0 1 0 0 1 0

Table 1.2 8421 BCD Code


The code words 1010, 1011, 1100, 1101, 1110 and 1111 are invalid combinations in BCD code. Home Work Examples

Perform the 8421 BCD addition: 1) 53 + 24 2) 68 + 31 3) 99 + 98 4) 177 + 915 5) 808 + 229

1.2.1.2 8421 BCD subtraction:

BCD arithmetic requires additional steps while performed by ALUs which perform only binary operations. In BCD subtraction a correction factor of 6(0110) must be subtracted from any BCD word

• if that word is greater than 9(1001) • Or if a borrow from the next (MSB) higher digit occurred during the subtraction.

Home Work Examples

Perform the 8421 BCD subtraction: 1) 24 – 22 2) 99 – 78 3) 17 – 09 4) 120 – 208 5) 205 – 106

1.2.1.3 Unpacked and Packed BCD Numbers represented as one BCD word per byte are referred to as unpacked BCD. If two BCD words are put in a byte, this form is referred to as packed BCD. Example: (89) 10 is written as 0000 1000 0000 1001 in unpacked BCD and as 1000 1001 in packed BCD.

1.2.2. Gray Codes: In pure binary coding or 8421 BCD, counting from 7 (0111) to 8 (1000) requires 4 bits to be changed simultaneously.

In many practical applications( for example in A/D converters, shaft encoders, I/O devices etc.) it is desirable to use codes in which all successive code words differ in only one bit position. Such codes are known as cyclic codes or unit distance codes.

• Gray code is one such cyclic code. • Gray code also belongs to the class of reflected codes. • Gray code is a non-BCD, non-weighted, binary code.


Decimal Gray Code

0 0000

1 0001

2 0011

3 0010

4 0110

5 0111

6 0101

7 0100

8 1100

9 1101

10 1111

11 1110

12 1010

13 1011

14 1001

15 1000

Table 1.3 Gray Codes

Home Work Examples- Convert from Binary to Gray:

1) (10001111)2 2) (10001001)2 3) (1110010)2 4) (11011000)2

Home Work Examples- Convert from Gray to Binary:

1) (1001011) G 2) (10110100) G 3) (111011) G 4) (11001000) G


1.2.3. Excess - 3 Codes

This is also a non-weighted binary code. Excess-3 code of a decimal digit = decimal digit + 3 Excess-3 code of a BCD code word = BCD code word + 0011.

Decimal Excess 3

0 0 0 1 1 1 0 1 0 0 2 0 1 0 1 3 0 1 1 0 4 0 1 1 1 5 1 0 0 0 6 1 0 0 1 7 1 0 1 0 8 1 0 1 1 9 1 1 0 0 10 0 1 0 0 0 0 1 1 11 0 1 0 0 0 1 0 0 12 0 1 0 0 0 1 0 1 Table 1.4 Excess 3 Codes 1.2.4. Other Weighted Codes

Binary codes are classified as:

• Numeric and

• Alpha numeric codes.

In numeric codes only numbers are expressed in series of 0’s and 1’s. In alpha numeric codes numbers as well as letters are expressed as 0’s and 1’s. 1.2.5. Self complementing codes:

A code is said to be self complementing if the code word of the 9’s complement of N (i.e. 9 – N) can be obtained from the code word of N by complementing all the 1’s & 0’s. Example: code word for 5 is the complement of the code word for 4, code word for 6 is the complement of the code word for 3, code word for 7 is the complement of the code word for 2, code word for 8 is the complement of the code word for 1, code word for 9 is the complement of the code word for 0,


A necessary condition for a weighted code to be self complementing is that the sum of the weights must be equal to 9. Examples: 2421, 3321, 4311, 5211 are examples of positively weighted self- Complementing codes. 8 4 -2 -1, 6 4 2 -3 are examples of negatively weighted self complementing Codes etc.

Decimal 2421 3321 4311 5211 84-2-1 642-3

0 0000 0000 0000 0000 0000 0000

1 0001 0001 0001 0001 0111 0101

2 0010 0010 0011 0011 0110 0010

3 0011 0011 0100 0101 0101 1001

4 0100 0101 0101 0111 0100 0100

5 1011 1010 1010 1000 1011 1011

6 1100 1100 1011 1010 1010 0110

7 1101 1101 1100 1100 1001 1101

8 1110 1110 1110 1110 1000 1010

9 1111 1111 1111 1111 1111 1111

Table 1.5 Self complementing Codes While writing the code words,

• Below decimal 5, use the right-most bits representing the required code word first • Above decimal 5, use the left-most bits representing the required code word first

1.2.6. BCD Code 4221

The 4221 BCD code is another binary coded decimal code where each bit is weighted by 4, 2, 2 and 1 respectively. Unlike BCD coding there are no invalid representations. The decimal numbers 0 to 9 have the following 4221 equivalents.


Decimal 4221 1's complement

0 0000 1111

1 0001 1110

2 0010 1101

3 0011 1100

4 1000 0111

5 0111 1000

6 1100 0011

7 1101 0010

8 1110 0001

9 1111 0000

Table 1.6 4221 codes and its 1’s complement

• The 1's complement of a 4221 representation is important in decimal arithmetic.

1.3. BASIC LOGIC GATES 1.3.1. NOT Gate or Inverter:

• The simplest possible gate is called an "inverter," or a NOT gate. • The output of this gate is NOT the same as its input. It is called an inverter because it inverts

or complements the input signal. • It takes one bit as input (denoted as A) and produces its opposite as output (denoted asQ). • The table below shows a logic table (called the Truth Table) for the NOT gate and the normal

symbol for it in circuit diagrams:

Fig.1.1 NOT gate Truth Table & Symbol

• The table shows how the gate behaves. When A= 0, Q=1 & When A= 1, Q=0. • The Boolean expression for NOT gate is written as:

A Q 0 1 1 0

Q

Q=A


• Inverter gates are available in the form of Integrated Circuit (IC) as IC 7404.IC 7404 is a hex inverter (contains 6 inverters).

Physical realization of NOT gate: (using Transistor)

Fig1.2 NOT gate using Transistor

Case.1: When A = +5V, the transistor will be fully turned ON and draws maximum collector current. Hence Vcc = 5V drops completely across R thereby making output Q = 0V (logic Low).

Case.2: When A= 0V, the transistor is cutoff and hence Vcc = 5V is dropped across the transistor thereby making output Q= 5V (logic High).

Problem: Draw the output waveforms if the inputs to the NOT gate are as shown.

1 1. A = 0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Q = 1 2. A = 0 t1 t2 t3 t4 t5 t6 Q =


1.3.2. AND Gate

• The AND gate produces logic 1 output if and only if all the inputs to the gate are on a logic 1. Even if a single input is on logic 0, the output of the gate will be logic 0.

A B Q 0 0 0 0 1 0 1 0 0 1 1 1

Q

Fig.1.3 AND Gate Truth Table & Symbol

• The Boolean expression for AND gate is written as: Q = A.B

• AND gates are available in the form of Integrated Circuit as IC 7408.

IC 7408 is a quad 2-i/p AND gate (contain four 2 input AND gates). Physical realization of AND gate using diodes: Vcc = +5V R D1 A Q

D2 B

Fig.1.4 AND gate using Diodes

Case.1: When A=0, B=0; D1 and D2 are forward biased. Hence Q = 0.

Case.2: When A=0, B=1(5V); D1 is forward biased and D2 is reverse biased. Hence Q = 0.

Case.3: When A =1(5V), B=0; D1 is reverse biased and D2 is forward biased. Hence Q = 0.

Case.4: When A=1, B=1; D1 and D2 are reverse biased. Hence Q = 1


Physical realization of AND gate using transistors: +5V

R1 R2 Q A T1 T3 B T2

Fig.1.5 AND gate using Transistors

Case.1: When A=0, B=0; T1 and T2 are OFF, T3 is ON. Hence Q = 0.

Case.2: When A=0, B=1(5V); T1 and T2 are OFF, T3 is ON. Hence Q = 0.

Case.3: When A =1(5V), B=0; T1 and T2 are OFF, T3 is ON. Hence Q = 0.

Case.4: When A=1, B=1; T1 and T2 are ON. So T3 is OFF. Hence Q = 1.

Problem: Draw the output waveform if the inputs A and B for a 2 input AND gate are as shown below.

A = t1 t2 t3 t4 t5 t6 t7 B = t1 t2 t3 t4 t5 t6 t7

Q =


1.3.3. OR Gate

• The OR gate produces logic 1 output if any or all of the inputs are on logic 1. • It produces a logic 0 output if and only if all the inputs are on logic 0.

A B Q 0 0 0 0 1 1 1 0 1 1 1 1

Q

Fig.1.6 OR gate Truth Table & Symbol

• The Boolean expression for OR gate is written as: Y = A + B • OR gates are available in the form of Integrated Circuit as IC 7432. IC 7432 is a quad 2-input

OR gate (contains four 2 input OR gates).

Physical realization of OR gate using diodes:

D1

A Q D2

B R

Fig.1.7 OR gate using Diodes

Case.1: When A=0, B=0; D1 and D2 are reverse biased. Hence Q=0.

Case.2: When A=0, B=1; D1 is reverse biased and D2 is forward biased. So voltage drop across R =5V and hence Q=1.

Case.3: When A=1, B=0; D1 is forward biased and D2 is reverse biased. So a current flows through R and voltage drop across R = 5V and Q = 1.

Case.4: When A=1, B=1; D1 and D2 are forward biased, hence Q =1.


Physical realization of OR gate using transistors:

Vcc = +5 R1 R2 Q M T1 T2 T3 A B

Fig.1.8 OR gate using Transistors

Case.1: When A=0, B=0; T1 and T2 are OFF, T3 is ON. Hence Q=0.

Case.2: When A=0, B=1; T1 is OFF, but T2 is ON. So T3 is OFF. Hence Q=1.

Case.3: When A=1, B=0; T1 is ON , T2 is OFF. T3 is OFF. Hence Q=1.

Case.4: When A=1, B=1; T1 and T2 are ON. So T3 is OFF. Hence Q=1.

Problem: Draw the output waveform if the inputs for OR gates are as shown below.

1

A = 0 t1 t2 t3 t4 t5 t6 t7 t8 t9 1 B = 0 t1 t2 t3 t4 t5 t6 t7 t8 t9 Q =


1.3.4. NOR Gate

It is a NOT-OR gate. It can be realized by connecting an inverter to the output of an OR gate.

A B Q 0 0 1 0 1 0 1 0 0 1 1 0

Q

Fig.1.9 NOR gate Truth Table & Symbol

_____ • The Boolean expression for NOR gate is written as: Y = A + B.

• NOR gates are available in the form of Integrated Circuit as IC 7402.IC 7402 is a quad 2-input NOR gate.

Physical realization of NOR gate using transistors:

Vcc = +5V

R T1 T2 Q

A B

Fig.1.10 NOR gate using Transistors

Case.1: When A=0, B=0; T1 and T2 are OFF. Hence Q=1

Case.2: When A=0, B=1; T1 is OFF and T2 is ON. Hence Q=0 Case.3: When A=1, B-0; T1 is ON and T2 is OFF. Hence Q=0

Case.4: When A=1, B=1; T1 and T2 are ON, Hence Q=0.


Problem: Draw the output waveform of the NOR gate if the inputs are as shown below.

1

A = 0 t1 t2 t3 t4 t5 t6 t7 t8 t9 1 B = 0 t1 t2 t3 t4 t5 t6 t7 t8 t9

Q =

1.3.5 NAND Gate

• It is a NOT-AND gate. It can be realized by connecting an inverter to the output of an AND gate.

A B Q 0 0 1 0 1 1 1 0 1 1 1 0

Q

Fig.1.11 NAND gate Truth Table & Symbol

___ • The Boolean expression for the NAND gate is written as: Q= A.B

• NAND gates are available in the form of Integrated Circuit as IC 7400. IC 7400 is a quad 2-input NAND gate.


Physical realization of NAND gate using transistors:

Vcc = +5V Q A T1 B T2

Fig.1.12 NAND gate using Transistors Case.1: When A=0, B=0, T1 and T2 are OFF Hence Q=1. Case.2: When A=0, B=1, T1 is OFF and T2 is ON. But no current flows through resistance R. Hence Q = 1. Case.3: When A=1, B=0, T1 is ON but T2 is OFF. Hence there is no current through R again and Q=1. Case.4: When A=1, B=1, T1 and T2 both are ON. Hence all the voltage drops across R and hence Q=0.

Physical realization of NAND gate using DTL (Diode Transistor Logic):

This circuit contains an AND gate realized with the help of two diodes and a resistance followed by a transistor inverter circuit which inverts the output of the AND gate every time.

Vcc = +5V D1 R1 R2 A Q T D2 M B

Fig.1.13 NAND gate using Diode- Transistor Logic


Case.1: When A=0, B=0; D1 and D2 are forward biased. So M = 0, T is OFF and Q=1.

Case.2: When A=0, B=1(5V); D1 is forward biased and D2 is reverse biased. So M = 0, T is OFF and Q=1.

Case.3: When A =1(5V), B=0; D1 is reverse biased and D2 is forward biased. So M = 0, T is OFF and Q=1.

Case.4: When A=1, B=1; D1 and D2 are reverse biased. So M=1, T is ON and hence Q = 0.

Problem: Draw the output waveforms if the following inputs are applied to a 2 input NAND gate.

1 A = 0 t1 t2 t3 t4 t5 t6 t7 t8 1 B = 0 t1 t2 t3 t4 t5 t6 t7 t8 Q = 1.3.6. Universal Property of NOR & NAND gates NOR gate as a universal gate:

NOR gate is called a universal gate because all the basic logic functions can be realized using only NOR gates. The following figures show how NOR gates can be used to realize NOT, AND and OR gates respectively.


Fig.1.14 NOR gate as universal gate

NAND gate as a universal gate:

NAND gate is also called a universal gate because all the basic logic functions can be realized using only NAND gates. The following figures show how NAND gates can be used to realize NOT, AND and OR gates respectively.

Fig.1.15 NAND gate as universal gate


1.3.7. EXCLUSIVE OR (XOR) and EXCLUSIVE NOR (XNOR) Gates

The final two gates are the XOR and XNOR gates, also known as "exclusive or" and "exclusive nor" gates, respectively.

A B Q 0 0 0 0 1 1 1 0 1 1 1 0

Q

Fig.1.16 XOR gate Truth Table & Symbol

_ _

• The Boolean expression for the XOR gate is written as: Q = A.B + A.B

• The idea behind an XOR gate is, "If either A OR B is 1, (but NOT both), then Q is 1."

A B Q 0 0 1 0 1 0 1 0 0 1 1 1

Q

Fig.1.17 XNOR gate Truth Table & Symbol

_ _ • The Boolean expression for the XNOR gate is written as: Q = A.B + A. B

• It is the NOR-XOR gate.

• It can be realized by connecting an inverter at the output of an XOR gate.

1.3.7.1 XOR gate using basic gates

The reason why XOR might not be included in a list of gates is because you can implement it easily using the three basic gates. Here is one implementation:


Fig.1.18 XOR gate using basic logic gates

Exercise: Draw the circuit diagram of an EX-NOR gate using Basic Logic Gates.

1.3.7.2 Multi-input EX-OR and EX-NOR gates:

A B C EX-OR EX-NOR 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0

Table 1.7 Truth Table for 3 input EX-OR and EX-NOR gates

As seen from the truth table the multi-input Exclusive OR gate gives an output 1 if the

number of 1’s in the input columns is ODD in number. It gives an output 0 if the number of 1’s in the input columns is EVEN in number.

The opposite is true when it comes to the Exclusive NOR gate. That is this gate gives an

output 1 if the number of 1’s in the input columns is EVEN in number. It gives an output 0 if the number of 1’s in the input columns is ODD in number. 1.3.7.3 Realization of EX- OR gate using Universal Gates: ____ _ _ A A+B = A B B _ A Q A B _ _ _ B A+B = A B

Fig.1.19 XOR gate using NOR gate


_ _ A A A B = (A+ B) B B _ A Q A B _ _ B A B = (A+B)

Fig.1.20 XOR gate using NAND gate 1.3.7.4 Realization of EX- NOR gate using Universal Gates: _ _ _ A A A+B = A B B B _ A Q A B _ _ _ B A+B = (A+B)

Fig.1.21 XNOR gate using NOR gate ____ _ _ A A A . B = A + B B B _ A Q _ _ _ B A . B = (A + B)

Fig.1.22 XNOR gate using NAND gate


UNIT 2

BOOLEAN ALGEBRA AND K-MAPS

Boolean algebra is a set of rules, laws and theorems by which logical operations can be

expressed mathematically. It is a convenient and systematic way of expressing and analyzing the operation of digital circuits and systems.

2.1. De-Morgan’s Laws De-Morgan’s 1st law: BA. = A + B De-Morgan’s 2nd law: BA + = A . B Proof: De-Morgan’s laws can be proved using logic gates, Boolean Expressions and truth tables. Bubbled OR gate: An OR gate with inverters connected to the inputs is called a bubbled OR gate, which is equivalent to a NAND gate. A bubbled OR gate gives the same output as that of a NAND gate. The circuit is as follows:

A A B BA. Q = A + B = BA. B

Fig.2.1 (a) NAND gate, (b) Bubbled OR gate

A

B

_ A

_ B

_ _ A+B

___ A.B

0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0

Table 2.1: Proof of De-Morgan’s 1st law using truth table

Bubbled AND gate:

An AND gate with inverters connected to the inputs is called a bubbled AND gate. The

circuit is as follows, which is equivalent to a NOR gate. A bubbled AND gate gives the same output as that of a NOR gate. The circuit is as follows:


A

A BA + B Q = A . B = BA + B

Fig.2.2 (a) NOR gate (b) Bubbled AND gate

Exercise: Prove De-Morgan’s 2nd law using truth table.

2.2 Boolean Algebraic Laws and Theorems

Identity Dual

Operations with 0 and 1: (OR laws) 1a). X + 0 = X (identity) 2a). X + 1 = 1 (null element)

(AND laws) 1b). X .1 = X 2b). X .0 = 0

Idempotency theorem: (OR law) 3a). X + X = X

(AND law) 3b). X .X = X

Complementarity: (OR law) 4a). X + X’ = 1

(AND law) 4b). X .X’ = 0

Involution theorem: (double inversion) 5). (X’)’ = X

Identities for multiple variables

Commutative law: 6a). X + Y = Y + X

6b). X.Y = Y X

Associative law: 7a). (X + Y) + Z = X + (Y + Z)= X + Y + Z

7b). (XY)Z = X(YZ) = XYZ

Distributive law: 8a). X(Y + Z) = XY + XZ

8b). X + (YZ) = (X + Y)(X + Z)

De Morgan’s theorem: 9a). (X + Y + Z + ...)’ = X’Y’Z’...

9b). (XYZ...)’ = X’ + Y’ + Z’ + ...


Identity Dual

Simplification theorems: 10a). XY + XY’ = X (uniting) 11a). X + XY = X (absorption law 1) 12a). X + X’Y = X + Y (absorption law 2) 13a). (X + Y’)Y = XY (adsorption law)

10b). (X + Y)(X + Y’) = X 11b). X(X + Y) = X 12b). X (X’ + Y) = XY 13b). XY’ + Y = X + Y

Consensus theorem: 14a). XY + X’Z + YZ = XY + X’Z

14b). (X + Y)(X’ + Z)(Y + Z)= (X + Y)(X’ +Z)

Theorem for multiplying and factoring:

15a). (X + Y)(X' + Z) = XZ + X'Y

15b). XY + X'Z = (X + Z)(X' + Y)

Table 2.1 Boolean Laws & Theorems Exercise: Prove the Boolean Laws and Theorems shown in table 2.1 above using truth table.

2.3 Simplification of Boolean Expressions

2.3.1 Home Work Examples Simplify the following expressions using Boolean laws and realize the final expressions using logic gates: _ 1. Y= AB +AB _ 2. Y= ABC+ ABC _ _ 3. Y=(A+B+C) (A+B+C) _ _ _ 4. Y=AB (D+DC) + (A+DAC) B _ _ _ _ _ _ _ _ 5. Y=ABC + ABC + ABC+ABC _ _ _ _ _ _ 6. T=(x + x y z )+ (x + x y z)(x + x y z) ______ 7. Q= x ( y +z (xy +x z)) _ _ _ 8. Y = [ (x y z + x y )’ + y z ]’


2.3.2 Write the output expressions for the following logic circuits: 1. A B C Y = ? D 2.

A B D C Y=?


2.4 Standard Sum Of Product (SOP) and Product Of Sum (POS) forms

A variable in un-complemented or complemented form is known as a “literal”. If each term in the SOP and POS equations contains all the literals, these equations are known as standard SOP and standard POS equations respectively. The other name given to standard forms is canonical form.

Minterm: Each individual term (fundamental product) in standard SOP form is known as a minterm.

Maxterm: Each individual term (fundamental sum) in standard POS form is called a maxterm. A given SOP equation can be converted into its standard SOP form by ANDing the terms in the expression with terms formed by ORing that variable and its complement which is missing in the term.

A given POS equation can be converted into its standard POS form by ORing the terms in the expression with terms formed by ANDing that variable and its complement which is missing in the term.

Example 1: Convert the expression given below into its standard SOP equation.

Y = (A + BC) (B + C’ A)

Answer: ABC + ABC’ +AB’C’ + A’BC

(111) (110) (100) (011)

This is represented in short hand notation as Σ m (3, 4, 6, 7) = m3 +m4 +m6 +m7

Example 2: Convert the expression given below into its standard POS equation.

Y = (A + B) (A + C) (B + C’)

Answer: (A + B + C) (A + B + C’) (A + B’ + C) ( A’ + B + C’)

(000) (001) (010) (101)

This is represented in short hand notation as Π M (0, 1, 2, 5) = M0, M1, M2, M5.

Both the above obtained SOP and POS forms represent the same logical function. It is observed that there is a complementary type of relationship between a function expressed in terms of its minterms and its maxterms.

Hence if a function is specified in terms of its minterms / maxterms, its maxterm / minterm representation can be determined by using the complementary property.


Home Work Examples: 1. Convert the expression shown below into canonical SOP form.

i. f( A, B, C, D) = A’B’C’ + AC + B’D’

ii. f( A, B, C, D) = B

iii. f( A, B, C, D) = (A ‘+ D) (A + B’ + C) (A +C’ ) (B’ + C)

iv. f( A, B, C, D) = ABC + AC + BD

v. f( A, B, C, D) = AB + C

vi. f( A, B, C, D) = A + C

2. Convert the expression shown below into canonical POS form.

i. f( A, B, C) = (A + C) (B’ + C)

ii. f( A, B, C, D) = (A + B) (A + B) (C + D) (C + D)

iii. f( A, B, C, D) = (A + D) (A + B + C) (A +C ) (B + C)

iv. f( A, B, C, D) = (A + B) (A + C) (A + D)

v. f( A, B, C, D) = (A + B) (A + B + C)


2.5 KARNAUGH MAPS (K-Maps)

So far we have seen that applying Boolean algebra is laborious to simplify expressions. Apart from being laborious (and requiring & remembering all the laws) the method can lead to solutions which, though they appear minimal, are not.

The Karnaugh map provides a simple and straight-forward method of minimising Boolean expressions. With the Karnaugh map Boolean expressions having up to four and even six variables can be simplified.

A Karnaugh map provides a pictorial method of grouping together the expressions with common factors and therefore eliminating unwanted variables. The Karnaugh map can also be described as a special arrangement of a truth table.

They are constructed from minterm codes. Minterms are fundamental product of a standard SOP equation. The diagram below illustrates the correspondence between the Karnaugh map and the truth table for the general case of a two variable problem. 2.5.1 Two Variable K- map

Table 2.2 Truth Table Fig 2.3 A 2 -variable K-map

The values inside the squares are copied from the output column of the truth table, therefore there is one square in the map for every row in the truth table. Around the edge of the Karnaugh map are the values of the two input variable. A is down the left hand side and B is along the top. The diagram below explains this:

A B Q

0 0 a

0 1 b

1 0 c

1 1 d

B A

_ B 0

B 1

A 0 a 0 b 1 A 1 c 2 d 3


Table 2.3 Truth Table Fig 2.4 A 2 -variable K-map

2.5.2 Three Variable K- map

Fig 2.5 A 3-variable K-map

Table 2.4 Truth Table

A B F

0 0 0

0 1 1

1 0 1

1 1 1

A B B 0

B 1

A 0 0 0 1 1 A 1 1 2 1 3

A B C Y

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1

A BC BC BC BC BC

A 0 0 0 1 0 3 1 2

A 0 4 0 5 1 7 1 6


2.5.3 Four Variable K- map eg:- f(A,B,C,D) = Σ m (1,6,7,14)

Fig 2.6 A 4-variable K-map

Note: Gray code is used for naming the cells. Example: Consider the following map. The function plotted is: Z = f(A,B) =AB+AB=B

Fig 2.7 A 2 -variable K-map

• Note that values of the input variables form the rows and columns. That is the logic values of the variables A and B (with one denoting true form and zero denoting false form) form the head of the rows and columns respectively.

• Bear in mind that the above map is a one dimensional type which can be used to simplify an expression in two variables.

• There is a two-dimensional map that can be used for up to four variables, and a three-dimensional map for up to six variables.

Using algebraic simplification,

Z = AB + AB Z = (A+A) B Z = B (Variable A becomes redundant.)

A B B 0

B 1

A 0 0 0 1 1

A 1 02 1 3


Referring to the map above, the two adjacent 1's are grouped together. Through inspection it can be seen that variable A has its true and false form within the group. This eliminates variable A leaving only variable B which only has its true form. The minimised answer therefore is Z = B.

To minimize a logical function, f, we loop out logical adjacencies.

Note. Looping out logical adjacencies is a graphical alternative to algebraic calculations.

Unit distance code (Gray code):

For two bits, the Gray code is:

Only one bit changes as you go from left to right. This code preserves logical adjacencies. 2.5.4 Grouping adjacent ones Pair: In general a “pair” of horizontally or vertically adjacent 1’s means the SOP equation will have a variable and its complement that drop out. (Refer Fig.2.6 & 2.7) Quad: A “quad” is a group of four 1’s that are horizontally or vertically adjacent. The 1’s may be ‘end to end’ or in a form of a ‘square’. A ‘quad’ eliminates two variables and their complements. (Fig.2.8)


_ _ _ _ f (A,B,C,D) = A B C D + A B C D + A B C D + A B C D _ _ _ _ = A B ( C D + C D + C D + C D) _ _ _ = A B { C (D + D) + C (D + D)} _ = A B ( C + C) = A B

00 01 11 10


Note: These two variables which change from complemented to un-complemented form or vice-versa will drop out. Octet: Octet is a group of eight 1’s (shown in fig.2.9). Octet eliminates three variables and their complements. (Fig.2.9& 2.10)


Overlapping groups: The same 1 can be used more than once. (Fig.2.10 & 2.11)

Fig 2.10 A 4 -variable K-map Fig 2.11 A 4 -variable K-map

Rolling the K-map:

Visualize picking up the K-map and rolling it so that the left edge of the map touches the right edge. The first and the fourth column are adjacent to each other. The first and fourth rows are adjacent to each other. To indicate this lines (grouping) are drawn as shown in Fig.2.12.



Note: Rolling and overlapping are done to obtain the largest groups possible. Eliminating redundant groups: A redundant group is that where 1’s are already used by other groups. The central quad is redundant and can be eliminated. (Fig.2.13)


Example 1: f (A,B,C) = Σ m (0,2,3,4,6) The minimal SOP representation is : f= A B + C

Example 2: f (A,B,C,D) = Σ m (0,1,4,8,9,12,14,15)

Therefore the minimal SOP representation is: f= A B C +C D+B C


Home Work Examples:

1. f (A,B,C) = Σ m (0,3,4,5,6,7). Realize using NAND gates.

2. f ( A,B,C) = Σ m ( 1,3,5,7) Realize using NAND gates.

3. f( A,B,C,D) = Σ m (0,1,5,7,11,12,13,14,15) Realize using NAND gates.

4. f( A,B,C,D) = Σ m (7,9,10,11,12,13,14,15) Realize using NAND gates.

5. f( A,B,C) = Π M ( 1,2,3,4,5,7) Realize using NOR gates.

6. f( A,B,C) = Π M ( 4,5,6,7) Realize using NOR gates.

7. f( A,B,C,D) = Π M ( 2,3,5,7,10,13,14,15) Realize using NOR gates.

8. f( A,B,C,D) = Π M ( 0,1,3,5,7,9,11,13,15) Realize using NOR gates.

2.5.5 Don't care condition:

In some applications it doesn't matter what the output is for certain input values. These input values are called don't cares.

For instance, in the Binary Coded Decimal code, not all input values occur:

The decimal numbers are those in the range 0 to 9 and a minimum of 4 bits is needed to encode these. The remaining numbers 10 to 15 (1010 to 1111) correspond to code values which are not used in BCD.

We shall use the symbols d or X to denote don't cares. Don't cares can be exploited to help minimize Boolean functions.

Example:

f (A, B, C) = Σ m (0, 1, 5, 7) + d (2, 4)

The minimal SOP representation is f = B + AC

Home Work Examples: 1. f (A, B, C) = Σ m ( 0,2,3,7,8,9,11) + Σ d (1,12) 2. f( A,B,C,D) = Π M ( 0,1,3,4,6,7,9,14,15) + Σ d (2,5,12)


UNIT- III

COMBINATIONAL LOGIC CIRCUITS A combinational logic circuit is one in which the outputs are completely determined by the values of the inputs. The outputs are not dependent upon the previous states of the inputs or the previous outputs. Examples of combinational circuits are adders, subtractors, multiplexers, de-multiplexers, decoders, code converters, parity generators etc. 3.1 Multiplexer (MUX)

A multiplexer performs the function of selecting the input on any one of 'n' input lines and feeding this input to one output line when a proper combination of bits is placed on the control or select lines.

Use of MUX: Multiplexers are used as one method of reducing the number of integrated circuit packages required by a particular circuit design. This in turn reduces the cost of the system.

It quite often happens, in the design of large-scale digital systems, that a single line is required to carry two or more different digital signals. Of course, only one signal at a time can be placed on the one line. What is required is a device that will allow us to select, at different instants, the signal we wish to place on this common line. Such a circuit is referred to as a Multiplexer.

For a 2 line –to-1 line multiplexer we have two lines D0,D1 which are to be multiplexed on a single line output, Y. The two input lines are also known as the Data Inputs. Since there are two inputs, we will need one additional input to the multiplexer, known as the Control input or Select Inputs, A, to select which of the D inputs is to appear at the output.

Similarly for a 4 line –to-1 line multiplexer four input lines D0,D1,D2 and D3 (Data Inputs ), which are to be multiplexed on a single line output ,Y. The four lines are also known as the Data Inputs. Since there are four inputs, we will need two additional inputs to the multiplexer, known as the Control inputs or Select Inputs, to select which of the D inputs is to appear at the output. Let us call these select lines as A and B.The gate implementation of a 4-line to 1-line multiplexer is shown in Fig.3.1.

Working: When AB = 00, the output of gate G1 will be D0. The outputs of gates G2, G3 and G4 will be “0” because one or two inputs to those AND gates is a “0”.

Similarly when AB = 01, output of the circuit will be equal to D1 ,

When AB = 10, output of the circuit will be equal to D2 ,

When AB = 11, output of the circuit will be equal to D3.


Thus by applying proper combination of bits on the control inputs, a specific input can be made to appear on the output line of the Multiplexer.

A _ B _

A B D0 D1 Y D2 D3

Fig.3.1 Circuit diagram of 4 line –to-1 line multiplexer

Data Output

Inputs Select Inputs

Fig.3.2 Circuit Symbol of 4 line –to-1 line multiplexer

Exercise:

Draw the logic circuit diagram of 2 line – to-1 line and 8 line –to-1 line multiplexer.

G1

G2

G3

G4

D0 D1 Y D2 D3 A B


3.2 De-Multiplexer (DE-MUX)

De-multiplex means one into many. It is a logic circuit with one input and many outputs. By applying proper control signals we can steer or drive the input signal to one of the output lines.

‘n’ control lines

. . . D Data . input . ‘2n’ output lines . .

Fig.3.3 Logic Symbol of De-multiplexer

A 1x2 DE-MUX has 1 data input signal, 2 output lines and 1 control or select signal.




A _

A D _ Y0= A D Y1= A D

Fig.3.4 Circuit diagram of 1x2 De-multiplexer

DE-MUX


A _ B _ A B D _ _ Y0 = A B D _ Y1 = A B D _ Y2 = A B D

Y3 = A B D

Fig.3.5 Circuit diagram of 1x4 De-multiplexer 1x4 De-multiplexer Working:

When AB=00, the uppermost AND gate is enabled while all the other AND gates are disabled.

Therefore the data input signal, D, is transmitted only to the Y0 output. (Y0 = D), at that time Y1=0, Y2=0 and Y3=0. When AB = 01, the second AND gate is enabled and D is transmitted to Y1. When AB = 10, the third AND gate is enabled and D is transmitted to Y2. When AB = 11, the lowermost AND gate is enabled and D is transmitted to Y3. Exercise:

Draw the logic circuit diagram of 1X8 DE-MUX & 1X16 DE-MUX.

3.3 Encoder An encoder is similar to a multiplexer with one exception. It does not have the data input

signal. The control signals themselves act as the input lines. 3.4 Decoder A decoder is similar to a de-multiplexer with one exception. It does not have the data input signal. The control signals themselves act as the input lines. A 1 : 2 decoder will have 1 input line and 2 output lines.

A 2 : 4 decoder will have 2 input lines and 4 output lines.



G1

G2

G3

G4


A 2: 4 decoder with active high output lines:

In such a decoder the output line which is active will be on a logic HIGH (logic 1) while all the other output lines will be on active LOW (logic 0).

A _ B _ A B _ _ Y0= A B _ Y1= A B _ Y2= A B Y3= A B Fig.3.6 Circuit diagram of 2:4 Decoder with active high output lines A 2: 4 decoder with active low output lines:

This decoder is constructed using NAND gates as shown below. It is seen that the output line which is active will be on a logic LOW (logic 0) while all the other output lines will be on a logic HIGH (logic 1).

A _ B _ A B _ _ Y0= A B _ Y1= A B _ Y2= A B Y3= A B

Fig.3.7 Circuit diagram of 2:4 Decoder with active low output lines


Note: A de-multiplexer can be converted into its respective decoder by connecting the data input signal of the de-multiplexer to a logic HIGH (logic 1) permanently. 3.5 Adder Circuits

Half Adder (2-Bit Adder)

• A half adder circuit adds two binary numbers. It has two inputs and two outputs, Sum and Carry.

• The truth table of a Half Adder is as shown below.

Binary Inputs Sum Carry

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Table 3.1 Truth table of Half Adder

• The circuit of a Half adder can be realized using an EX OR gate and an AND gate as shown below.

Half Adder

Fig.3.8 Logic Circuit of Half Adder


Full Adder (3 bit Adder)

• A Full adder circuit adds three binary digits. This circuit has the provision to include carry bit. • A Full adder circuit has three inputs A, B, Cin (which represents the carry-in from the previous

stage) and two outputs, Sum and Carry out (Cout). • The truth table for the full adder (with carry input) is as follows.

A B Cin Sum Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Table 3.2 Truth table of Full Adder

• The “Cout” carry bit is 1 if both A and B are 1, or any one of A and B is 1 and the input carry, Cin is 1.

• The sum bit S is 1 if an odd number of the three inputs is on, i.e., S is the XOR of the three inputs.

• Hence, the full adder can be realized as shown below. • Notice that the full adder can be constructed from two half adders and an OR gate

Fig.3.9 Logic Circuit of Full Adder


NAND-NAND realization of a Full Adder circuit: _ _ _ _ _ _ Let Sum, S = A B Cin + A B Cin + A B Cin + A B Cin Cout = A B + B Cin + A Cin A _ B _ Cin _ A B Cin

SUM

COUT

Fig.3.10 Logic Circuit of Full Adder using NAND gates only

Binary 4-Bit Adder

• Adders for arbitrarily large binary numbers can be constructed by cascading full adders. • A full adder is used to add the least significant bits A0 and B0 when two or more adders of this

type are cascaded to increase the number of bits to be added (e.g. an 8-bit adder can be obtained by cascading two 4-bit adders.).

• The carry bit ``ripples'' from one stage to the next. • A drawback of this circuit is that the carry information has to propagate through all stages. • This may lead to undesirably long delays before the output stabilizes.


• The resulting sum is S3 S2 S1 S0. The final carry is C3. • Thus the final answer is C3 S3 S2 S1 S0.

Fig.3.11 Logic Circuit of 4Bit Binary Adder 3.6 Subtractor Circuit Half Subtractor circuit

• This circuit is used to subtract two binary bits. It has two inputs and two outputs, Difference and Borrow.

• The truth table of a half subtractor circuit is as shown below.

Binary Inputs Difference Borrow

A B D Bo

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Table 3.3 Truth table of Half Subtractor

C2 C1 C0C3

C3


A Difference B

Borrow

Fig.3.12 Logic Circuit of Half Subtractor Full Subtractor Circuit:

To perform multi bit subtraction where a borrow from the previous bit position may need to be

considered, a full subtractor circuit is used. This circuit has three inputs A (minuend), B (subtrahend), Bin (Borrow in from the previous stage) and two outputs D (Difference) and Bout (Borrow out).The truth table of a Full subtractor circuit can be shown as follows. The basic operation performed is (A-B-Bin).

X Y Bin D Bout

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

Table 3.4 Truth table of Full Subtractor

The circuit of a Full subtractor using half subtractors can be drawn as follows.

Fig.3.13 Logic Circuit of Full Subtractor


UNIT- IV

SEQUENTIAL LOGIC CIRCUITS Introduction

The output of a sequential circuit depends on the external inputs and the present contents of the memory elements referred to as a present state of memory elements. The new contents of the memory elements, referred to as the next state, depend on the external inputs and the present state. Hence, the output of a sequential circuit is a function of the time sequence of inputs and the internal states.

Sequential circuit whose behavior depends upon the sequence in which the input signals change is referred to as an asynchronous sequential circuit. The outputs will be affected whenever the inputs change. A sequential circuit whose behavior can be defined from the knowledge of its signal at discrete instants of time is referred to as a synchronous sequential circuit.

Since the design of asynchronous circuits is more difficult, their uses are limited. Synchronous circuits are also known as clocked-sequential circuits. 4.1 A 1-Bit Memory Cell

The basic digital memory circuit is known as FLIP-FLOP. It has two stable states which are known as the 1 state and the 0 state. It can be obtained by using NAND or NOR gates. We shall be systematically developing a FLIP-FLOP circuit starting from the fundamental circuit shown in Fig. 4.1. It consists of two inverters G1 and G2 (NAND gates used as inverters). The output of G1 is connected to the input of G2 (A2) and the output of G2 is connected to the input of G1 (A1). A1 Q A2 Q Fig 4.1 Cross-coupled inverters as a memory element.

Let us assume the output of G1 to be Q =1, which is also the input of G2 (A2=1). Therefore, the output of G2 will be Q =0, which makes A1 =0 and consequently Q = 1 which confirms our assumption.

In a similar manner, it can be demonstrated that if Q =0, then Q =1 and this is also consistent with the circuit connections.

G2


From the above discussion we note the following:

1. The outputs Q and Q are always complementary. 2. The circuit has two stable states; in one of the stable state Q =1 which is referred to as the 1

state (or set state) whereas in the other stable state Q =0 which is referred to as the 0 state (or reset state).

3. If the circuit is in 1 state, it continues to remain in this state and similarly if it is in 0 state, it continues to remain in this state. This property of the circuit is referred to as memory, i.e. it can store 1-bit of digital information.

Since this information is locked or latched in this circuit, therefore, this circuit is also referred to as a latch. In the modified circuit shown in Fig 4.2, two additional inverters G3 and G4 have been added.

If S = R = 0, the circuit is exactly the same as that off Fig 4.1. If S =1 and R =0, the output of G3 will be 0 and the output of G4 will be 1. Since one of the inputs of G1 is 0, its output will certainly be 1. Consequently, both the inputs of G2 will be 1 giving an output Q = 0. Hence, for this input condition, Q =1 and Q =0. Similarly, if S=0 and R=1 then the outputs will be Q =0 and Q =1. The first of these two input conditions (S=1, R=0) makes Q=1 which is referred to as the set state, whereas the second input condition (S=0, R=1) makes Q=0 which is referred to as the reset state or clear state. This gives us the means for entering the desired bit in the latch. S Q (Set) R Q (Reset) Fig 4.2 The memory cell with provision for entering data

Now we see what happens if the input conditions are changed from S=1, R=0 to S=R=0 or from S=0, R=1 to S=R=0. The output remains unaltered. This shows the basic difference between a combinational circuit and a sequential circuit, even though the sequential circuit is made up of combinational circuits.

The two input terminals are designated as set (S) and reset (R) because S=1 brings the circuit in set state and R =1 brings it to reset or clear state.

If S=R=1, both the outputs Q and Q will try to become 1 which is not allowed and therefore, this input condition is prohibited.

G1

G2

G3

G4


4.2 Clocked S-R FLIP-FLOP

It is often required to set or reset the memory cell (Fig 4.2) in synchronism with a train of pulses known as clock (abbreviated as CK). Such a circuit is shown in Fig 4.3, and is referred to as a clocked set-reset (S-R) FLIP-FLOP. S Q (Set) CK R Q (Reset) Fig 4.3 A clocked S-R FLIP-FLOP

In this circuit, if a clock pulse is present (CK=1), its operation is exactly the same as that of Fig 4.2. On the other hand, when the clock pulse is not present (CK =0), the gates G3 and G4 are inhibited, i.e. their outputs are 1 irrespective of the values of S or R. In other words, the circuit responds to the inputs S and R only when the clock is present.

Assuming that the inputs do not change during the presence of the clock pulse, we can express the operation of a FLIP-FLOP in the form of the truth table in Table 4.1 for the S-R FLIP-FLOP. Here Sn and Rn denote the inputs and Qn the output during the bit time n. Q n+1 denotes the output Q after the pulse passes, i.e. in the bit time n+1 Table 4.1 Truth table of S-R FLIP FLOP

Inputs Output Sn Rn Qn+1 0 0 Qn 1 0 1 0 1 0 1 1 ?

If Sn=Rn=0, and the clock pulse is applied, the output at the end of the clock pulse is same as

the output before the clock pulse, i.e Qn+1 = Qn. This is indicated in the first row of the truth table. If Sn=1 and Rn=0, the output at the end of the clock pulse will be 1, whereas if Sn =0 and

Rn=1, then Qn+1=0. These are indicated in the second and third rows of the truth table respectively. When Sn & Rn =1 and the clock pulse is present the output of gates G3 and G4 are both 0, making one

G1

G2

G3

G4


of the inputs of G1 and G2 NAND gates 0. Consequently, Q and Q bot will attain logic 1 which is inconsistent wit the assumption of complementary outputs. Now, when the clock pulse pass away (CK=0), the outputs of G3 and G4 will rise from 0 to 1. Depending upon the propagation delays of the gates, either the stable state Qn+1=1 (Qn+1 = 0) or Qn+1=0 (Qn+1 = 1) will result. That means the state of the circuit is undefined, indeterminate and therefore is indicated by a question mark. The condition Sn=Rn=1 is forbidden and it must not be allowed to occur.

The logic symbol of clocked S-R FLIP-FLOP is given in Fig 4.4. S Q CK _ R Q Fig 4.4 Logic symbol of clocked S-R FLIP-FLOP 4.2.1 Preset and Clear

In the FLIP-FLOP of Fig 4.3, when the power is switched on, the state of the circuit is uncertain. It may come to set (Q=1) or reset (Q=0) state. In many applications it is desired to initially set or reset the FLIP-FLOP, i.e. the initial state of the FLIP-FLOP is to be assigned. This is accomplished by using the direct or asynchronous inputs, referred to as preset (Pr) and clear (Cr) inputs. These inputs may be applied at any time between clock pulses and are not in synchronism with the clock. An S-R FLIP-FLOP with preset and clear is shown in Fig 4.5. If Pr=Cr=1 the circuit operates in accordance with the truth table of S-R FLIP-FLOP given in Table 4.1. Preset (Pr) S Q CK _ R Q Clear (Cr)

Fig 4.5 (a) An S-R FLIP-FLOP with preset and clear

S-R FLIP-FLOP

G

G

G

G


Pr S Q CK _ R Q Cr Fig 4.5(b) An S-R FLIP-FLOP logic symbol

If Pr =0 and Cr =1, the output of G1 (Q) will certainly be 1. Consequently, all the three inputs to G2 will be 1 which will make Q =0, Hence, making Pr=0 sets the FLIP-FLOP.

Similarly, if Pr=1 and Cr=0, the FLIP-FLOP is reset. Once the state of the FLIP-FLOP is established asynchronously, the asynchronous inputs Pr and Cr must be connected to logic 1 before the next clock is applied.

The condition Pr=Cr=0 must not be used, since this leads to an uncertain state. In the logic symbol of Fig4.5 (b), bubbles are used for Pr and Cr inputs, which means these are active-low, i.e. the intended function is performed when the signal applied to Pr or Cr is LOW. The operation of Fig 4.5 is summarized in Table 4.2.

Table 4.2 Summary of operation of S-R FLIP-FLOP

Inputs Output Operation CK Cr Pr Q Performed 1 1 1 Qn+1 (Table4.1) Normal FLIP-FLOP 0 0 1 0 Clear 0 1 0 1 Preset

S-R FLIP-FLOP


4.3 J-K FLIP-FLOP

The uncertainty in the state of an S-R FLIP-FLOP when Sn =Rn=1 (fourth row of the truth table) can be eliminated by converting it into a J-K FLIP-FLOP. The data inputs are J and K which are ANDed with Q and Q respectively, to obtain S and R inputs, i.e. S = J. Q R = K. Q

A J-K FLIP-FLOP thus obtained is shown in Fig 4.6. Its truth table is given in Table 4.3a which is reduced to Table 4.3b for convenience. Table 4.3a has been prepared for all the possible combinations of J and K inputs and for each combination both the states of the output have been considered. _ Pr S = J Q Q J CK _ Q K R = K Q

Cr

Fig 4.6 An S-R FLIP-FLOP converted into J-K FLIP-FLOP

It is not necessary to use the AND gates of Fig 4.6, since the same function can be performed by adding an extra input terminal to each NAND gate G3 and G4 of Fig 4.5. With this modification incorporated in Fig 4.5, we obtain the J-K FLIP-FLOP using NAND gates as shown in Fig 4.7. The logic symbol of J-K FLIP-FLOP is given in Fig 4.8.

S-R FLIP-FLOP


Table 4.3(a) Truth table for Fig 4.6

Data Inputs Outputs Inputs to

S-R FF Output

Qn+1 Jn Kn Qn Qn Sn Rn 0 0 0 1 0 0 0 0 1 0 0 0

0 = Qn 1

1 0 0 1 1 0 1 0 1 0 0 0

1 =1 1

0 1 0 1 0 0 0 1 1 0 0 1

0 = 0 0

1 1 0 1 1 0 1 1 1 0 0 1

1 = Qn 0

Table 4.3(b) Truth table of J-K FLIP-FLOP

Inputs Output

Jn Kn Qn+1 0 0 Qn 1 0 1 0 1 0 1 1 Qn

Fig 4.7 A J-K FLIP-FLOP using NAND gates


Pr J Q CK _ K Q Cr

Fig 4.8 Logic symbols of J-K FLIP-FLOP 4.4.1 The Race-Around Condition

The difficulty of both inputs l(S=R=1) being not allowed in an S-R FLIP-FLOP is eliminated in a J-K FLIP-FLOP by using the feedback connection from outputs to the inputs of the gates G3 and G4 (Fig 4.7). Table 4.3 assumes that the inputs do not change during the clock pulse (CK=1), which is not true because of the feedback connections.

Consider, for example, that the inputs are J=K=1 and Q=0, and a pulse as shown in Fig 4.9 is

applied at the clock input. After a time interval ∆t equal to the propagation delay through two NAND gates in series, the output will change to Q=1 (see fourth row of Table 4.3b). Now we have J=K=1 and Q=1 and after another time interval of ∆t the output will change back to Q=0. Hence, we conclude that for the duration tp of the clock pulse, the output will oscillate back and forth between 0 and 1. At the end of the clock pulse, the output will oscillate back and forth between 0 and 1 and the value of Q is uncertain. This situation is referred to as the race-around condition. Leading (positive) Trailing (negative)

edge edge ∆t tp O T

Fig 4.9 A clock pulse

J-K FLIP-FLOP


The race-around condition can be avoided if tp < ∆t < T. However, it may be difficult to satisfy

this inequality because of very small propagation delays in ICs. A more practical method for overcoming this difficulty is the use of the master-slave (M-S) configuration discussed below. 4.4.2 The Master-Slave J-K FLIP FLOP

A master-slave J-K FLIP-FLOP is a cascade of two S-R Flip-Flops, with feedback from the outputs of the second to the inputs of the first as illustrated in Fig 4.10. Positive clock pulses are applied to the first FLIP-FLOP and the clock pulses are inverted before these are applied to the second FLIP-FLOP.

When CK=1, the first FLIP-FLOP is enabled and the outputs Qm and Qm respond to the inputs J and K according to Table 4.3. At this time, the second FLIP-FLOP is inhibited because its clock is LOW (CK=0). When CK goes LOW (CK=1), the first FLIP-FLOP is inhibited and the second FLIP-FLOP is enabled, because now its clock is HIGH (CK=1). Therefore, the outputs Q and Q follow the outputs Qm and Qm respectively (second and third rows of Table 4.3b).

Since the second FLIP-FLOP simply follows the first one, it is referred to as the slave and the first one as the master. Hence, this configuration is referred to as master-slave (M-S) FLIP-FLOP.

Fig 4.10 A master-slave J-K FLIP-FLOP


Pr J Q CK _ K Q Cr

Fig 4.11 A master-slave J-K FLIP-FLOP logic symbol

In this circuit, the inputs to the gates G3m and G4m do not change during the clock pulse; therefore the race-around condition does not exist. The state of the master-slave FLIP-FLOP changes at the negative transition (trailing edge) of the clock pulse. The logic symbol of a M-S FLIP-FLOP is given in Fig 4.11. At the clock input terminal, the symbol > is used to illustrate that the output changes when the clock makes a transition and the accompanying bubble signifies negative transition (change in CK from 1 to 0). 4.5 D-Type FLIP-FLOP

If we use only the middle two rows of the truth table of the S-R (Table 4.1) or J-K (Table 4.3b) FLIP-FLOP, we obtain a D-type FLIP-FLOP as shown in Fig 4.12. It has only one input referred to as D-input or data input. Its truth table is given in Table 4.4 from which it is clear that the output Qn+1 at the end of the clock pulse equals the input Dn before the clock pulse. Pr J or S D Q CK _ Q K or R Cr

Fig 4.12 (a) A J-K or S-R FLIP-FLOP converted into a D-type FLIP-FLOP

M-S J-K FF

J-K Or S-R FF


Pr D Q CK _ Q Cr

Fig 4.12 (b) Its logic symbol Table 4.4 Truth table of D-Type FLIP-FLOP

Input Output Dn Qn+1 0 0 1 1

This is equivalent to saying that the input data appears at the output at the end of the clock

pulse. Thus, the transfer of data from the input to the output is delayed and hence the name delay (D) FLIP-FLOP. The D-type FLIP-FLOP is either used as a delay device or as a latch to store 1-bit of binary information. 4.6 T-Type FLIP-FLOP

In a J-K FLIP-FLOP, if J=K, the resulting FLIP-FLOP is referred to as a T-type FLIP-FLOP and is shown in Fig 4.13. It has only one input, referred to as T-input. Its truth table is given in Table 4.5 from which it is clear that if T=1 it acts as a toggle switch. For every clock pulse, the output Q changes. Pr T J Q CK _ K Q Cr

Fig 4.13 (a) A J-K FLIP-FLOP converted into a T-type FLIP-FLOP

D FF

J-K FF


Pr T Q CK _ Q

Cr Fig 4.13 (b) Its logic symbol

Table 4.5 Truth table of T-Type FLIP-FLOP

Input Output Tn Qn+1 0 Qn 1 Qn

An S-R FLIP-FLOP cannot be converted into a T-type FLIP-FLOP since S=R=1 is not

allowed. However, the circuit of Fig 4.14 acts as a toggle switch, i.e. the output Q changes with every clock pulse. S Q CK _ R Q

Fig 4.14 An S-R FLIP-FLOP as a toggle switch.

T FF

S-R FF


UNIT- V

REGISTERS AND COUNTERS

5.1 Registers

A Flip-flop can store 1 bit of digital information (1 or 0). It is also referred to as a 1 – bit register. An array of Flip flops is required to store binary information. The number of Flip-flops required is equal to the number of bits present in the binary word that is to be stored (one flip-flop for each bit). Registers find application in a variety of digital systems including microprocessors, counters, serial to parallel conversion, parallel to serial conversion etc. The data can be entered into the register in serial form (one bit at a time) or in parallel form (all the bits simultaneously). Data can also be retrieved in the serial or parallel form. For serial input /output, only one line is required for data input and one line for data output. For parallel input/output the number of lines required is equal to the number of bits that are to be inputted or outputted. Registers are classified depending upon the way in which data are entered and retrieved. There are four possible modes of operation.

1. Serial-in, serial-out (SISO) 2. Serial-in, parallel -out (SIPO) 3. Parallel-in, serial-out (PISO) 4. Parallel-in, parallel out (PIPO).

5.1.1 A 3- bit register using Flip Flops: A register is composed of a group of flip flops to store a group of bits (word). For storing an N- bit word, the number of flip flops required is N (one flip flop for each bit).

Fig 5.1 A 3-bit register using Flip-Flops.


A 3-bit register using flip flops is shown in Fig.5.1.The bits to be stored are applied at the D-

inputs which are clocked in at the leading-edge of the clock pulse. In this register, the data to be entered is available in parallel form. The data output is from Q0, Q1, Q2. 5.2 Shift registers:

Registers in which data are entered or/ and taken out in serial form are referred to as shift registers.

If bits are shifted in the Flip-flops with the occurrence of clock pulses in the right direction, it is known as a right shift register.

If bits are shifted in the Flip-flops with the occurrence of clock pulses in the left direction, it is known as a left shift register.

In the bi-directional shift register, data can be shifted from left to right as well as in the reverse direction, using the mode control.

A register is referred to as a universal register if it can be operated in all the four possible modes and also as a bi-directional register.

5.3 Counters

Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. Flip-flops are connected in a specific way to make a counter. The number of flip-flops used and how they are connected determine the number of states and the sequence of the states that the counter goes through in each complete cycle.

Counters can be classified into two broad categories according to the way they are clocked:

1. Asynchronous (Ripple) Counters – Here, the first flip-flop is clocked by the external clock pulse, and then each successive flip-flop is clocked by the Q or Q' output of the previous flip-flop. 2. Synchronous Counters – Here all the memory elements are simultaneously triggered by the same clock.

A decade counter counts from 0 to 9 and then recycles to 0 again.

In certain applications a counter must be able to count both up and down. Such a counter is known as an up-down counter. Digital counters are very useful in many applications. They can be found in digital clocks and parallel-to-serial data conversion.


5.3.1 A 3-bit counter using Flip-Flops

The counters are composed of flip flops. A 3-bit counter consisting of three flip flops is shown in Fig.5.2 below. A circuit with ‘n’ flip flops has 2n possible states. Therefore, the 3- bit counter can count from decimal 0 to 7.

Fig 5.2 A 3-bit counter using Flip-Flops. The flip flops used are JK master-slave flip flops. The pulses to be counted are connected at the clock input of FF0. The Q0 output of FF0 is connected to the clock input of FF1 and similarly Q1 is connected to the clock input of FF2. The flip flops are cleared by applying logic 0 at the clear input. For normal counting operation it is to be maintained at logic 1.

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digital logic design -course materials-fall 2008

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