EE1411

EECS141 1Lecture #18

EE141EE141--Fall 2010Fall 2010Digital Integrated Digital Integrated CircuitsCircuits

Lecture 18Lecture 18RatioedRatioed and Pass and Pass Transistor LogicTransistor Logic

EE1412

EECS141 2Lecture #18

AnnouncementsAnnouncementsProject #1 due Thursday

Midterm 2: Thurs. Nov. 4th, 6:30-8:00pm, Location TBD

Review session time/day TBA

EE1413

EECS141 3Lecture #18

RatioedRatioed LogicLogic

EE1414

EECS141 4Lecture #18

RatioedRatioed LogicLogic

VDD

VSS

PDNIn1In2In3

F

RLLoad

VDD

VSS

In1In2In3

F

VDD

VSS

PDNIn1In2In3

FVSS

PDN

Resistive DepletionLoad

PMOSLoad

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

VT < 0

Goal: build gates faster/smaller than staticcomplementary CMOS

EE1415

EECS141 5Lecture #18

Ratioed LogicRatioed LogicSpend power for speed

Use pseudo nMOS NOR gates, not NAND gates

DC characteristics:VOH = VDD

VOL depends on PMOS to NMOS ratio

W

WW W

EE1416

EECS141 6Lecture #18

PseudoPseudo--NMOS VTCNMOS VTC

0.0 0.5 1.0 1.5 2.0 2.50.0

0.5

1.0

1.5

2.0

2.5

3.0

Vin [V]

Vou

t[V

]

W/Lp = 4

W/Lp = 2

W/Lp = 1

W/Lp = 0.25

W/Lp = 0.5

EE1417

EECS141 7Lecture #18

Ratioed Logic LERatioed Logic LERising and falling delays aren’t the same

Calculate LE for the two edges separately

For tpLH:Cgate = WCG Cinv = (3/2)WCG LELH =

EE1418

EECS141 8Lecture #18

Ratioed Logic LE (pullRatioed Logic LE (pull--down edge)down edge)

What is LE for tpHL?Switch model would predict Reff = Rn||Rp

Would that give the right answer for LE?

EE1419

EECS141 9Lecture #18

Response on Falling EdgeResponse on Falling Edge

Time constant is smaller, but it takes more time to complete 50% VDD transient.

Rp actually takes some current away from discharging C

Rp

Rn C

vo(t)

0 1 2 3 40

0.5

1

vo(t)/VDD

t

Rp=Rn

Rp=2Rn

Rp=4RnRp=∞

CRpRnRpRn ⋅

+⋅=τ

τ/1)( t

DD

o eRpRn

RnRpRn

RnV

tv −⎟⎟⎠

⎞⎜⎜⎝

⎛+

−++

=

EE14110

EECS141 10Lecture #18

RatioedRatioed Logic PullLogic Pull--down Delaydown DelayThink in terms of the current driving Cload

When you have a conflict between currentsAvailable current is the difference between the twoIn pseudo-nMOS case:

(Works because Rp >> Rn for good noise margin)

( )1drive drive

1 RnR = R =1 1- Rn-Rn Rp Rp

EE14111

EECS141 11Lecture #18

Ratioed Logic LE (pullRatioed Logic LE (pull--down edge)down edge)

For tpHL (assuming Rsqp = 2Rsqn):Rgate = Rn/(1-Rn/Rp) = 2Rn Rinv = Rn

Cgate = WCG Cinv = 3WCG

LEHL = LE is lower than an inverter!

But have static power dissipation…

W

WW W

2W

W

EE14112

EECS141 12Lecture #18

Improved Loads (2)Improved Loads (2)VDD

VSS

F

Out

VDD

VSS

F_b

Out

AABB

M1 M2

Differential Cascode Voltage Switch Logic (DCVSL)

EE14113

EECS141 13Lecture #18

DCVSL Example1DCVSL Example1

EE14114

EECS141 14Lecture #18

PassPass--TransistorTransistorLogicLogic

EE14115

EECS141 15Lecture #18

PassPass--Transistor LogicTransistor Logic

Inpu

ts Switch

Network

OutOut

A

B

B

B

• N transistors• No static consumption

EE14116

EECS141 16Lecture #18

Example: AND GateExample: AND Gate

B

B

A

F = AB

0

EE14117

EECS141 17Lecture #18

NMOSNMOS--Only LogicOnly Logic

VDD

In

Outx

0.5µm/0.25µm0.5µm/0.25µm

1.5µm/0.25µm

0 0.5 1 1.5 20.0

1.0

2.0

3.0

Time [ns]Vo

ltage

[V]

xOut

In

EE14118

EECS141 18Lecture #18

NMOSNMOS--only Switchonly Switch

A = 2.5 V

B

C = 2.5V

CL

A = 2.5 V

C = 2.5 V

BM2

M1

Mn

Threshold voltage loss causesstatic power consumption

VB does not pull up to 2.5V, but 2.5V -VTN

NMOS has higher threshold than PMOS (body effect)

EE14119

EECS141 19Lecture #18

NMOS Only Logic: NMOS Only Logic: Level Restoring TransistorLevel Restoring Transistor

M2

M1

Mn

Mr

OutA

B

VDDVDDLevel Restorer

X

• Advantage: Full Swing• Restorer adds capacitance, takes away pull down current at X• Ratio problem

EE14120

EECS141 20Lecture #18

Restorer SizingRestorer Sizing

0 100 200 300 400 5000.0

1.0

2.0

W/Lr =1.0/0.25 W/Lr =1.25/0.25

W/Lr =1.50/0.25

W/Lr =1.75/0.25

Vol

tage

[V]

Time [ps]

3.0 •Upper limit on restorer size•Pass-transistor pull-downcan have several transistors in stack

EE14121

EECS141 21Lecture #18

Pass Transistor Logic LEPass Transistor Logic LEWhat is LE of “gate” shown below for A and B inputs?

Hint: Can you answer this question with only the information shown below?

EE14122

EECS141 22Lecture #18

Pass Transistor Logic LEPass Transistor Logic LEIn CMOS, a “gate” is defined only when trace a connection all the way back to a supply

Otherwise don’t know what drive resistance really is

EE14123

EECS141 23Lecture #18

Pass Transistor Logic LEPass Transistor Logic LE

EE14124

EECS141 24Lecture #18

Restoring Full Swing: CPLRestoring Full Swing: CPL

A

B

A

B

B B B B

A

B

A

B

F=AB

F=AB

F=A+B

F=A+B

B B

A

A

A

A

F=A⊕ΒÝ

F=A⊕ΒÝ

OR/NOR EXOR/NEXORAND/NAND

F

F

Pass-TransistorNetwork

Pass-TransistorNetwork

AABB

AABB

Inverse

(a)

(b)

EE14125

EECS141 25Lecture #18

CPL Level RestoreCPL Level Restore

EE14126

EECS141 26Lecture #18

Solution 2: Transmission GateSolution 2: Transmission Gate

A B

C

C

A B

C

C

BCL

C = 0 V

A = 2.5 V

C = 2.5 V

EE14127

EECS141 27Lecture #18

Resistance of Transmission GateResistance of Transmission Gate

Vout

0 V

2.5 V

2.5 VRn

Rp

0.0 1.0 2.00

10

20

30

Vout, V

Res

ista

nce,

ohm

s

Rn

Rp

Rn || Rp

EE14128

EECS141 28Lecture #18

RC Model of Transmission GateRC Model of Transmission Gate

EE14129

EECS141 29Lecture #18

PassPass--Transistor Based MultiplexerTransistor Based Multiplexer

AM2

M1

B

S

S

S F

VDD

GND

VDD

In1 In2S S

S S

EE14130

EECS141 30Lecture #18

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Dynamic Logic