ee141-fall 2007 alternate definition for write margin...

EE1411

EECS141 1Lecture #17

EE141EE141--Fall 2007Fall 2007Digital Integrated Digital Integrated CircuitsCircuits

Lecture 17Lecture 17DecodersDecodersRatioedRatioed LogicLogic

EE1412


AnnouncementsAnnouncementsHomework #7 due ThursdayProject phase 1 in lab this week and nextMidterm 2 two weeks from today

Covers up to next Tuesday’s lectureMidterm review: Fri. Nov. 2nd?

EE1413


Class MaterialClass Material

Last lectureSRAM

Today’s lectureDecodersRatioed logic

Reading (Chapters 12, 6)

EE1414


Alternate Definition for Write MarginAlternate Definition for Write Margin

EE1415


DecodersDecoders

EE1416


Memory Architecture: DecodersMemory Architecture: Decoders

Word 0

Word 1

Word 2

Word N2 2

Word N2 1

Storagecell

M bits M bits

N

w o rd s

S0

S1

S2

SN2 2

A 0

A 1

A K2 1

K = log2N

SN2 1

Word 0

Word 1

Word 2

Word N2 2

Word N2 1

Storagecell

S0

Input-Output(M bits)

Intuitive architecture for N x M memoryToo many select signals:

N words == N select signals K = log2NDecoder reduces the number of select signals

Input-Output(M bits)

D e c od er

EE1417


Row DecodersRow DecodersCollection of 2M complex logic gatesOrganized in regular and dense fashion

(N)AND Decoder

NOR Decoder

EE1418


Decoder Design ExampleDecoder Design Example

Look at decoder for 256x256 memory block (8KBytes)

EE1419


Problem SetupProblem SetupGoal: Build fastest possible decoder with static CMOS logic

What we knowBasically need 256 AND gates, each one of them drives one word line

N=8

EE14110


Problem Setup (1)Problem Setup (1)Each word line has 256 cells connected to itTotal output load is 256*Ccell + Cwire

Assume that decoder input capacitance is Caddress=4*Ccell

Each address drives 28/2 AND gatesA0 drives ½ of the gates, A0_b the other ½ of the gates

Neglecting Cwire, the fan-out on each one of the 16 address wires is: ( )8 8

13(2 / 2) 2

24

cellload

in cell

CCFC C

= = =

EE14111


Decoder FanDecoder Fan--OutOutF of at least 213 means that we will want to use more than log4(213) = 6.5 stages to implement the AND8

Need many stages anyways, so should use as many gates as needed to minimize total LE of the AND8

As saw in HW#7, tree of 2-input gates gives lowest LE

EE14112


Decoder StructureDecoder Structure

Using 2-input NAND gates8-input gate takes 6 stages

Total LE is (4/3)3 ≈ 2.4So PE is 2.4*213 – optimal N of ~7.1

EE14113


Decoder So FarDecoder So Far256 8-input AND gates

Each built out of tree of NAND gatesand inverters

Issue:Every address line hasto drive 128 gates (andwire) right awayForces us to add buffers just to drive address inputs

EE14114


Look Inside Each AND8 GateLook Inside Each AND8 Gate

EE14115


PredecodersPredecodersUse a single gate for each of the shared terms

E.g., from A0, A0, A1, and A1, generate four signals: A0A1, A0A1, A0A1, A0A1

In other words, we are decoding smaller groups of address bits first

And using the “predecoded” outputs to do the rest of the decoding

EE14116


Predecoder and DecoderPredecoder and DecoderA0 A1 A4 A5A2 A3

EE14117


PredecoderPredecoder/Decoder Layout/Decoder Layout

EE14118


Aside: Unmatched Decoder/Cell PitchAside: Unmatched Decoder/Cell Pitch

EE14119


PredecodePredecode OptionsOptionsBack to our 256x256 memory exampleTwo options for predecoding:

EE14120


PredecodePredecode Options (2)Options (2)Larger predecode usually better:More stages before the large wire capacitance

Decreases its effect on the circuit

Less capacitance switches

Lower powerEasier to fit 2-input gate into cell pitch

CL

1 161 16

256

4 to 16 predecoder

A0 A1 A2A3

A0A1A2A3

EE14121


Decoder in Project Phase 1Decoder in Project Phase 1

SRAM Array

WL0

WL1

WL31

a4 a3 a4 a3a2 a1 a0

EN

a2

Cw CwCw

EE14122


Decoder in Project Phase 1Decoder in Project Phase 1Because of wire capacitance from pre-decoder

Will have a fixed “side-load” on predecoderoutputsUse heuristic method we saw in HW#5 for sizing

EE14123


Why Why ““EnEn”” Signal?Signal?

EE14124


RatioedRatioed LogicLogic

EE14125


RatioedRatioed LogicLogic

VDD

VSS

PDNIn1In2In3

F

RLLoad

VDD

VSS

In1In2In3

F

VDD

VSS

PDNIn1In2In3

FVSS

PDN

Resistive DepletionLoad

PMOSLoad

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

VT < 0

Goal: build gates faster/smaller than staticcomplementary CMOS

EE14126


Ratioed LogicRatioed LogicSpend power for speed

Use pseudo nMOS NOR gates, not NAND gates

DC characteristics:VOH = VDD

VOL depends on PMOS to NMOS ratio

W

WW W

EE14127


PseudoPseudo--NMOS VTCNMOS VTC

0.0 0.5 1.0 1.5 2.0 2.50.0

0.5

1.0

1.5

2.0

2.5

3.0

Vin [V]

Vou

t[V

]

W/Lp = 4

W/Lp = 2

W/Lp = 1

W/Lp = 0.25

W/Lp = 0.5

EE14128


Ratioed Logic LERatioed Logic LERising and falling delays aren’t the same

Calculate LE for the two edges separately

For tpLH:Cgate = WCG Cinv = (3/2)WCG LELH =

EE14129


Ratioed Logic LE (pullRatioed Logic LE (pull--down edge)down edge)

What is LE for tpHL?Switch model would predict Reff = Rn||Rp

Would that give the right answer for LE?

EE14130


Response on Falling EdgeResponse on Falling Edge

Time constant is smaller, but it takes more time to complete 50% VDD transient.

Rp actually takes some current away from discharging C

Rp

Rn C

vo(t)

0 1 2 3 40

0.5

1

vo(t)/VDD

t

Rp=Rn

Rp=2Rn

Rp=4RnRp=∞

CRpRnRpRn ⋅

+⋅=τ

τ/1)( t

DD

o eRpRn

RnRpRn

RnV

tv −⎟⎟⎠

⎞⎜⎜⎝

⎛+

−++

=

EE14131


RatioedRatioed Logic PullLogic Pull--down Delaydown DelayThink in terms of the current driving Cload

When you have a conflict between currentsAvailable current is the difference between the twoIn pseudo-nMOS case:

(Works because Rp >> Rn for good noise margin)

( )1drive drive

1 RnR = R =1 1- Rn-Rn Rp Rp

EE14132


Ratioed Logic LE (pullRatioed Logic LE (pull--down edge)down edge)

For tpHL (assuming Rsqp = 2Rsqn):Rgate = Rn/(1-Rn/Rp) = 2Rn Rinv = Rn

Cgate = WCG Cinv = 3WCG

LEHL = LE is lower than an inverter!

But have static power dissipation…

W

WW W

2W

W

EE14133


Improved Loads (2)Improved Loads (2)VDD

VSS

F

Out

VDD

VSS

F_b

Out

AABB

M1 M2

Differential Cascode Voltage Switch Logic (DCVSL)

EE14134


DCVSL Transient ResponseDCVSL Transient Response

0 0.2 0.4 0.6 0.8 1.0-0.5

0.5

1.5

2.5

Time [ns]

Vol

tage

[V] A B

A B

A,BA,B

EE14135


DCVSL Example1DCVSL Example1

EE14136


DCVSL Example2DCVSL Example2

B

A A

B B B

Out

Out

XOR-NXOR gate

ee141-fall 2007 alternate definition for write margin...

Documents