ee141-spring 2008 digital integrated...

EE141

EE141EECS141 1Lecture #18

EE141EE141--Spring 2008Spring 2008Digital Integrated Digital Integrated CircuitsCircuits

LectureLecture 1818Domino LogicDomino LogicPower RevisitedPower Revisited


AnnouncementsAnnouncementsProject Phase 1 due Today!Midterm 2 next We – 6:30-8pm

105 North GateCovers all material up to (and including) dynamic logic

Review session next Tu

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Class MaterialClass MaterialLast lecture

Dynamic LogicToday’s lecture

Domino logicRevisit power

ReadingChapter 6, Chapter 7


Dynamic Dynamic Gate Gate -- RevisitedRevisited

In1

In2 PDNIn3

Me

Mp

Clk

ClkOut

CL

Out

Clk

Clk

A

BC

Mp

Me

Two phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)

on

off

1off

on

((AB)+C)

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Issues in Dynamic LogicIssues in Dynamic Logic

Charge LeakageCharge redistributionClock feedthroughBack-gate couplingCascading of gates


Issues in Dynamic Design 2: Issues in Dynamic Design 2: Charge SharingCharge Sharing

CL

Clk

Clk

CA

CB

B=0

AOut

Mp

Me

Charge initially stored on CLCA previously discharged

When A rises, this charge is redistributed (shared) between CL and CAMakes Out drop below VDD

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Charge Sharing ExampleCharge Sharing Example


Charge SharingCharge Sharing

B = 0

Clk

X

CL

Ca

Cb

A

Out

Mp

Ma

VDD

Mb

Clk Me

• Two cases:• Ma stays on – complete charge share• Ma turns off – incomplete charge share

•Complete charge share:• QCa = VOutCaΔQCL = -VOutCa

ΔVOut = -VDDCa/(Ca+CL)

•Incomplete charge share:• QCa = (VDD-VTN*)CaΔQCL = -(VDD-VTN*)Ca

ΔVOut = -(VDD-VTN*)Ca/CL

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Solution to Charge SharingSolution to Charge Sharing

Clk

Clk

Me

Mp

A

B

OutMkp

Clk

• Keeper helps a lot• Can still get failures if Out drops below inverter Vsw

• Another option: precharge internal nodes• Increases power and area


Issues in Dynamic Design 3: Clock Issues in Dynamic Design 3: Clock FeedthroughFeedthrough

CL

Clk

Clk

B

AOut

Mp

Me

Coupling between Out and Clk input of the prechargedevice due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.

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Clock FeedthroughClock Feedthrough

-0.5

0.5

1.5

2.5

0 0.5 1

Clk

Clk

In1

In2

In3

In4

Out

In &Clk

Out

Time, ns

Vol

tage

Clock feedthrough

Clock feedthrough


Issues in Dynamic Design 4: Issues in Dynamic Design 4: BackgateBackgate CouplingCoupling

CL1

Clk

Clk

B=0

A=0

Out1Mp

Me

Out2

CL2In

Dynamic NAND Static NAND

=1 =0

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BackgateBackgate Coupling EffectCoupling Effect

-1

0

1

2

3

0 2 4 6

Vol

tage

Time, ns

Clk

In

Out1

Out2


Other EffectsOther Effects

Capacitive couplingSubstrate couplingMinority charge injectionSupply noise (ground bounce)Cascading dynamic gates

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Cascading Dynamic GatesCascading Dynamic Gates

Clk

Clk

Out1In

Mp

Me

Mp

Me

Clk

Clk

Out2

V

t

Clk

In

Out1

Out2 ΔV

VTn

Only 0 → 1 transitions allowed at inputs!


Domino LogicDomino Logic

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Domino LogicDomino Logic

In1

In2 PDNIn3

Me

Mp

Clk

Clk Out1

In4 PDNIn5

Me

Mp

Clk

ClkOut2

Mkp

1 → 11 → 0

0 → 00 → 1


Why Named Domino?Why Named Domino?

Clk

Clk

Ini PDNInj

IniInj

PDN Ini PDNInj

Ini PDNInj

Like falling dominos!

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Properties of Domino LogicProperties of Domino Logic

Only non-inverting logic can be implementedVery high speed

static inverter can be skewed, only L-H transition criticalInput capacitance reduced – smaller logical effort


Domino Logic LEDomino Logic LE

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Domino Logic LE (skewed static gate)Domino Logic LE (skewed static gate)


Buffer Buffer ““AverageAverage”” LELE

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Designing with Domino Logic

Mp

Me

VDD

PDN

Clk

In1In2

In3

Out1

Clk

Mp

Me

VDD

PDN

Clk

In4

Clk

Out2

Mr

VDD

Inputs = 0during precharge

Can be eliminated


Footless DominoFootless Domino

The first gate in the chain needs a foot switchPrecharge is rippling – short-circuit current

VDD

Clk Mp

Out1

In1

1 0

VDD

Clk Mp

Out2

In2

VDD

Clk Mp

Outn

InnIn3

1 0

0 1 0 1 0 1

1 0 1 0

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Can mitigate short-circuit current by alternating between footed and unfooted domino



To eliminate the short-circuit current, can delay the clock for each stage

VDD

Clk Mp

Out1

In1

1 0

VDD

Clk Mp

Out2

In2

VDD

Clk Mp

Outn

InnIn3

1 0

0 1 0 1 0 1

1 0 1 0

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Differential (Dual Rail) DominoDifferential (Dual Rail) Domino

A

B

Me

Mp

Clk

ClkOut = AB

!A !B

MkpClk

Out = ABMkp Mp

Allows inverting gates to be built


npnp--CMOSCMOS

In1

In2 PDNIn3

Me

Mp

Clk

Clk Out1

In4 PUNIn5

Me

MpClk

Clk

Out2(to PDN)

1 → 11 → 0

0 → 00 → 1

Only 0 → 1 transitions allowed at inputs of PDN Only 1 → 0 transitions allowed at inputs of PUN

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NORA LogicNORA Logic

In1

In2 PDNIn3

Me

Mp

Clk

Clk Out1

In4 PUNIn5

Me

MpClk

Clk

Out2(to PDN)

1 → 11 → 0

0 → 00 → 1

Fast, but EXTREMELY sensitive to noise!


Power Power RevisitedRevisited

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Transition Activity and PowerTransition Activity and PowerEnergy consumed in N cycles, EN:

EN = CL • VDD2 • n0→1

n0→1 – number of 0→1 transitions in N cycles

fVCN

nfNEP DDLN

NNavg ⋅⋅⋅⎟

⎠⎞

⎜⎝⎛=⋅= →

∞→∞→

210limlim

fN

nN

⋅= →

∞→→10

10 limα

fVCP DDLavg ⋅⋅⋅= →2

10α


“Dynamic” or timing dependent component

Type of Logic Function (NOR vs. XOR)“Static” component (does not account for timing)

Circuit Topology

Type of Logic Style (Static vs. Dynamic)

Signal StatisticsInter-signal Correlations

Signal Statistics and Correlations

Factors Affecting Transition ActivityFactors Affecting Transition Activity

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Type of Logic Function: NORType of Logic Function: NOR

A B Out0 0 10 1 01 0 01 1 0

Example: Static 2-input NOR Gate

Assume signal probabilitiespA=1 = 1/2pB=1 = 1/2

Then transition probabilityp0→1 = pOut=0 x pOut=1

= 3/4 x 1/4 = 3/16

α0→1 = 3/16

If inputs switch every cycle


Type of Logic Function: NANDType of Logic Function: NAND

A B Out0 0 10 1 11 0 11 1 0

Example: Static 2-input NAND Gate



=

α0→1 =

If inputs switch every cycle

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Type of Logic Function: XORType of Logic Function: XOR

A B Out0 0 00 1 11 0 11 1 0

Example: Static 2-input XOR Gate



= 1/2 x 1/2 = 1/4

α0→1 = 1/4

If inputs switch in every cycle


Power Consumption of Dynamic GatesPower Consumption of Dynamic Gates

In1

In2 PDNIn3

Me

Mp

CLK

CLKOut

CL

Power only dissipated when previous Out = 0

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Dynamic Power Consumption is Dynamic Power Consumption is Data DependentData Dependent

A B Out0 0 10 1 01 0 01 1 0

Dynamic 2-input NOR Gate

Assume signal probabilitiesPA=1 = 1/2PB=1 = 1/2

Then transition probabilityP0→1 = Pout=0 x Pout=1

= 3/4 x 1 = 3/4

Switching activity always higher in dynamic gates!P0→1 = Pout=0


Vdd

I

I

Vdd

IN

INB

OUTB OUT

Guaranteed transition for every operation!

α0->1 = 1

DualDual--Rail DominoRail Domino

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ClockClock

Always switchesOften consumes 25-50% of total powerClock gating commonly employed


Problem: Reconvergent Fanout

A

B

X

Z

Reconvergence

P(Z = 1) = P(B = 1) . P(X = 1 | B=1)

Becomes complex and intractable fast

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Inter-Signal Correlations

Logic withoutreconvergent fanout

Logic with reconvergent fanout

A

BZ

CA

Z

C

B

p0→1 = (1 – pApB) pApBP(Z = 1) = p(C=1 | B=1) p(B=1)

p0→1 = 0

Need to use conditional probabilities to model inter-signal correlationsCAD tools best for performing such analysis


GlitchingGlitching in Static CMOSin Static CMOSA

B

X

CZ

ABC 101 000

X

Z

Gate DelayAlso known as

dynamic hazards

The result is correct,but there is extra power dissipated

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Example: Chain of NAND GatesExample: Chain of NAND Gates1

Out1 Out2 Out3 Out4 Out5

0 200 400 6000.0

1.0

2.0

3.0

Time (ps)

Volta

ge (V

)

Out8Out6

Out2

Out6

Out1

Out3

Out7

Out5


Principles for Power ReductionPrinciples for Power ReductionMost important idea: reduce wasteExamples:

Don’t switch capacitors you don’t need to– Clock gating, glitch elimination, logic re-structuring

Don’t run circuits faster than needed– Power α VDD

2 – can save a lot by reducing supply for circuits that don’t need to be as fast

– Parallelism falls into this category

Let’s say we do a good job of that – then what?

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Energy Energy –– Performance SpacePerformance Space

Plot all possible designs on a 2-D planeNo matter what you do, can never get below/to the right of the solid line

This line is called “Pareto Optimal Curve”Usually (always) follows law of diminishing returns

PerformanceEn

ergy

/op


Optimization PerspectiveOptimization Perspective

Instead of metrics like EDP, this curve often provides information more directly

Ex1: What is minimum energy for XX performance?Ex2: Over what range of performance is a new technique (dotted line) actually beneficial?

Performance

Ener

gy/o

p

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Sequential logic

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