EE141-Fall 2010 Digital Integrated 2010 Digital Integrated Circuits Lecture 20 ... Register Adder Shifter Multiplexer Control ... Full-Adder AB Cout Sum Cin Full adder kill kill EE141 10 EECS141 Lecture #20 10

Download EE141-Fall 2010 Digital Integrated   2010 Digital Integrated Circuits Lecture 20 ... Register Adder Shifter Multiplexer Control ... Full-Adder AB Cout Sum Cin Full adder kill kill EE141 10 EECS141 Lecture #20 10

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  • EE1411

    EECS141 1Lecture #20

    EE141EE141--Fall 2010Fall 2010Digital Integrated Digital Integrated CircuitsCircuits

    Lecture 20Lecture 20AddersAdders

    EE1412

    EECS141 2Lecture #20

    AnnouncementsAnnouncementsMidterm 2: Thurs. Nov. 4th, 6:30-8:00pm

    Exam starts at 6:30pm sharpReview session: Wed., Nov. 3rd, 6pm

    Project phase 2 out this Thurs., due next Fri.

    Elad out of the office this afternoonChintan will hold office hours today from 2-3pmHanh-Phuc will hold extra office today from 4-5pmElad will hold extra office hours Thurs. 1-2pm

    EE1413

    EECS141 3Lecture #20

    Class MaterialClass Material

    Last lectureDynamic logic

    Todays lectureAdders

    ReadingChapter 11

    EE1414

    EECS141 4Lecture #20

    AddersAdders

    EE1415

    EECS141 5Lecture #20

    An Intel MicroprocessorAn Intel Microprocessor

    9-1

    Mux

    9-1

    Mux

    5-1

    Mux

    2-1

    Mux

    ck1

    CARRYGEN

    SUMGEN+ LU

    1000um

    b

    s0

    s1

    g64

    sum sumb

    LU : LogicalUnit

    SUM

    SEL

    a

    to Cachenode1

    REG

    Itanium has 6 64-bit integer execution units like this

    EE1416

    EECS141 6Lecture #20

    BitBit--Sliced DesignSliced Design

    Bit 3

    Bit 2

    Bit 1

    Bit 0

    Reg

    ister

    Add

    er

    Shift

    er

    Mul

    tiple

    xer

    Control

    Dat

    a-In

    Dat

    a-O

    ut

    Tile identical processing elements

  • EE1417

    EECS141 7Lecture #20

    Itanium Integer Itanium Integer DatapathDatapath

    Fetzer, Orton, ISSCC02

    EE1418

    EECS141 8Lecture #20

    Data Paths Are Thermal HogsData Paths Are Thermal Hogs

    EE1419

    EECS141 9Lecture #20

    FullFull--AdderAdderA B

    Cout

    Sum

    Cin Fulladder

    killkill

    EE14110

    EECS141 10Lecture #20

    The Binary AdderThe Binary Adder

    S A B Ci =

    A= BCi ABCi ABCi ABCi+ + +

    Co AB BCi ACi+ +=

    EE14111

    EECS141 11Lecture #20

    Express Sum and Carry as a function of P, G, KExpress Sum and Carry as a function of P, G, K

    Define 3 new variables which ONLY depend on A, BGenerate (G) = ABPropagate (P) = A BKill = A B

    Can also derive expressions for S and Co based on K and P

    Propagate (P) = A + BNote that we will sometimes use an alternate definition for

    EE14112

    EECS141 12Lecture #20

    Simplest Adder: RippleSimplest Adder: Ripple--CarryCarry

    Worst case delay linear with the number of bits

    Goal: Make the fastest possible carry path circuit

    FA FA FA FA

    A0 B0

    S0

    A1 B1

    S1

    A2 B2

    S2

    A3 B3

    S3

    Ci,0 Co,0

    (= Ci,1)

    Co,1 Co,2 Co,3

    td = O(N)

    tadder = (N-1)tcarry + tsum

  • EE14113

    EECS141 13Lecture #20

    Complementary Static CMOS Full Adder: Complementary Static CMOS Full Adder: DirectDirect ImplementationImplementation

    28 Transistors

    A B

    B

    A

    Ci

    Ci A

    X

    VDD

    VDD

    A B

    Ci BA

    B VDD

    A

    B

    Ci

    Ci

    A

    B

    A CiB

    Co

    VDD

    S

    EE14114

    EECS141 14Lecture #20

    Complementary Static CMOS Full AdderComplementary Static CMOS Full Adder

    28 Transistors

    EE14115

    EECS141 15Lecture #20

    Inversion PropertyInversion Property

    A B

    S

    CoCi FA

    A B

    S

    CoCi FA

    EE14116

    EECS141 16Lecture #20

    Minimize Critical Path by Reducing Inverting StagesMinimize Critical Path by Reducing Inverting Stages

    Exploit Inversion Property

    A3

    FA FA FA

    Even cell Odd cell

    FA

    A0 B0

    S0

    A1 B1

    S1

    A2 B2

    S2

    B3

    S3

    Ci,0 Co,0 Co,1 Co,3Co,2

    EE14117

    EECS141 17Lecture #20

    A Better Structure: The Mirror AdderA Better Structure: The Mirror Adder

    VDD

    CiA

    BBA

    B

    A

    A BKill

    Generate"1"-Propagate

    "0"-Propagate

    VDD

    Ci

    A B Ci

    Ci

    B

    A

    Ci

    A

    BBA

    VDD

    SCo

    24 transistors

    EE14118

    EECS141 18Lecture #20

    Sizing the Mirror Adder: Sizing the Mirror Adder: FanoutFanout Since LE of carry gate is 2, want f of 2to get EF of 4

    Use min. size sum gates to reduceload on carry.

    Total load on carry gate is:

    Cload = CCi + (6+6+9)Cload = 2CCi

  • EE14119

    EECS141 19Lecture #20

    Sizing the Mirror AdderSizing the Mirror Adder

    Cload = CCi + (6+6+9) = 2CCi

    CCi = 21

    Minimum size G and K stacks to reduce diffusion loading

    EE14120

    EECS141 20Lecture #20

    Mirror Adder SummaryMirror Adder SummaryThe NMOS and PMOS chains are completely symmetrical. Maximum of two series transistors in the carry-generation gate.

    When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. Reduction of the diffusion capacitances is particularly important.

    Carry signals are critical - transistors connected to Ciare placed closest to the output.

    Only the transistors in the (propagate) carry chain have to be optimized for speed. All transistors in the sum stage can be minimal size.

    EE14121

    EECS141 21Lecture #20

    Transmission Gate Full AdderTransmission Gate Full Adder

    A

    B

    P

    Ci

    VDD A

    A A

    VDD

    Ci

    A

    P

    AB

    VDD

    VDD

    Ci

    Ci

    Co

    S

    Ci

    P

    P

    P

    P

    P

    Sum Generation

    Carry Generation

    Setup

    EE14122

    EECS141 22Lecture #20

    Manchester Carry ChainManchester Carry Chain

    CoCi

    Gi

    KiPi

    PiVDD

    EE14123

    EECS141 23Lecture #20

    Dynamic Manchester Carry ChainDynamic Manchester Carry Chain

    CoCi

    Gi

    KiPi

    PiVDD

    CoCi

    Gi

    PiVDD

    EE14124

    EECS141 24Lecture #20

    Manchester Carry ChainManchester Carry Chain

    G2

    C3

    G3Ci,0

    P0

    G1

    VDD

    G0

    P1 P2 P3

    C3C2C1C0

  • EE14125

    EECS141 25Lecture #20

    CarryCarry--Bypass AdderBypass Adder

    FA FA FA FA

    P0 G1 P0 G1 P2 G2 P3 G3

    Co,3Co,2Co,1Co,0Ci,0

    FA FA FA FA

    P0 G1 P0 G1 P2 G2 P3 G3

    Co,2Co,1Co,0Ci,0

    Co,3

    Mul

    tiple

    xer

    BP=PoP1P2P3

    Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else kill or generate.

    Also called Carry-Skip

    EE14126

    EECS141 26Lecture #20

    CarryCarry--Bypass Adder (cont.)Bypass Adder (cont.)

    Carrypropagation

    SetupBit 03

    Sum

    M bits

    tsetup

    tsum

    Carrypropagation

    SetupBit 47

    Sum

    tbypass

    Carrypropagation

    SetupBit 811

    Sum

    Carrypropagation

    SetupBit 1215

    Sum

    tadder = tsetup + (M-1)tcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

    EE14127

    EECS141 27Lecture #20

    Carry Ripple versus Carry BypassCarry Ripple versus Carry Bypass

    N

    tp

    ripple adder

    bypass adder

    4..8

    EE14128

    EECS141 28Lecture #20

    CarryCarry--Select AdderSelect AdderSetup

    "0" Carry Propagation

    "1" Carry Propagation

    Multiplexer

    Sum Generation

    Co,k-1 Co,k+3

    "0"

    "1"

    P,G

    Carry Vector

    EE14129

    EECS141 29Lecture #20

    Carry Select Adder: Critical Path Carry Select Adder: Critical Path

    0

    1

    Sum Generation

    Multiplexer

    1-Carry

    0-Carry

    Setup

    Ci,0 Co,3 Co,7 Co,11 Co,15

    S03

    Bit 03 Bit 47 Bit 811 Bit 1215

    0

    1

    Sum Generation

    Multiplexer

    1-Carry

    0-Carry

    Setup

    S47

    0

    1

    Sum Generation

    Multiplexer

    1-Carry

    0-Carry 0-Carry

    Setup

    S811

    0

    1

    Sum Generation

    Multiplexer

    1-Carry

    Setup

    S1215

    EE14130

    EECS141 30Lecture #20

    Linear Carry Select Linear Carry Select

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

    S0-3 S4-7 S8-11 S12-15

    Ci,0

    (1)

    (1)

    (5)(6) (7) (8)

    (9)

    (10)

    (5) (5) (5)(5)

  • EE14131

    EECS141 31Lecture #20

    Square Root Carry Select Square Root Carry Select Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Setup

    "0" Carry

    "1" Carry

    Multiplexer

    Sum Generation

    "0"

    "1"

    Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13

    S0-1 S2-4 S5-8 S9-13

    Ci,0

    (4) (5) (6) (7)

    (1)

    (1)

    (3) (4) (5) (6)

    Mux

    Sum

    S14-19

    (7)

    (8)

    Bit 14-19

    (9)

    (3)

    M

    EE14132

    EECS141 32Lecture #20

    Adder Delays Adder Delays -- Comparison Comparison

    Square root select

    Linear select

    Ripple adder

    20 40N

    t p(in

    uni

    t del

    ays)

    600

    10

    0

    20

    30

    40

    50

    EE14133

    EECS141 33Lecture #20

    Logarithmic (Tree) Adders Logarithmic (Tree) Adders Basic Basic IdeaIdeaLook ahead across groups of multiple bits to figure out the carry

    Example with two bit groups:P1:0 = P1P0, G1:0 = G1 + P1G0, Cout1 = G1:0 + P1:0Cin

    Combine these groups in a tree structure:Delay is now ~log2(N) Instead of ~N

    P7, G7PGP6, G6

    P5, G5P4, G4

    P3, G3PGP2, G2

    P1, G1PGP0, G0

    PG

    PG

    P7:6, G7:6

    P5:4, G5:4

    PG

    P3:2, G3:2

    P1:0, G1:0

    PG

    P7:4, G7:4

    P3:0, G3:0

    P7:0, G7:0

    EE14134

    EECS141 34Lecture #20

    Rest of the TreeRest of the TreePrevious picture shows only half of the algorithm

    Need to generate carries at individual bit positions too

    P7, G7

    P6, G6P5, G5

    P4, G4P3, G3

    P2, G2P1, G1

    P0, C0 C0

    C1PG

    C2

    PG

    PG

    PG PG

    C

    PG C3

    PG C7

    C C4

    C C5C C6

    EE14135

    EECS141 35Lecture #20

    Many Kinds of Tree AddersMany Kinds of Tree AddersMany ways to construct these tree (or carry lookahead) adders

    Many of these variations named after the people who first came up with them

    Most of these vary three basic parameters:Radix: how many bits are combined in each PG gate

    Previous example was radix 2; often go up to radix 4

    Tree Depth: how many stages of logic you go through to get the final carry. Must be at least logRadix(N)Fanout: Maximum logical branching in the tree

    EE14136

    EECS141 36Lecture #20

    Tree AddersTree Adders

    (A0,

    B0)

    (A1,

    B1)

    (A2,

    B2)

    (A3,

    B3)

    (A4,

    B4)

    (A5,

    B5)

    (A6,

    B6)

    (A7,

    B7)

    (A8,

    B8)

    (A9,

    B9)

    (A10

    , B10

    )

    (A11

    , B11

    )

    (A12

    , B12

    )

    (A13

    , B13

    )

    (A14

    , B14

    )

    (A15

    , B15

    )

    S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10

    S 11

    S 12

    S 13

    S 14

    S 15

    Brent-Kung Tree

  • EE14137

    EECS141 37Lecture #20

    Tree AddersTree Adders

    16-bit radix-2 Kogge-Stone tree

    (A0,

    B0)

    (A1,

    B1)

    (A2,

    B2)

    (A3,

    B3)

    (A4,

    B4)

    (A5,

    B5)

    (A6,

    B6)

    (A7,

    B7)

    (A8,

    B8)

    (A9,

    B9)

    (A10

    , B10

    )

    (A11

    , B11

    )

    (A12

    , B12

    )

    (A13

    , B13

    )

    (A14

    , B14

    )

    (A15

    , B15

    )

    S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10

    S 11

    S 12

    S 13

    S 14

    S 15

    EE14138

    EECS141 38Lecture #20

    Tree AddersTree Adders

    (a0,

    b 0)

    (a1,

    b 1)

    (a2,

    b 2)

    (a3,

    b 3)

    (a4,

    b 4)

    (a5,

    b 5)

    (a6,

    b 6)

    (a7,

    b 7)

    (a8,

    b 8)

    (a9,

    b 9)

    (a10

    , b10

    )

    (a11

    , b11

    )

    (a12

    , b12

    )

    (a13

    , b13

    )

    (a14

    , b14

    )

    (a15

    , b15

    )

    S1

    S3

    S5

    S7

    S9

    S11

    S13

    S15

    S0

    S2

    S4

    S6

    S8

    S10

    S12

    S14

    16-bit radix-2 sparse tree with sparseness of 2

    EE14139

    EECS141 39Lecture #20

    Tree AddersTree Adders

    (a0,

    b0)

    (a1,

    b1)

    (a2,

    b2)

    (a3,

    b3)

    (a4,

    b4)

    (a5,

    b5)

    (a6,

    b6)

    (a7,

    b7)

    (a8,

    b8)

    (a9,

    b9)

    (a10

    , b10

    )

    (a11

    , b11

    )

    (a12

    , b12

    )

    (a13

    , b13

    )

    (a14

    , b14

    )

    (a15

    , b15

    )

    S0

    S1

    S2

    S3

    S4

    S5

    S6

    S7

    S8

    S9

    S10

    S11

    S12

    S13

    S14

    S15

    16-bit radix-4 Kogge-Stone Tree

    EE14140

    EECS141 40Lecture #20

    Next LectureNext Lecture

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