lecture20-energy cntdbwrcs.eecs.berkeley.edu/classes/icdesign/ee141_s09/lectures/lectu… · ee141...

EE141

1

EE141 EECS141 1 Lecture #20


  Project Phase 2 posted   Questions?

EE141

2


 Last lecture  Dynamic Logic/Energy

 Today’s lecture   Energy and Power  Memory Cells

 Reading (Ch 6/12)


EE141

3


  Energy consumed in N cycles, EN:

EN = CL • VDD2 • n0→1

n0→1 – number of 0→1 transitions in N cycles


EE141

4


A B Out 0 0 1 0 1 0 1 0 0 1 1 0

Example: Static 2-input NOR Gate

Assume signal probabilities pA=1 = 1/2 pB=1 = 1/2

Then transition probability p0→1 = pOut=0 x pOut=1

= 3/4 x 1/4 = 3/16

α0→1 = 3/16

If inputs switch every cycle


A B Out 0 0 1 0 1 1 1 0 1 1 1 0

Example: Static 2-input NAND Gate



= 3/4 x 1/4 = 3/16

α0→1 = 3/16

If inputs switch every cycle

EE141

5


A B Out 0 0 0 0 1 1 1 0 1 1 1 0

Example: Static 2-input XOR Gate



=

α0→1 =

If inputs switch in every cycle


In1

In2 PDN

In3

Me

Mp

CLK

CLK

Out CL

Power only dissipated when previous Out = 0

EE141

6


A B Out 0 0 1 0 1 0 1 0 0 1 1 0

Dynamic 2-input NOR Gate

Assume signal probabilities PA=1 = 1/2 PB=1 = 1/2

Then transition probability P0→1 = Pout=0 x Pout=1

= 3/4 x 1 = 3/4

Switching activity always higher in dynamic gates! P0→1 = Pout=0


 Always switches  Often consumes 25-50% of total power  Clock gating commonly employed

EE141

7


P(Z = 1) = P(B = 1) . P(X = 1 | B=1)

Becomes complex and intractable fast


Logic without reconvergent fanout

Logic with reconvergent fanout

p0→1 = (1 – pApB) pApB P(Z = 1) = p(C=1 | B=1) p(B=1)

p0→1 = 0

  Need to use conditional probabilities to model inter-signal correlations

  CAD tools best for performing such analysis

EE141

8


ABC 101 000 X Z

Gate Delay Also known as

dynamic hazards

The result is correct, but there is extra power dissipated


EE141

9


  Most important idea: reduce waste   Examples:

  Don’t switch capacitors you don’t need to – Clock gating, glitch elimination, logic re-structuring

  Don’t run circuits faster than needed –  Power α VDD

2 – can save a lot by reducing supply for circuits that don’t need to be as fast

–  Parallelism falls into this category

  Let’s say we do a good job of that – then what?


  Plot all possible designs on a 2-D plane   No matter what you do, can never get below/to the

right of the solid line   This line is called “Pareto Optimal Curve”

  Usually (always) follows law of diminishing returns

Performance

Ener

gy/o

p

EE141

10


  Instead of metrics like EDP, this curve often provides information more directly   Ex1: What is minimum energy for XX performance?   Ex2: Over what range of performance is a new

technique (dotted line) actually beneficial?

Performance En

ergy

/op


EE141

11


Row

Dec

oder

Bit line2L!K

Word line

AK

AK"1

AL!1

A0

M.2K

AK!1

Sense amplifiers / Drivers

Column decoder

Input-Output(M bits)

Storage cell


•  If D is high, D_b will be driven low •  Which makes D stay high

•  Positive feedback

EE141

12


Vo1

Vi1

A

C

B

Vi2

! V

o1

Vo2

Vi2

! V

o1

Vi1 ! Vo2

Vi1 Vo2

Vo2 ! Vi1

Vo1 ! Vi2

(b)

(a)


Access transistor must be able to overpower the feedback

EE141

13



Complementary data values are written (read) from two sides

EE141

14

EE141 EECS141 27 Lecture #20 EE141

WL

BL

V DD

M 5 M 6

M 4

M 1

M 2

M 3

BL

Q Q


0 1

•  Q_b will get pulled up when WL first goes high •  Reading the cell should not destroy the stored value

Read

EE141

15


WL

BL V DD

M 5 M 6

M 4

M 1 V DD V DD V DD

BL Q = 1 Q = 0

C bit C bit


0 0

0.2 0.4 0.6 0.8

1 1.2

0.5 1 1.2 1.5 2 Cell Ratio (CR)

2.5 3

Volta

ge R

ise

(V)

EE141

16


BL = 1 BL = 0

Q = 0 Q = 1

M 1

M 4

M 5 M 6

V DD

V DD WL


EE141

17



EE141

18


 ST/Philips/Motorola

Access Transistor

Pull down Pull up


Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem

M 3

R L R L V DD

WL

Q Q

M 1 M 2

M 4

BL BL

EE141

19


No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V WWL -V Tn

WWL BL 1

M 1 X M 3

M 2 C S

BL 2

RWL

V DD V DD - V T

D V V DD - V T BL 2 BL 1 X RWL WWL


BL2 BL1 GND

RWL

WWL

M3

M2

M1

WWL BL 1

M 1 X M 3

M 2 C S

BL 2

RWL

EE141

20


Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.

Δ V BL V PRE – V BIT V PRE – C S C S C BL + ------------ = = V

M1

CS

WL

BL

CBL

VDD ! VT

WL

X

sensing

BL

GND

Write 1 Read 1

VDD

VDD/2 VDD/2


Uses Polysilicon-Diffusion Capacitance Expensive in Area

M 1 word line

Diffused bit line

Polysilicon gate

Polysilicon plate

Capacitor

Cross-section Layout

Metal word line

Poly

SiO 2

Field Oxide n + n + Inversion layer induced by plate bias

Poly

EE141

21



Cell Plate Si

Capacitor Insulator

Storage Node Poly

2nd Field Oxide

Refilling Poly

Si Substrate

Trench Cell Stacked-capacitor Cell

Capacitor dielectric layer Cell plate Word line

Insulating Layer

Isolation Transfer gate Storage electrode

lecture20-energy cntdbwrcs.eecs.berkeley.edu/classes/icdesign/ee141_s09/lectures/lectu… · ee141...

Documents