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EE141 EECS141 1 Lecture #20

EE141 EECS141 2 Lecture #20

  Midterm 2 on We April 7 6:30-8pm in 277 Cory   Open book.   Covers everything until Lecture 17 (DOMINO

LOGIC). Registers and timing NOT included.   Review Session: Tu April 6 6:30-8pm in 289

Cory   DO NOT FORGET THE PROJECT!

  Extra office hours of TAs on Mo and Tu (during lab hours) in 353 Cory

  Project Phase 1 has been graded. Results will be posted early next week.

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EE141 EECS141 3 Lecture #20

 Last lecture   Timing

 Today’s lecture   Technology Scaling

 Reading (Ch 5)

EE141 EECS141 4 Lecture #20

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EE141 EECS141 5 Lecture #20

Cycle time (max): TClk > tclk-q + tlogic + tsetup

Race margin (min): thold < tclk-q,min + tlogic,min

tclk-q tclk-q,min

tlogic tlogic,min

tsetup, thold

EE141 EECS141 6 Lecture #20

If launching edge is late and receiving edge is early, the data will not be too late if:

Minimum cycle time is determined by the maximum delays through the logic

tclk-q + tlogic + tsetup < TCLK – tJS,1 – tJS,2 + δ

tclk-q + tlogic + tsetup - δ + 2tJS < TCLK

Skew can be either positive or negative

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EE141 EECS141 7 Lecture #20

Minimum logic delay

If launching edge is early and receiving edge is late:

tclk-q,min + tlogic,min – tJS,1 > thold + tJS,2 + δ

tclk-q,min + tlogic,min > thold + 2tJS+ δ (This assumes jitter at launching and receiving clocks are independent – which usually is not true)

EE141 EECS141 8 Lecture #20

Reference Pipelined

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EE141 EECS141 9 Lecture #20

EE141 EECS141 10 Lecture #20

(Domino logic almost always uses latch-based clocking)

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EE141 EECS141 11 Lecture #20

  In a flip-flop based system:   Data launches on one rising edge

–  And must arrive before next rising edge   If data arrives late, system fails

–  If it arrives early, wasting time   Flip-flops have hard edges

  In a latch-based system:   Data can pass through latch while it is transparent   Long cycle of logic can borrow time into next cycle

–  As long as each loop finished in one cycle

EE141 EECS141 12 Lecture #20

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EE141 EECS141 13 Lecture #20

  Flip-flops generally easier to use   Most digital ASICs designed with register-based

timing   But, latches (both pulsed and level-sensitive)

allow more flexibility   And hence can potentially achieve higher

performance   Latches can also be made more tolerant of clock

un-certainty   More in EE241

EE141 EECS141 14 Lecture #20

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EE141 EECS141 15 Lecture #20

 Make things cheaper:  Want to sell more functions (transistors)

per chip for the same money  Or build same products cheaper   Price of a transistor has to be reduced

 But also want to be faster, smaller, lower power…

EE141 EECS141 16 Lecture #20

  Benefits of 30% “Dennard” scaling (1974):   Double transistor density   Reduce gate delay by 30% (increase operating

frequency by 43%)   Reduce energy per transition by 65% (50% power

savings @ 43% increase in frequency)   Die size used to increase by 14% per

generation (not any more)   Technology generation spans 2-3 years

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EE141 EECS141 17 Lecture #20

EE141 EECS141 18 Lecture #20

2X reduction every ~5 years

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EE141 EECS141 19 Lecture #20

EE141 EECS141 20 Lecture #20

tp decreases by 30%/year f increases by 43%

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EE141 EECS141 21 Lecture #20 From Kuroda

EE141 EECS141 22 Lecture #20

• Full Scaling (Constant Electrical Field)

• Fixed Voltage Scaling

• General Scaling

ideal model — dimensions and voltages scale together by the same factor S

most common model until 1990’s only dimensions scale, voltages remain constant

most realistic for today’s situation — voltages and dimensions scale with different factors

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EE141 EECS141 23 Lecture #20

EE141 EECS141 24 Lecture #20

  W, L, tox: 1/S   VDD, VT: 1/S

  Area: WL   Cox: 1/tox   CL: CoxWL   ID: Cox(W/L)(VDD-VT)2

  Req: VDD/IDSAT

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EE141 EECS141 25 Lecture #20

  W, L, tox: 1/S   VDD, VT: 1/S

  tp: ReqCL

  Pavg: CLVDD2/tp

  Pavg/A: CoxVDD2/tp

EE141 EECS141 26 Lecture #20

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EE141 EECS141 27 Lecture #20

  W, L, tox: 1/S   VDD, VT: 1/S

  Area: WL   Cox: 1/tox   CL: CoxWL   ID: WCoxvsat(VDD-VT-VVSAT/2)

  Req: VDD/IDSAT

EE141 EECS141 28 Lecture #20

  W, L, tox: 1/S   VDD, VT: 1/S

  tp: ReqCL

  Pavg: CLVDD2/tp

  Pavg/A: CoxVDD2/tp

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EE141 EECS141 29 Lecture #20

EE141 EECS141 30 Lecture #20

  What will did cause this model to break?   Leakage set by kT/q

–  Temp. does not scale –  VT set to minimize power

  Power actually increased –  Leakage increased drastically –  f increased faster than device speed – Hit cooling limit

  Process Variation – Hard to build very small things accurately (less

averaging)