EE141

1

EE141 EECS141 1 Lecture #12

EE141 EECS141 2 Lecture #12

  HW 5 posted – due in two weeks   No re-grades on MT1 after Wednesday   Project to be launched in week 7 – stay tuned

EE141

2

EE141 EECS141 3 Lecture #12

B

D

G

ID

S

for VGT ≤ 0: ID = 0

with VDS,eff = min (VGT, VDS, VD,VSAT)

for VGT ≥ 0:

define VGT = VGS – VT

EE141 EECS141 4 Lecture #12

-4

0 0.5 1 1.5 2 2.5 0

0.5

1

1.5

2

2.5 x 10

Velocity Saturation

VDS (V)

I D (A

)

VDS = VGT

VGT = VD,VSAT

Saturation

Linear

VDS = VD,VSAT

  Define VGT = VGS – VT, VD,VSAT = ξc·L

EE141

3

EE141 EECS141 5 Lecture #12

EE141 EECS141 6 Lecture #12

= CGCS + CGSO = CGCD + CGDO

= CGCB = Cdiff

G

S D

B

= Cdiff

EE141

4

EE141 EECS141 7 Lecture #12

 Capacitance (per area) from gate across the oxide is W·L·Cox, where Cox=εox/tox

EE141 EECS141 8 Lecture #12

 Distribution between terminals is complex  Capacitance is really distributed

– Useful models lump it to the terminals   Several operating regions:

– Way off, off, transistor linear, transistor saturated

EE141

5

EE141 EECS141 9 Lecture #12

 When the transistor is off, no carriers in channel to form the other side of the capacitor. – Substrate acts as the other capacitor terminal – Capacitance becomes series combination of gate

oxide and depletion capacitance

EE141 EECS141 10 Lecture #12

 When |VGS| < |VT|, total CGCB much smaller than W·L·Cox – Usually just approximate with CGCB = 0 in this region.

  (If VGS is “very” negative (for NMOS), depletion region shrinks and CGCB goes back to ~W·L·Cox)

EE141

6

EE141 EECS141 11 Lecture #12

 Channel is formed and acts as the other terminal – CGCB drops to zero (shielded by channel)

 Model by splitting oxide cap equally between source and drain – Changing either voltage changes the channel charge

EE141 EECS141 12 Lecture #12 12

 Changing source voltage doesn’t change VGC uniformly – E.g. VGC at pinch off point still VTH

  Bottom line: CGCS ≈ 2/3·W·L·Cox

EE141

7

EE141 EECS141 13 Lecture #12

 Drain voltage no longer affects channel charge – Set by source and VDS_sat

  If change in charge is 0, CGCD = 0

EE141 EECS141 14 Lecture #12

Cgate vs. VGS (with VDS = 0)

Cgate vs. operating region

EE141

8

EE141 EECS141 15 Lecture #12 15

Off/Lin/Sat CGSO = CGDO = CO·W

EE141 EECS141 16 Lecture #12

 COV not just from metallurgic overlap – get fringing fields too

  Typical value: ~0.2fF·W(in µm)/edge

n + n +

Cross section

n + n +

Cross section

Fringing fields

EE141

9

EE141 EECS141 17 Lecture #10

Bottom

Side wall

Side wall Channel

Source

Substrate

W

NA+

NA LS

ND

xj

  Bottom – Area cap – Cbottom = Cj·LS·W

  Sidewalls – Perimeter cap – Csw = Cjsw·(2LS+W)

 GateEdge – Cge = Cjgate·W – Usually automatically included in the SPICE model

EE141 EECS141 18 Lecture #10

  SPICE model equations:

–  Area CJ = area × CJ0 / (1+ |VDB|/φΒ)mj

–  Perimeter CJ = perim × CJSW / (1 + |VDB|/φΒ)mjsw

–  Gate edge CJ = W × CJgate / (1 + |VDB|/φΒ)mjswg

  How do we deal with nonlinear capacitance?

  Junction caps are nonlinear

–  CJ is a function of junction bias

EE141

10

EE141 EECS141 19 Lecture #10

Replace non-linear capacitance by large-signal equivalent linear capacitance

which displaces equal charge over voltage swing of interest

EE141 EECS141 20 Lecture #10

  Gate-Channel Capacitance   CGC ≈ 0 (|VGS| < |VT|)   CGC = Cox·W·Leff (Linear)

–  50% G to S, 50% G to D   CGC = (2/3)·Cox·W·Leff (Saturation)

–  100% G to S

  Gate Overlap Capacitance   CGSO = CGDO = CO·W (Always)

  Junction/Diffusion Capacitance   Cdiff = Cj·LS·W + Cjsw·(2LS + W) + CjgW (Always)

EE141

11

EE141 EECS141 21 Lecture #10

EE141 EECS141 22 Lecture #10

EE141

12

EE141 EECS141 23 Lecture #10

V in V out

V DD

Wp = βWn

Wn

EE141 EECS141 24 Lecture #10

  For DC VTC, IDn = IDp   Graphically, looking for intersections of NMOS and

PMOS IV characteristics   To put IV curves on the same plot, PMOS IV is

“flipped” since |VDSp| = VDD – Vout   Also, |VGSp| = Vdd - Vin I

IDp

VGSp ! "1

VGSp ! "2.5

VDSp

IDnVin ! 0

Vin ! 1.5

VDSp

IDnVin ! 0

Vin ! 1.5

Vout

Vin ! VDD # VGSpIDn ! "IDp

Vout ! VDD # VDSp

EE141

13

EE141 EECS141 25 Lecture #10

Vin ! 0.6

Vin ! 0

Vout

Vin ! 1

Vin ! 2

Vin ! 1.5

Vin ! 1

Vin ! 1

Vin ! 1.5

Vin ! 0.5

Vin ! 0IDn

Vin ! 2.5

Vin ! 1.9

Vin ! 1.5

Vin ! 2.5

NMOSPMOS

EE141 EECS141 26 Lecture #10

0.5

0.5

1

1.5

2

2.5

1 1.5 2 2.5

NMOS resPMOS off

NMOS resPMOS sat

NMOS satPMOS sat

NMOS satPMOS res

NMOS offPMOS res

Vin

Vout

EE141

14

EE141 EECS141 27 Lecture #10

10 0 10 1 0.8 0.9

1

1.1 1.2 1.3

1.4 1.5 1.6

1.7 1.8

M

V (V

)

W p /W n

EE141 EECS141 28 Lecture #10

10 0 10 1 0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

M

V (V

)

W p /W n

EE141

15

EE141 EECS141 29 Lecture #10

A simplified approach

Vin

VM

VILVOL

VOH

Vout

VIH

EE141 EECS141 30 Lecture #10

Gain=-1

EE141

16

EE141 EECS141 31 Lecture #10

0 0.5 1 1.5 2 2.5 0

0.5

1

1.5

2

2.5

V in (V)

V out (V

) Wider PMOS

Wider NMOS

Symmetrical

EE141 EECS141 32 Lecture #10

0 0.5 1 1.5 2 2.5 0

0.5

1

1.5

2

2.5

V in (V)

V out (V

)

Fast PMOS Slow NMOS

Fast NMOS Slow PMOS

Nominal