assignment #1 due today! assignment #2 to be posted right...

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EE141 EECS141 1 Lecture #4


  Assignment #1 due today!   Assignment #2 to be posted right thereafter   DIS 101 (Th 11am-noon) in GPB (Genetics

and Plant Biology) 107 starting next week   Office hours of TAs in 557 Cory   Labs start next week (Monday)

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 Last lecture   Basic metrics for IC design  Manufacturing

 Today’s lecture  Design Rules   Introduction to switch logic

 Reading (2.3, 3.3.1-3.3.2)


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(well contacts)

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  Interface between designer and process engineer

  Guidelines for constructing process masks   Unit dimension: Minimum line width

  scalable design rules: lambda parameter   absolute dimensions (micron rules)


 Intra-layer  Widths, spacing, area

 Inter-layer   Enclosures, distances, extensions,

overlaps  Special rules (sub-0.25µm)

  Antenna rules, density rules, (area)

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•  Dimensionless layout entities •  Only topology is important

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Polysilicon In Out

V DD

GND

PMOS 2λ

Metal 1

NMOS

Contacts

N Well

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Connect in Metal

Share power and ground

Abut cells


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|VGS|

An MOS Transistor

|VGS| ≥ |VT|

S D

Ron

A Switch!

S D

G


|VGS|

S D

G

|VGS| < |VT| |VGS| > |VT|

Ron

S D S D

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|VGS|

S D

G

|VGS| < |VT| |VGS| > |VT|

Ron

S D

Roff

S D


VGS > 0

S D

G

VGS < 0

S D

G

NMOS Transistor PMOS Transistor

Y=Z IF X=1 Y=Z IF X=0

Y Z

Ron X

Y Z

Ron X

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V in V out

C L

V DD

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VOL = 0 VOH = VDD

VM = f(Rn, Rp)

V DD V DD

V in = V DD V in = 0

V out V out

R n

R p


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 VOH =  VOL =  VIL =  VIH =  NMH =  NML =  VM =


 VOH = VDD = 2.5V  VOL = 0V  VM = 1.2V  VIL = 1.05V  VIH = 1.45V  NMH =1.05V  NML = 1.05V

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t pHL = f(RonCL) = 0.69 R n C L

(a) Low-to-high (b) High-to-low


  Full rail-to-rail swing   Symmetrical VTC   Propagation delay function of load

capacitance and resistance of transistors   No static power dissipation   Direct path current during switching

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0 → ?

CL

VDD

0 → VDD

S

D

VGS

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VDD

0 → ?

CL

0 → ?

CL

VDD

VDD S

D S

D

VGS

VDD → ?

CL VDD

VDD → ?

CL

S

S D

D

VGS

VGS

VGS


CL

In Out

  For some given CL:   How many stages are needed to minimize delay?   How to size the inverters?

  Anyone want to guess the solution?

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 Get fastest delay if build one very big inverter   So big that delay is set only by self-loading

 Likely not the problem you’re interested in   Someone has to drive this inverter…


 Need to have a set of constraints

 Constraints key to:  Making the result useful  Making the problem have a ‘clean’ solution

 For sizing problem:  Need to constrain size of first inverter

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  You are given:   A fixed number of inverters   The size of the first inverter   The size of the load that needs to be driven

  Your goal:   Minimize the delay of the inverter chain

  Need model for inverter delay vs. size


tpHL = (ln 2) RNCL tpLH = (ln 2) RpCL Delay:

2W

W

  Assume we want equal rise/fall delays tpHL = tpLH   Need approximately equal resistances, RN = RP

  PMOS approximately 2 times larger resistance for same size;

  Must make PMOS 2 times wider, WP = 2WN = 2W   tp = (ln 2) (Rinv/W) CL with Rinv resistance of

minimum size NMOS

Loading on the previous stage: Cin = WCginv = W(3CG)

CP = 2WCg

CN = WCg

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Cint CL

Replace ln(2) with k (a constant): Delay = kR(Cint + CL)

Delay = k(Rmin/W)(WCdinv + CL)

2W

W

R = Rinv/W Cint = W(3Cd) = WCdinv


Load

Delay

Delay = kR Cin(Cint/Cin+ CL /Cin) = kRminCginv[Cdinv/Cginv + CL/(WCginv)] = Delay (Internal) + Delay (Load) Cdinv/Cginv = γ = Constant independent of size

Cint CL

Cin 2W

W

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Cint = γ Cin (γ ≈ 1 for CMOS inverter) f = CL/Cin – electrical fanout tinv = kRminCginv

tinv is independent of sizing of the gate!!!

assignment #1 due today! assignment #2 to be posted right...

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