ee141-fall 2007 homework #2 feedback digital...

EE1411

EECS141 1Lecture #10

EE141EE141--Fall 2007Fall 2007Digital Integrated Digital Integrated CircuitsCircuits

Lecture 10Lecture 10CMOS ScalingCMOS ScalingWiresWires

EE1412


AnnouncementsAnnouncements

Lab 4 this weekNo lab next week

Homework #5 due next ThursdayMidterm 1 next Thursday!

105 Northgate, 6:30-8:00pm– No 10 min delay – show up on time!

Material until today’s lecture, homework 5, lab 4Review session in Tuesday’s lecture

– Prepare your questionsNo labs, no new homework next week

EE1413


Class MaterialClass Material

Last lectureBuffer sizing

Today’s lectureScalingWires

Reading (5.5, Chapter 4)

EE1414


Homework #2 feedbackHomework #2 feedbackSimulation is not a substitute for thinking!

Garbage in, garbage out

Always check if your sim result makes senseChange parameters you think shouldn’t affect your result, and make sure they don’t.

Example: “step inputs”If delay you measured was close to the “step” rise timeBetter check your risetime

– You probably don’t really have a “step”

EE1415


Homework #2 feedbackHomework #2 feedback

tp,avg = (tpHL + tpLH)/2

If unsure what we want you to do in a problem, ask us

E.g., in problem 1, don’t assume that you can just eyeball the VTC curve

EE1416


Impact ofImpact ofTechnology ScalingTechnology Scaling

EE1417


Goals of Technology ScalingGoals of Technology Scaling

Make things cheaper:Want to sell more functions (transistors) per chip for the same moneyOr build same products cheaperPrice of a transistor has to be reduced

But also want to be faster, smaller, lower power

EE1418


Technology ScalingTechnology ScalingBenefits of 30% “Dennard” scaling (1974):

Double transistor density Reduce gate delay by 30% (increase operating frequency by 43%)Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency)

Die size used to increase by 14% per generation (not any more)Technology generation spans 2-3 years

EE1419


Technology Scaling (1)Technology Scaling (1)

Minimum Feature SizeMinimum Feature Size1960 1970 1980 1990 2000 2010

10-2

10-1

100

101

102

Year

Min

imum

Fea

ture

Siz

e (m

icro

n)

2X reduction every ~5 years

EE14110


Technology Scaling (2) Technology Scaling (2)

Number of components per chipNumber of components per chip

EE14111



Propagation DelayPropagation Delay

tp decreases by 30%/yearf increases by 43%

EE14112



(a) Power dissipation vs. year.

959085800.01

0.1

1

10

100

Year

Pow

er D

issi

patio

n (W

)

x4 / 3 year

s

MPU DSP

x1.4 / 3 years

Scaling Factor κ �inormalized by 4µm design rule�j

1011

10

100

1000

∝ κ 3

Pow

er D

ensi

ty (m

W/m

m2 )

∝ κ 0.7

(b) Power density vs. scaling factor.

From Kuroda

EE14113


Technology Scaling Models Technology Scaling Models • Full Scaling (Constant Electrical Field)

• Fixed Voltage Scaling

• General Scaling

ideal model — dimensions and voltage scaletogether by the same factor S

most common model until 1990’sonly dimensions scale, voltages remain constant

most realistic for today’s situation —voltages and dimensions scale with different factors

EE14114


ScalingScalingL

x

LD

L/S

x/S

LD/S

L

W

L/S

W/S

EE14115


Full Scaling (Full Scaling (DennardDennard, Long, Long--Channel)Channel)

W, L, tox: 1/S VDD, VT: 1/S

Area: WLCox: 1/toxCL: CoxWLID: Cox(W/L)(VDD-VT)2

Req: VDD/IDSAT

EE14116


Full Scaling (Full Scaling (DennardDennard, Long, Long--Channel)Channel)


tp: ReqCL

Pavg: CLVDD2/tp

Pavg/A: CoxVDD2/tp

EE14117


Scaling Relationships for Long Channel DevicesScaling Relationships for Long Channel Devices

EE14118


Full Scaling (Full Scaling (DennardDennard, Short, Short--Channel)Channel)


Area: WLCox: 1/toxCL: CoxWLID: WCoxvsat(VDD-VT-VVSAT/2)Req: VDD/IDSAT

EE14119


Full Scaling (Full Scaling (DennardDennard, Short, Short--Channel)Channel)


tp: ReqCL

Pavg: CLVDD2/tp

Pavg/A: CoxVDD2/tp

EE14120


Transistor ScalingTransistor Scaling(Velocity(Velocity--Saturated Devices)Saturated Devices)

EE14121


An interesting questionAn interesting questionWhat will did cause this model to break?

Leakage set by kT/q– Temp. does not scale– VT set to minimize power

Power actually increased– Leakage increased drastically– f increased faster than device speed– Hit cooling limit

Process Variation– Hard to build very small things accurately (less

averaging)

EE14122


WiresWires

EE14123


The WireThe Wire

PhysicalSchematic

EE14124


Wire ModelsWire Models

All-inclusive model Capacitance-only

EE14125


Impact of Interconnect Impact of Interconnect ParasiticsParasiticsInterconnect and its parasitics can affect all of the metrics we care about

Cost, reliability, performance, power consumption

Parasitics associated with interconnect:CapacitanceResistanceInductance

EE14126


Interconnect Length DistributionInterconnect Length Distribution

From Magen et al., “Interconnect Power Dissipation in a Microprocessor”

SLocal = STechnology

SGlobal = SDie

EE14127


INTERCONNECTINTERCONNECT

EE14128


Capacitance: The Parallel Plate ModelCapacitance: The Parallel Plate Model

Dielectric

Substrate

L

W

H

tdi

Electrical-field lines

Current flow

WLt

cdi

diint

ε= 1 ( / is constant)CwireL L

SS Cwire LengthS S S

= =⋅

EE14129


PermittivityPermittivity

EE14130


Fringing CapacitanceFringing Capacitance

W - H/2H

+

(a)

(b)

EE14131


Fringing versus Parallel PlateFringing versus Parallel Plate

(from [Bakoglu89])

EE14132


InterwireInterwire CapacitanceCapacitance

fringing parallel

EE14133


Capacitive coupling and noiseCapacitive coupling and noise

EE14134


Coupling Capacitance and DelayCoupling Capacitance and Delay

EE14135



EE14136



EE14137


Impact of Impact of InterwireInterwire CapacitanceCapacitance

(from [Bakoglu89])

EE14138


Wiring Capacitances (0.25 Wiring Capacitances (0.25 µµm CMOS)m CMOS)

EE14139


Wiring CapacitancesWiring Capacitances

EE14140


Next LectureNext Lecture

Finish wire modelingStart CMOS logic

ee141-fall 2007 homework #2 feedback digital...

Documents