EE141

1

EE1411

Tu-Th 5pm-6:30pm150 GSPP

EE141- Spring 2007Introduction to Digital

Integrated Circuits

EE1412

What is this class about?

Introduction to digital integrated circuits.» CMOS devices and manufacturing technology.

CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies.

What will you learn?» Understanding, designing, and optimizing digital

circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability

EE141

2

EE1413

Digital Integrated Circuits

Introduction: Issues in digital designThe CMOS inverterCombinational logic structuresSequential logic gates; timingArithmetic building blocksInterconnect: R, L and CMemories and array structuresDesign methods

EE1414

Interludium: Administrativia

Instructor

Andrei Vladimirescuandrei@eecs.berkeley.eduOffice hours: 511 Cory

Tu 2:45-4:45pm

Kenny DuongDiscussion + labkeduong@berkeley.eduOffice Hours: TBD

TBDDiscussion + lab???@eecs.berkeley.eduOffice Hours: TBD

The TAs

ReaderTBD

EE141

3

EE1415

The Web-Site

Class and lecture notesAssignments and solutionsLab and project informationExamsMany other goodies …

The sole source of informationhttp://bwrc.eecs.berkeley.edu/Classes/ee141

Save a tree!

EE1416

Class Admission

No enrollment issues. Everyone will be accommodated (hopefully)!

Make sure your name is on the class roll!

EE141

4

EE1417

Discussions and Labs

Discussion sessions» Mo 2-3pm, 293 Cory» We 3-4pm, 521 Cory» Pick any of the two (they are covering the same material)

Labs (353 Cory)» Mo 1-4pm» We 11am-2pm» F 2-5pm» Pick the one that fits you the best (pending availability) and

STICK TO IT!

EE141 8

TAmtng

M

T

W

R

F

8 9 10 11 12 1 2 3 4 5 6Lab(?)

353 Cory

Lab()

353 Cory

OH(Andrei)511 Cory

DISC*()

521 Cory

DISC*()

293 Cory

Lec(Andrei)

GSPP

ProblemSets Due

Lec(Andrei)

GSPP

* Discussion sections will cover identical material

Your EE141 Week At a Glance

Lab()

353 Cory

EE141

5

EE1419

Class Organization

10 AssignmentsA couple of design projects (1 term project)Labs: 6 software, 1 hardware2 midterms, 1 final» Midterm 1:

– Tu February 20, 6:30-8:00pm, or– Th February 22, 5-6:30pm

» Midterm 2: Tu April 3, 6:30-8:00pm» Final:

– Currently Th May 17, 5-8pm, to be changed to– Mo May 14, time TBA

EE14110

Grading Policy

Homeworks: 10%Labs: 10%Projects: 20%Midterms: 30%Final: 30%

EE141

6

EE14111

Class Material

Textbook: “Digital Integrated Circuits – A Design Perspective,” 2nd Edition, by J. Rabaey, A. Chandrakasan, and B. NikolicLab Reader:Available on the web page!Selected material will be made available from Copy

CentralCheck web page for the availability of tools

EE14112

Software

Cadence software only!» Phased out the Micromagic software.» Online documentation and tutorials

HSPICE and IRSIM(?) for simulation

EE141

7

EE14113

Getting Started

Assignment 1: Getting SPICE to work » see web-page» also “The SPICE Book”, by A. Vladimirescu

NO discussion sessions or labs this week.First discussion sessions in Week 2First Software Lab in Week 3

EE14114

Introduction

Why is designing digital ICs different today than it was before?Will it change in future?

EE141

8

EE14115

The First Computer

The BabbageDifference Engine(1832)25,000 partscost: £17,470

EE14116

ENIAC - The first electronic computer (1946)

EE141

9

EE14117

The Transistor Revolution

First transistorBell Labs, 1948

EE14118

The First Integrated Circuits

Bipolar logic1960’s

ECL 3-input GateMotorola 1966

EE141

10

EE14119

Intel 4004 Micro-Processor

EE14120

Intel Pentium (II) microprocessor

Intel 199810 Mil. Transistors

EE141

11

EE14121

Intel Pentium 4

EE14122

Intel Core 2 Microprocessor

EE141

12

EE14123

Moore’s Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.

He made a prediction that semiconductor technology will double its effectiveness every 18 months

EE14124

Moore’s Law16151413121110

9876543210

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

LOG

2 OF

THE

NU

MB

ER O

FC

OM

PON

ENTS

PER

INTE

GR

ATE

D F

UN

CTI

ON

Electronics, April 19, 1965.

EE141

13

EE14125

Evolution in Complexity

EE14126

Moore’s law in Microprocessors

400480088080

8085 8086286

386486 Pentium® proc

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010Year

Tran

sist

ors

(MT)

2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 years

S. Borkar

EE141

14

EE14127

Moore’s Law - Logic Density

Shrinks and compactions meet density goalsNew micro-architectures drop density

Shrinks and compactions meet density goalsNew micro-architectures drop density

Sour

ce: I

ntelPentium (R)

Pentium Pro (R) 486386

i860

1

10

100

1000

1.5µ

1.0µ

0.8µ

0.6µ

0.35µ

0.25µ

0.18µ

0.13µ

Logi

c D

ensi

ty

2x trend

Logi

c Tr

ansi

stor

s/m

m2

Pentium II (R)

EE14128

Die Size Growth

40048008

80808085

8086286

386486 Pentium ® procP6

1

10

100

1970 1980 1990 2000 2010Year

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years

Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law

S. Borkar

EE141

15

EE14129

Transistor Count

EE14130

Frequency Prediction ~2004

P6Pentium ® proc

48638628680868085

8080800840040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Freq

uenc

y (M

hz)

Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years

Doubles every2 years

S. Borkar

EE141

16

EE14131

Frequency (Today)

EE14132

Power will be a problem

5KW 18KW

1.5KW 500W

4004800880808085

8086286

386486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Pow

er (W

atts

)

Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive

S. Borkar

EE141

17

EE14133

Power Dissipation

EE14134

Processor Power

386 386

486 486

Pentium(R) Pentium(R) MMX

Pentium Pro (R)

Pentium II (R)

1

10

100

1.5µ 1µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ

Max

Pow

er (W

atts

) ?

Lead processor power increases every generationCompactions provide higher performance at lower power

Sour

ce: I

ntel

EE141

18

EE14135

Power density will increase

400480088080

8085

8086

286 386486

Pentium® procP6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Pow

er D

ensi

ty (W

/cm

2)

Hot Plate

NuclearReactor

RocketNozzle

Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp

S. Borkar

EE14136

Not Only Microprocessors

Digital Cellular Market(Phones Shipped)

1996 1997 1998 1999 2000

Units 48M 86M 162M 260M 435M Analog Baseband

Digital Baseband(DSP + MCU)

PowerManagement

Small Signal RF

PowerRF

(data from Texas Instruments)(data from Texas Instruments)

CellPhone

EE141

19

EE14137

Productivity Trends

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

2003

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2005

2007

2009

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000Logic Tr./ChipTr./Staff Month.

xxxx

xx

x21%/Yr. compound

Productivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Logi

c Tr

ansi

stor

per

Chi

p(M

)

0.01

0.1

1

10

100

1,000

10,000

100,000

Prod

uctiv

ity(K

) Tra

ns./S

taff

-Mo.

Source: Sematech

Complexity outpaces design productivity

Com

plex

ity

EE14138

Challenges in Digital Design

“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.

Everything Looks a Little Different

“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.

…and There’s a Lot of Them!

∝ DSM ∝ 1/DSM

?

EE141

20

EE14139

Design Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

EE14140

Why Scaling?

Technology shrinks by 0.7/generationWith every generation can integrate 2x more functions per chip; chip cost does not increase significantlyCost of a function decreases by 2xHow to design chips with more and more functions?Design engineering population does not double every two years…Need to understand different levels of abstraction

EE141

21

EE14141

2010 Outlook

1B transistors on a chip20-30 GHz operation1T operations/sMost formidable challenges» Power» Design complexity

P. Gelsinger, ISSCC2001

EE14142

Next Class

Introduces basic metrics for design of integrated circuits – how to measure delay, power, etc.Brief intro to IC manufacturing and design