digital radio receiver

8/2/2019 Digital Radio Receiver

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Digital Radio Receiver

Amit ManeSystem Engineer


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Introduction

Virtually all digital receivers perform channel access usingDDC

The desired channel is translated using the digital mixer

comprised of multipliers and DDS

The sample rate is then adjusted to match the channelbandwidth

CIC filter

Two poly phase decimators


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Introduction

The functions performed in the system are Waveform synthesis (DDS)

Complex multiplication

Multirate filtering

The overall sample rate change of the DDC is 120 The DDS mixer has a SFDR of 102 dB

The data rate can be upto 208 MHz


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Introduction

Innovative DRR System requires One Quadia

Two UWBs

Number of channels implemented = 40


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Complete System


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Block diagram


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Digital Receiver Block Diagram

A

10channel

s ofI/Q @

1.0833MSPS

16-bit

Clockcircuitry

A/D12-bit

130/208MSPS

A/D12-bit

130/208MSPS

A

B

ClkCIC

30:1

NCO

MixerA/DMux

RegistersA/D input select

Mixer FreqRev Code

StatusGainTest

20 channels of I/Q @4.33 MSPS

32--bit

J4Link

UWB1 of 2

CommandChannel

1 of 20 channels

A/DIntf

A/DIntf

Gain

PCI FPGA

DDR RAM16Mx16

DS

P

QuadiaLogic1 of 2

DSP

CFIR2:1

Overflowdetect

1 of 20channels

Interrupts

Interrupts

Triggering

Spectral

invert

RegisterSpectral Inversion

20-bit

TestMux

TestGenerator

TestMux

Register

Test Controls2-bit

Dual QueueVFIFO

FIFO

RegisterRev Codes

StatusRegisterDCMs locked

Clock DCMIn = DSP1 EMIF Clk

Out = DSP1 EMIF Clk

Clock DCMIn = DSP2 EMIF Clk

Out = DSP2 EMIF Clk

DSP1Registers

DSP2 RegistersDRR FIFO Thresh

J4link

Reset

DataFlow

Controller

Overflowdetect

FIFO

FIFO

10channel

s ofI/Q @

1.0833MSPS

16-bit

FIFO

PFIR

2:1

TestGenerator


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UWB


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Filter Guide

Fs /2= kHz22222

Fpass = kHz222

Fstop2= . kHz222222

Fstop2= kHz1111


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MATLAB Development System


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DDC Frequency Response


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MATLab SimuLink Development

MATLab and Simulink

used with Xilinx SystemGenerator

Simulink gatewaysprovide connection tophysical hardware andconnect with

Framework Logic End-to-end simulation

under MATLab

JTAG link allows realhardware to be testedfrom MATLabenvironment

System Generator linksXilinx tools for chipdesign


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Using Simulink and System Generator

Simulink Block libraries are used to draw the system

Innovative BSP provides blocks for UWB components Simulink blocks for DSP, data generation and viewing

Xilinx System Generator links all blocks

Starting anewdesign!


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Simulink Libraries

Board Support Package for CS includes hardware and signalprocessing components

A/Ds, J4, DDCs ....


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SimuLink Block Diagram

The top level design has the Xilinx System Generator blockfor integration with logic tools

Top LevelDesign


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Xilinx System Generator Integrates withSimulink

Compiling and fitting the design is done directly from the Simulinkenvironment


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Design Using Simulink Blocks and Functions Large libraries of DSP and logic function may be directly used

Drag-n-drop from Simulink libraries


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Validating the Design

Validate the design by including the hardware in the Simulink

Hardware in the loop testing using JTAG

Bit-true and cycle-true testing

The RealHardware

Observe and

analyze realdata insideSimulink

Flow data fromSimulinkthrough thehardware andback to

Simulink


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Design Testing using Simulink

Run real-time or Simulink test data through the actual design

ExecutionControl


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VHDL Development Tools Flow


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Quadia Application Logic Simulation


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Multiple Channel on DSP 0

Ten Channels per DSP


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Multiple Channel Operation

DSP 0

DSP 1

DSP 2

DSP 3


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Spectral Inversion Testing

32.51 MHz Input

32.52 MHz Tunefs = 129.843 MHz

Before Spectral Inversion...

9.7 kHz


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32.51 MHz Input

32.52 MHz Tunefs = 129.843 MHz

After Spectral Inversion...

Spectral Inversion Testing

531 kHz


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Thank you !

digital radio receiver

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