digital system design lec 1a (1)

7/28/2019 Digital System Design Lec 1a (1)

1/92

Adv. Digital System Design

1

ummer

Dr M Umer Munir

Email: [email protected]


2/92

Course Purpose

Provide knowledge and experience in:

Contemporary logic design using an HDL (Verilog)

HDL simulation

Synthesis of structural and behavioral designs

2

Analysis of design tradeoffs

Optimizing hardware designs

Design tools commonly used in industry

Teach you to be able to think hardware


3/92

What You Should Already Know

Digital Logic Design

Computer Architecture

Signals and Systems

3


4/92

Course Materials

Text Book Digital Design of Signal Processing System by Shoab Khan

Feb 2011, John Wiley & Sons

Website www.drshoabkhan.com

4

References Verilog HDL-A guide to digital design and synthesis by

Samir Palnitkar Advanced Digital Design With Verilog HDL by Ciletti,

Michael D.


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Goals

This course is designed to introduce engineers anddesigners advanced digital design concepts.

The students are taught different steps in the designflow of VLSI circuit designing using Verilog.

They will be exposed to converting floating-point

5

algorithms to Fixed point format and then optimallydesigning the HW to implement the algorithm.

After successful completion of the course a studentwill able to design digital systems using RegisterTransfer Level Verilog.


6/92

Topics

High-level digital design methodology using Verilog, Design, Implementation, andVerification

Application requiring HW implementation, Floating-Point to Fixed-PointConversion

Architectures for Basic Buildin Blocks, Adder, Com ression Trees, and

6

Multipliers

Transformation for high speed using pipelining, retiming, and parallel processing,

Dedicated Fully Parallel Architecture, Time shared Architecture, Hardwired StateMachine based Design, Micro Program State Machine based Design

FPGA-based design and logic synthesis


7/92

Grading Criteria

Quizzes 8% ,

Project & assignments to be developed

ALONE: 12%,

7

wo ess ona s:

Final: 50%


8/92

Advancement in VLSI

The advancement and growth in VLSI has been exponential

An interesting comment by Bill Gates:

IfGM had kept up with the technology like the computer

industry has, we would all be driving $25.00 cars that got 1,000 miles to

the gallon.

8


9/92

GM responded (just for fun) If GM had developed technology likeMicrosoft, we would all be driving cars with the following characteristics: 1. Occasionally, executing a maneuver would cause your car to stop

and fail to restart and you'd have to re-install the engine. 2. Occasionally, for no reason whatsoever, your car would lock you

out and refuse to let you in until you simultaneously lifted the doorhandle, turned the key and grabbed hold of the radio antenna.

. ,bought a "Car 95" or a "Car NT". But then you'd have to buy moreseats.

4. The airbag system would say "Are you sure?" before going off. 5. You'd have to press the "Start" button to turn the engine off.

9


10/92

Introduction

Why is designingdigital ICs different

today than it was

10

Will it change infuture?


11/92

The First Computer

11

The BabbageDifference Engine

(1832)

25,000 parts

cost: 17,470


12/92

ENIAC - The first electronic computer(1946)

12


13/92

The Transistor Revolution

13

First transistor

Bell Labs, 1948


14/92

The First Integrated Circuits

Bipolar logic

1960s

14

ECL 3-input Gate

Motorola 1966


15/92

Intel 4004 Micro-Processor

19711000 transistors1 MHz operation

15


16/92

Intel Pentium (IV) microprocessor

2002>1 Million transistors>3 GHz operation

16


17/92

Chips Everywhere!

17


18/92

Who is this Guy?

18

Moores Law: Number of transistorsdoubles every 18 months


19/92

Moores Law

In 1965, Gordon Moore noted that thenumber of transistors on a chip doubled

ever 18 to 24 months.

19

He made a prediction thatsemiconductor technology will double its

effectiveness every 18 months


20/92

Moores Law

1 6

1 5

1 4

1 3

1 2

1 1

1 0

9

U

M

B

ER

O

F

G

RA

TED

FU

N

C

TIO

N

20

8

7

6

5

4

3

2

1

0

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

LO

G

2

O

F

TH

E

N

CO

M

PO

N

EN

TS

PER

IN

T

Electronics, April 19, 1965.


21/92

Moores Law

1965: Gordon Moore plotted transistoron each chip Fit straight line on semilog scale

Transistor counts have doubled every 26 months

1,000,000,000

ECE425

Year

Transistors

40048008

8080

8086

80286Intel386

Intel486Pentium

Pentium ProPentium II

Pentium III

Pentium 4

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

1970 1975 1980 1985 1990 1995 2000

SSI: 10 gatesMSI: 1000 gatesLSI: 10,000 gates

VLSI: > 10k gates


22/92

Corollaries (1)

Many other factors grow exponentially Ex: clock frequency, processor performance

1,000

10,000

4004

8008

Year

1

10

100

1970 1975 1980 1985 1990 1995 2000 2005

8080

8086

80286

Intel386

Intel486

Pentium

Pentium Pro/II/III

Pentium 4

ClockSpeed(MHz)


23/92

Corollaries (2)

Since the cost of the printing process (calledwafer fabrication) is growing at a slower rate, itimplies that the cost per function, is droppingexponentially. At each new generations, eachgate cost about 1/2 what it did 3 years ago.Shrinking an existing chip makes it cheaper!

yearyear

diecost

ln(cost/function)


24/92

What are inside a chip?

A chip may include: Hundreds of millions of transistors

~Mb embedded SRAM

DSP, IP cores

PLL, ADC, DAC

100+ internal clocks

24

Design issues: Speed

Power

Area Signal integrity

Process variation

Manufacturing yield

Source: Byran Preas


25/92

Chip Design Productivity Crisis

58%/Yr. Complexity

growth rate100,000

1,000,000

10,000,000

1,000,000

10,000,000

100,000,000

Chip

(K)

ff-M

onth

25

xxx

xxx

x

21%/Yr.Productivity growth rate

x

1

10

100

1,000

,

199810

100

1,000

10,000

,

Transistors/

Transistor/St

2003

Source NTRS97


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Evolution in Complexity

26


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Transistor Counts

1,000,000

100,000

10,000

K1 Billion1 Billion

TransistorsTransistors

PentiumIIPentium

III

27

1,000

10

100

1

1975 1980 1985 1990 1995 2000 2005 2010

8086

80286i386

i486Pentium

PentiumPro

Source: IntelSource: Intel

ProjectedProjected

Courtesy, Intel


28/92

Moores law in Microprocessors

Pentium procP6

10

100

1000

tors

(MT)

2X growth in 1.96 years!

28

4004

80088080

8085 8086

286386

0.001

0.01

0.1

1970 1980 1990 2000 2010

Year

Trans

i

Transistors on Lead Microprocessors double every 2 years

Courtesy, Intel


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Die Size Growth

286386

486 Pentium procP6

10

100

size

(mm

)

29

40048008

8085

1

1970 1980 1990 2000 2010

Year

Di

~7% growth per year

~2X growth in 10 years

Die size grows by 14% to satisfy Moores Law

Courtesy, Intel


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Frequency

P6

Pentium proc

48638610

100

1000

10000

uency

(Mhz

)Doubles every2 years

30

8086

8080

80084004

0.1

1

1970 1980 1990 2000 2010Year

Fre

Lead Microprocessors frequency doubles every 2 years

Courtesy, Intel


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Power Dissipation

P6Pentium proc

486

386

2868086

8085

10

100

we

r(Wa

tts

)

31

80808008

4004

0.1

1971 1974 1978 1985 1992 2000Year

P

Lead Microprocessors power continues to increase

Courtesy, Intel


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Power will be a major problem

5KW18KW

1.5KW

500W

8086286 486

Pentium proc100

1000

10000

100000

ower

(Wa

tts

)

32

40048008

80808085

0.1

1

1971 1974 1978 1985 1992 2000 2004 2008Year

P

Power delivery and dissipation will be prohibitive

Courtesy, Intel


33/92

Power density

100

1000

10000

Dens

ity

(W/cm

2)

Nuclear

Reactor

Rocket

Nozzle

33

40048008

8080

8085

8086

286386

486Pentium proc

P6

1

10

1970 1980 1990 2000 2010Year

Power

Hot Plate

Power density too high to keep junctions at low temp

Courtesy, Intel


34/92

Not Only Microprocessors

Small

Signal RF

Power

RF

CellPhone

34

Digital Cellular Market

(Phones Shipped)

1996 1997 1998 1999 2000

Units 48M 86M 162M 260M 435MAnalog

Baseband

Digital Baseband

(DSP + MCU)

Power

Management

(data from Texas Instruments)(data from Texas Instruments)


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Challenges in Digital Design

Microscopic Problems

Ultra-high speed design

Macroscopic Issues

Time-to-Market

35

Noise, Crosstalk

Reliability, Manufacturability

Power Dissipation

Clock distribution.

Everything Looks a Little Different

High-Level Abstractions

Reuse & IP: Portability

Predictability

etc.

and Theres a Lot of Them!

?


36/92

Productivity Trends

1,000

10,000

100,000

1,000,000

10,000,000

10,000

100,000

1,000,000

10,000,000

100,000,000

Logic Tr./Chip

Tr./Staff Month.

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1T

ransistorperChip(M)

10

100

1,000

10,000

100,000

Productivity

rans./

Staff-Mo.

Complexity

36

1

10

100

2

003

1

981

1

983

1

985

1

987

1

989

1

991

1

993

1

995

1

997

1

999

2

001

2

005

2

007

2

009

10

100

1,000x

xx

xxx

x

21%/Yr. compoundProductivity growth rate

x0.1

0.01

0.001

Logic

0.01

0.1

1

(K)

Source: Sematech

Complexity outpaces design productivity

Courtesy, ITRS Roadmap


37/92

Why Scaling?

Technology shrinks by 0.7/generation

With every generation can integrate 2x morefunctions per chip; chip cost does not increasesignificantly

Cost of a function decreases b 2x

37

But How to design chips with more and more functions?

Design engineering population does not double every

two years Hence, a need for more efficient design methods

Exploit different levels of abstraction


38/92

The Challenge in VLSI Design Managing Complexity

Simplify the design problem

Cant understand 10M transistors, or 100M rectangles

Need to make less complex (and less numerous) models

Abstraction

Simplified model for a thing, works well in some subset of the design

space Modeling Constraints

Needed to ensure that the abstractions are valid

Might work if you violate constraints, but guarantees are off

Understand the underlying technology

Provide a feeling for what abstractions and constraints are needed.

Determine efficient solutions (make the right tradeoffs).

CAD tools use the abstractions and constraints to help us manage the complexity. They do not replace the need to understand the technology.

In fact, we now need to understand how tools work.


39/92

Reality of VLSI Design JugglingTradeoffs

Bottom line is $$$$

To the VLSI designer, the external constraints and issues aremulti-dimensional.

Design time and

Performance

Portables (power - performance/area)

DRAM (area - features/performance)

DSP (design time/area - performance)

Military (robustness - power/performance)

Area

resources o us ness

Power


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Design Abstraction Levels

+

MODULE

SYSTEM

40

n+n+

S

G

D

DEVICE

CIRCUIT


41/92

Design Metrics

How to evaluate performance of adigital circuit (gate, block, )? Cost

Reliabilit

41

Scalability

Speed (delay, operating frequency)

Power dissipation

Energy to perform a function


42/92

Cost of Integrated Circuits

NRE (non-recurrent engineering) costs

design time and effort, mask generation

one-time cost factor

42

ecurren cos s

silicon processing, packaging, test

proportional to volume

proportional to chip area


43/92


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Cost per Transistor

0.010.01

0.10.1

11

cost:cost:--perper--transistortransistor

Fabrication capital cost per transistor (Moores law)

45

0.00000010.0000001

0.0000010.000001

0.000010.00001

0.00010.0001

0.0010.001

19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012


46/92

Basic Design Flow

System design Instruction set for processor

Hardware/software partition

Memory, cache

System/Architectural Design

46

Logic synthesis

Logic optimization

Technology mapping

Physical design Floorplanning

Placement

Routing

Physical Design/Layout

Fabrication


47/92

Design Cycles

System/Architectural Design

Logic Design

HDL

47

Physical Design/Layout

Fabrication

er ca on mu a on

Parasitic Extraction

Testing


48/92

Design and Technology Styles

Custom design Mostly manual design, long design cycle

High performance, high volume

Microprocessors, analog, leaf cells, IP

48

Standard cell Pre-designed cells, CAD, short design cycle

Medium performance, ASIC

FPGA/PLD Pre-fabricated, fast automated design, low cost

Prototyping, reconfigurable computing


49/92

Integrated Circuits

Uses for digital IC technology today:standard microprocessors

used in desktop PCs, and embedded applications

memory chips (DRAM, SRAM)

application specific ICs (ASICs)

can be optimized for low-power, low-cost, high-performancehigh-design cost

field programmable logic devices (FPGAs)

customized to particular application

short time to market

relatively high part cost


50/92


51/92

What is the next wave?


52/92

The Embedded Processor

What?A programmable processor whose

programming interface is not accessible to the

end-user of the product.

The only user-interaction is through the actualapp ca on.


53/92

- The micro-controller is embedded in the appliance

- You often are not aware of the fact that it contains

a micro-controller (e.g. 70 micro-controllers in a modern

high end car: engine control, ABS, airbag, interior

illumination, central lock, alarm, radio, ...)


54/92

Design Process

Design : specify andenter the design intent

Verify:

verify thecorrectness of

design and

implementation

refine the

design

through all

phases


55/92

Digital Design Objectives

Digital design process can be described in terms of:

Area on the chip required by the design.

The critical path delay of the design.

The testability of the design.

Power dissipation of the circuit.

The art of digital design is finding the optimal tradeoffs.


56/92

Synchronous Digital Hardware Systems

Synchronous: Clocked - all changes in the

system are controlled by a global clock (notasynchronous)

values (signals) take on discrete values (not

analog).


57/92

Clocking MethodologyAll storage elements are clocked by thesame clock edge

The combination logic blocks:

Inputs are updated at each clock tick

clock tick

Clk

.

.

.

.

.

.

.

.

.

.

.

.

Combination Logic


58/92

Critical Path & Cycle TimeCritical path: the slowest path between any twostorage devices

Cycle time is a function of the critical path

must be greater than:

Clock-to-Q + Longest Path through Combination Logic +

Clk

.

.

.

.

.

.

.

.

.

.

.

.


59/92


60/92

DSP

flexibility

efficiency

Programmable

CPU DSP

Programmable Application specific

instruction setprocessor (ASIP)

Application

specific processor


61/92

Design Cycle

Specification

Design

Design

Improvements

Modeling

Simulation &

Verification

(Compl.&Perf.&Power)

FPGA

Implementation


62/92

Design Examples

Massively Parallel Fingerprint Recognitionystem

Digital Designof SignalProcessing Systems,John Wiley & Sons by Shoab A. Khan


63/92

Massively Parallel Fingerprint Recognition System

Real-time identity

management of largeBorderlessEconomies

user base requires a

scalable massively

parallel fingerprint

recognition systemMultimillion

Matching server

ecommerce

Rise of Cloud

Computing

Reforms

National

Database

Border

Control Mobile devices andtrusted access

anywhere

Digital Designof SignalProcessing Systems,John Wiley & Sons by Dr.ShoabA. Khan


64/92

la

Modu

Application/ Services

User Access and Security Module

License Manager

Open APIs

Fingerprint Acquisition Module

Multimillion Matches

Enroll Verify Identify

ablelar,Sc

Q ua li ty Che ck Ima ge Enha nc em en t

mage rocess ng o u e

Template GeneratorDatabase

Component

Feature Extraction Module

Remote configurableMatching Module

Report Generator

User Access andSecurity Module

Digital Designof SignalProcessing Systems,John Wiley & Sons by Dr.ShoabA. Khan 3


65/92

Central Matching System

CENTRALDATABASE

FPM

SERVER

FPM

SERVER

FPM

SERVER

FPM

SERVER

Digital Designof SignalProcessing Systems,John Wiley & Sons by Dr.ShoabA. Khan37


66/92

Extension of application as global authentication service



67/92

Design Strategies

GPPprogramming flexibility

High code and low computationally intensivecode mapping

High power consumption

DSPProgramming flexibility

Computationally intensive & Non structured

code

Computationally intensive structured code

Programmability is more complex

ASICLower cost, low power

No flexibility of programming

Standard algorithms



68/92

Flexibility vs Efficiency

Efficiency verses flexibility tradeoff goes upGPP

DSPApplication Specific solutionHW based Instruction set of dedicated design on an FPGA or

ASIC



69/92

Design decision and complexity

Conceptual level design decisions are

less complex but have a grave impact

on the design

The complexity increases as design

moves down in the design cycle

critical



70/92

Example: Design Partitioning and Mapping

A Satellite burst modem receiverDSP maps irregular code intensiveapplication

Burst detection

Parameter Estimation

Correction loops

Demodulation

FPGA maps regular code intensive

and interfaces Forward Error Correction Codin

Glue Logic

ASICs standard code intensive Digital Down Converter

GPP maps code intensive anduser interfaces

Modem control software

Initialization and configurationsoftware

User interface



71/92

Verilog a SW Language to Design HW

Verilog is an implementation languageYou realize something using standarddigital design techniques, and thenimplement the circuit using Verilog

tell other tools what type of circuit element

to implement

Verilog is a type of software used to

describe hardware; it is an HDL, orHardware Description Language, NOT a

software programming language


72/92

Then why use Verilog?

Because Verilog looks similar to C, which issomething a lot of people understand

Verilog is less tedious than schematic entry

Its easy to develop test benches in Verilog


73/92

How Verilog is like traditional software?

Compilation and interpretationHas software constructs like while / for

loops, etc

Behaves like software at the lowest level,

,


74/92

How Verilog is not like traditional software?

Verilog can represent constructs that arephysically realizable that is, they represent(and model) real circuitry

From a higher, user level perspective,

Verilo executes in arallel like hardwarewould


75/92

Other Verilog tidbits

A large percentage of Verilog constructs areNOT realizable in gates

Design the circuit on paper... and THEN

code it into Verilog

,ignoring the software aspects of it


76/92

What do we do with the Verilog once we have it?

Two types of tools that use the Verilog wedevelop

Simulator (Silos, Verilog-XL, VCS, Veriwell,Modelsim)Synthesis (Synopsys Design Compiler)

functionality of the circuit via test benchesthat stimulate the design, and check forexpected results.

Synthesis tools take the Verilog as input andattempt to create the circuit described bythe Verilog.


77/92

Overview of HDLs

Hardware description languages (HDLs)

Are computer-based hardware programming languages

Allow modeling and simulating the functional behavior andtiming of digital hardware

Synthesis tools take an HDL description and generate a

77

ec no ogy-spec c ne s

Two main HDLs used by industry

Verilog HDL (C-based, industry-driven)

VHSIC HDL or VHDL (Ada-based,

defense/industry/university-driven).


78/92

Why do we need HDLs ?

HDL can describe both circuit structure andbehavior Schematics describe only circuit structure

C language describes only behaviors

78

design

High portability and readability

Enable rapid prototyping

Support different hardware styles


79/92

What do we need from HDLs ?

Describe Combinational logic

Level sensitive storage devices

Edge-triggered storage devices

79

hierarchical design Behavioral level

Dataflow level

Gate level

Switch level

Support for hardware concurrency


80/92

Two major HDLs

Verilog Slightly better at gate/transistor level

Language style close to C/C++

Pre-defined data type, easy to use

80

Slightly better at system level

Language style close to Pascal

User-defined data type, more flexible

Equally effective, personal preference


81/92

Synthesis of HDLs

Takes a description of what a circuit DOES

Creates the hardware to DO it

HDLs may LOOK like software, but theyre not!

NOT a program

81

Though we do simulate them on computers

Dont confuse them!

Also use HDLs to test the hardware you create

This is more like software


82/92

Describing Hardware!

All hardware createdduring synthesis Even ifa is true, still

if (a) f = c & d;

else if (b) f = d;

else f = d & e;

82

Learn to understand

how descriptionstranslated tohardware

f

ab

c

d

e


83/92

Why Use an HDL?

More and more transistors can fit on a chip

Allows larger designs!

Work at transistor/gate level for large designs: hard

Many designs need to go to production quickly

Abstract large hardware designs!

83

Tools then design the hardware for you

BIG CAVEAT

Good descriptions => Good hardware

Bad descriptions => BAD hardware!


84/92

Why Use an HDL?

Simplified & faster design process

Explore larger solution space

Smaller, faster, lower power

Throughput vs. latency

Examine more design tradeoffs

84

Design errors still possible, but in fewer places

Generally easier to find and fix

Can reuse design to target different technologies

Dont manually change all transistors for rule change


85/92

Other Important HDL Features

Are highly portable (text)

Are self-documenting (when commented well)

Describe multiple levels of abstraction

Represent parallelism

Provides many descriptive styles

85

Register Transfer Level (RTL)

Behavioral

Serve as input for synthesis tools


86/92

Hardware Implementations

HDLs can be compiled to semi-custom andprogrammable hardware implementations

F u l l S e m i - P r o g r a m m a b l e

86

Standard

Cell

Gate

ArrayFPGA PLD

Manual

VLSI

u s o m u s o m

less work, faster time to market

implementation efficiency


87/92

Standard Cells

Library of common gates and structures (cells)

Decompose hardware in terms of these cells

Arrange the cells on the chip

Connect them using metal wiring

87


88/92

FPGAs

Programmable hardware

Use small memories as truth tables of functions

Decompose circuit into these blocks

Connect using programmable routing

SRAM bits control functionality

88

P

P1P2

P3P4P5

P6P7

P8

I1 I3I2

OUT

FPGA Tiles


89/92

Schematic Design

aAdd_half

sum

a

b sum

89

c_ou

sum = a

bc_out = a b

c_out

_ _


90/92

Module portsModule name

Taste of Verilog

moduleAdd_half ( sum, c_out, a, b );

input a, b;

output sum, c_out;

Declaration of port modes

90

Verilog keywords

_ _

xor(sum, a, b);

nand (c_out_bar, a, b);

not (c_out, c_out_bar);

endmodule

Instantiation of primitive gates

c_out

a

b sum

c_out_bar


91/92

Behavioral Description

moduleAdd_half ( sum, c_out, a, b );

input a, b;

output sum, c_out;

reg sum, c_out;

a sum

91

begin

sum = a b; // Exclusive or

c_out = a & b; // And

endendmodule

b

_

c_out


92/92

Example of Flip-flop

module Flip_flop ( q, data_in, clk, rst );

input data_in, clk, rst;

output q;

reg q;

data_in q

rst

clk

always @ ( posedge clk )

begin

if( rst == 1) q = 0;

else q = data_in;

end

endmodule

Declaration of synchronous behavior

Procedural statement

digital system design lec 1a (1)

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