Combinational logic
STATIC CMOS GATES
no clock design
Can Be Made pipelined By Inserting Latchesin between
Combinational logic
STATIC CMOS GATES
no clock design
Can Be Made pipelined By Inserting Latchesin between
Drawback of static cmos
• 2N devices required• Prop delay inc with increase in fanin
because of inc in Cint, large series chain
Uniform transistor sizing
• For the gate, Find equivalent invertermodel
• Find the required transistor w/L• Hence estimate w/L of each transistor
• For the gate, Find equivalent invertermodel
• Find the required transistor w/L• Hence estimate w/L of each transistor
Other delay reduction techniques• Progressive transistor sizing• Input reordering• Logic restructuring
Power reduction- Time multiplexing ofresources—area reduces, activity increases
Very low switching activity Very high switching activity as bustoggles between 0 and 1
Xor/ XnorADVANTAGE---TRANSISTOR SHARING
DCVSL is advantageous forfull adder implementationThen static CMOS
DCVSL is advantageous forfull adder implementationThen static CMOS