Combinational logic

STATIC CMOS GATES

no clock design

Can Be Made pipelined By Inserting Latchesin between

Combinational logic

STATIC CMOS GATES

no clock design

Can Be Made pipelined By Inserting Latchesin between

Design StylesFull Static CMOS or complementary logic

NAND NOR

XOR/ XNOR

DRAWBACK

complementary signalsare required

F = D + A. (B+C)F = D + A. (B+C)

static CMOS gateVTC--Input data dependent

Tphl--Delay computation –NANDstate of intermediate nodes matter --worst case

Drawback of static cmos

• 2N devices required• Prop delay inc with increase in fanin

because of inc in Cint, large series chain

Uniform transistor sizing

• For the gate, Find equivalent invertermodel

• Find the required transistor w/L• Hence estimate w/L of each transistor

• For the gate, Find equivalent invertermodel

• Find the required transistor w/L• Hence estimate w/L of each transistor

Influence of fan-in / fanouton propagation delay

Other delay reduction techniques• Progressive transistor sizing• Input reordering• Logic restructuring

Reduce power consumption

Reduce switching activity

Power consumption due to glitches

Power reduction—balanced signalpath for glitch reduction

Logic restructuring for loweringswitching activity

Power reduction- Input reorderingaffects

Power reduction- Time multiplexing ofresources—area reduces, activity increases

Very low switching activity Very high switching activity as bustoggles between 0 and 1

Other design styles--PseudoNMOS

DCVSL

Xor/ XnorADVANTAGE---TRANSISTOR SHARING

DCVSL is advantageous forfull adder implementationThen static CMOS

DCVSL is advantageous forfull adder implementationThen static CMOS

NAND/ AND

Adder

Other logic design styles

Switch logic