Download - MIPI Cadence Presentation
Confidential
Shri Jaganathan Solutions Architect Cadence Design Systems
MIPI MPHY OVERVIEW
2 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
• Introduction • Who is MIPI Alliance • What MIPI Do • MPhy Introduction • TX- Key parameters • RX-Key parameters
AGENDA
3 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Who is MIPI® Alliance?
• MIPI drive mobile and mobile-influenced interface technology through the development of hardware and software specifications
• MIPI work globally and collaboratively with other standards bodies to benefit the mobile ecosystem
Copyright © 2013 MIPI Alliance. All rights reserved.
4 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
What MIPI Do
• 45+ interface specifications released to date • MIPI has full ecosystem of members to support
many types of mobile and mobile-influenced designs
• Specs are widely adopted for designs across the mobile industry and beyond
• 255 members worldwide
Copyright © 2013 MIPI Alliance. All rights reserved.
5 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
MIPI Overview
6 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
MIPI Interfaces / Stack
UniPro 1.5 and
2.0
Conf PIE
DDB
M-PHY
serial I/F
PTI
CMOS CMOS
M-PHY
serial I/F
CMOS-based
SLIMbus
CMOS-based
M-PHY
serial I/F
D-PHY
serial I/F
D-PHY
serial I/F
D-PHY
serial I/F
PHY
STP
HSI UniPro 1.5 and
2.0
UniPro 1.0
Transport
DigRF 4G
DigRF 3G
SPMI :
Power Mgmt.
RF-FE:
RF Control DSI-1 CSI-2
App-data
ICLC ICLC DCS
App-control
NAND SW IMF
Software
Gigabit Trace Trace Mass
Storage IPC BB-RF 4G BB-RF 3G Control Audio/ Data/Ctrl
UniPort- M
UniPort- D Display Camera
TWP OST
OST FrameWork
App-data
App-data
M-PHY
serial I/F
UniPro 1.5 and
2.0
Conf
7 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
8 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
• M-PHY – V1.0 board approved 08 FEB 2011 – 1.45Gbps – V2.0 Released on June 2012 – extends operation to 2.9Gbps – V3.0 Released on Oct 2013 – extends operation to 5.8Gbps – V4.0 expected in 2014 extends operation to 11.6Gbps
– Connects Modem DigRF v4 and Memory LLI v1.0 to the Application Processor – Next generation cameras CSI-3 v0.8, displays DSI-2 v0.1 – Joint Standard Development: JEDEC UFS v1.1, USB SSIC v1, PCI Mobile Express
– Features – Custom Clock – Self Consistent – Aggressive Power Management – Optical/Repeater ready
MPHY Specification Overview
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M-PHY Introduction: Lane, Link and More…
Picture taken from the MPHY specification document
10 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-PHY Introduction: Lane, Link and More…
M-TX = TX
Module
M-RX = RX
Module
Picture taken from the MPHY specification document
11 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-PHY Introduction: Lane, Link and More…
Lane = unidirectional single-signal physical channel. Consists of one M-
TX, one M-RX and one line
Picture taken from the MPHY specification document
12 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-PHY Introduction: Lane, Link and More…
SUB-LINK = a collection of lanes all in one direction
Picture taken from the MPHY specification document
13 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Link = 2 sublinks (one each in opposite direction) + Lane management function
M-PHY Introduction: Lane, Link and More…
Picture taken from the MPHY specification document
14 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-TX State Diagram
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M-RX State Diagram
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M-PHY Burst Operation
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M-PHY V1.0
• HS Burst 25mW • LS Burst 1mW • Stall ns 10mW • Sleep us 100uW • Hibern8 0.1-1ms 10uW
state recovery power latency
Assumption: one M-TX and one M-RX (including clock multiplication)
Race to Halt Power Heuristics
HS Burst
Stall
LS Burst
Sleep
Hibern8
Disable
Power On
Power M-PHY States
18 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-PHY Configuration Using protocol configuration mechanism
• Local protocol checks capabilities of local PHY and … … receives capabilities of remote PHY
• Protocol decision on operation profile • Profile request send to local PHY and via the protocol layer to the remote
PHY using the current PHY operation mode • INIT-PCC cycle through the PHYs will activate the change • Optical converters can be configured by flushing configuration data
during the INIT-PCC cycle
E/O O/E PHY PHY PROT PROT
E/O O/E LOCAL REMOTE
19 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-PHY Configuration Using protocol configuration mechanism
• Local protocol checks capabilities of local PHY and … … receives capabilities of remote PHY
• Protocol decision on operation profile • Profile request send to local PHY and via the protocol layer to the remote
PHY using the current PHY operation mode • INIT-PCC cycle through the PHYs will activate the change • Optical converters can be configured by flushing configuration data
during the INIT-PCC cycle
E/O O/E PHY PHY PROT PROT
E/O O/E LOCAL REMOTE
20 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-PHY Configuration Using protocol configuration mechanism
• Local protocol checks capabilities of local PHY and … … receives capabilities of remote PHY
• Protocol decision on operation profile • Profile request send to local PHY and via the protocol layer to the remote
PHY using the current PHY operation mode • INIT-PCC cycle through the PHYs will activate the change • Optical converters can be configured by flushing configuration data
during the INIT-PCC cycle
E/O O/E PHY PHY PROT PROT
E/O O/E LOCAL REMOTE
??
21 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-PHY Configuration Using protocol configuration mechanism
• Local protocol checks capabilities of local PHY and … … receives capabilities of remote PHY
• Protocol decision on operation profile • Profile request send to local PHY and via the protocol layer to the remote
PHY using the current PHY operation mode • INIT-PCC cycle through the PHYs will activate the change • Optical converters can be configured by flushing configuration data
during the INIT-PCC cycle
E/O O/E PHY PHY PROT PROT
E/O O/E LOCAL REMOTE
??
22 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-PHY Configuration Using protocol configuration mechanism
• Local protocol checks capabilities of local PHY and … … receives capabilities of remote PHY
• Protocol decision on operation profile • Profile request send to local PHY and via the protocol layer to the remote
PHY using the current PHY operation mode • INIT-PCC cycle through the PHYs will activate the change • Optical converters can be configured by flushing configuration data
during the INIT-PCC cycle
E/O O/E PHY PHY PROT PROT
E/O O/E LOCAL REMOTE
??
23 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-PHY Configuration Using protocol configuration mechanism
• Local protocol checks capabilities of local PHY and … … receives capabilities of remote PHY
• Protocol decision on operation profile • Profile request send to local PHY and via the protocol layer to the remote
PHY using the current PHY operation mode • INIT-PCC cycle through the PHYs will activate the change • Optical converters can be configured by flushing configuration data
during the INIT-PCC cycle
E/O O/E PHY PHY PROT PROT
E/O O/E LOCAL REMOTE
??
24 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-PHY Specification Roadmap
M-PHY v1
Bandwidth support - HS GEAR 1 - PWM G0-G3 - SYSBURST Bandwidth Provisional - HS-Gear 2 - PWM G4-G5
Bandwidth support - HS GEAR 1 & 2 - PWM G0-G5 - SYSBURST Bandwidth Provisional - HS-Gear 3 - PWM G6-G7
Bandwidth support - HS GEAR 1,2 & 3 - PWM G0-G7 - SYSBURST Bandwidth Provisional HS-Gear 4
v2.0
M-PHY v3
2011 2012 2013
v1.0
v3.0
Bandwidth support - HS GEAR 1, 2, 3 & 4 - PWM G0-G7 - SYSBURST
M-PHY v4
v4.0
2014
1.45Gbps 2.9Gbps 5.8Gbps 11.6Gbps
DigRF v4
UFS
LLI/SSIC
CSI-3/Mobile Express
M-P
HY
supp
orts
:
M-PHY v2
25 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
DPHY and MPHY Comparison Feature DPHY MPHY
Min. number of pins per direction 4 2
Minimum configuration (# of pins) 4 4
Data traffic for minimum configuration
Unidirectional or half-duplex dual-simplex
Medium <30 cm PCB, flex,micro-coax
< 30 cm PCB, flex,micro coax,<1.2 m cable, optical
Data rate per lane
HS Mode 80 Mb/s - 1.5 Gb/s ~ 1.25, 2.5, 5 Gb/s (A series); ~ 1.5, 3, 6 Gb/s (B series)
LP Mode < 10 Mb/s 10k-600Mb/s
Electrical signaling
HS Mode SLVS - 200 mV SLVS - 200 mV
LP Mode LVCMOS - 1.2V SLVS - 200 mV w/o RX-RT
HS Clocking method DDR Source-Sync Clk Embedded Clk
HS Line coding None or 8b-9b 8b-10b
Power – Energy/bit Low Lower than DPHY
Receiver Complexity CDR not required CDR required
LP only PHY’s Disallowed Allowed
26 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
• High-Speed data transfer per lane – Multiple transmission speed ranges and rates per BURST mode to further scale
bandwidth to application needs; Mitigates interference problems.
• Supports both SYS and PWM mode LS operation – Flexibility in data rates
• Low power dissipation – Multiple power saving modes, where power consumption can be traded-off
against recovery time • Clocking flexibility: designed to be able to operate with independent local
reference clocks at each side, but suitable to exploit the benefits of a shared reference clock
• Optical friendly: enables low-complexity electro-optical signal conversion and optical data
• Distance: optimized for short interconnect (<10 cm) but extendable to a meter with good quality interconnect or even further with optical converters and optical waveguides.
• Configurability: differences in supported functionality (to reduce cost) and tune for best performance (implementation) without hampering interoperability
MIPI M-PHY IP Key Feature List
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MPHY – Key Features v3.0
• Supports 2 Low speed modes – Type-1 (PWM Signaling) – Type-2
• Supports 2 amplitude modes – LA – SA
• Supports 3 Speed modes and 2 rates per mode • Supports 8b-10b encoding • Supports Termination and no Termination modes • Standard RMMI interface definition
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PWM Bit waveform and Bit Stream Example
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Line Conditions and States
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Line Conditions and States
DIF-P and DIF-N : States during normal operation and used for data-transmission
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Line Conditions and States
DIF-Z : Possible only during power-up and power-saving states
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Line Conditions and States
DIF-Q : Possible only when the M-RX has been powered off.
33 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
MPHY TX Architecture
PPI Interface
HS / LS FSM
DATA PATH
DATA Serializer & Clock Gen
DRIVERS
TX_DP
TX_DN
CONTROL + BIST
LOOPBACK
HSCLK LSCLK
HSCLK LSCLK
BIST
CFGCLK
CTRLInterface
DATAInterface
CLK from CMN Block
RM
MI I
nter
face
Driver +
Term
34 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
PPI Interface
HS / LS FSM
DATA PATH
DATA DeSerializer & CDR
PREAMP + TERM
RX_DP
RX_DN
CONTROL
LOOPBACK
REFCLK
CFGCLK
CTRLInterface
DATAInterface
SYMCLK
DATA
MPHY RX Architecture
RM
MI I
nter
face
35 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
PPI Interface
HS / LS FSM
DATA PATH
DATA DeSerializer & CDR
PREAMP + TERM
RX_DP
RX_DN
CONTROL
LOOPBACK
REFCLK
CFGCLK
CTRLInterface
DATAInterface
SYMCLK
DATA
MPHY RX Architecture
RM
MI I
nter
face
HS Amp for G1/G2/G3
modes
36 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
PPI Interface
HS / LS FSM
DATA PATH
DATA DeSerializer & CDR
PREAMP + TERM
RX_DP
RX_DN
CONTROL
LOOPBACK
REFCLK
CFGCLK
CTRLInterface
DATAInterface
SYMCLK
DATA
MPHY RX Architecture
RM
MI I
nter
face
LP Amp for low-speed
modes
37 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
PPI Interface
HS / LS FSM
DATA PATH
DATA DeSerializer & CDR
PREAMP + TERM
RX_DP
RX_DN
CONTROL
LOOPBACK
REFCLK
CFGCLK
CTRLInterface
DATAInterface
SYMCLK
DATA
MPHY RX Architecture
RM
MI I
nter
face
Ultra low power squelch detector
for Hibernate mode
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Data Transfer Modes
Data Transfer Modes
HS Mode
HS-Gear1 (Mandatory)
HS-Gear2 (Optional)
HS-Gear3 (Optional)
LS Mode
PWM Mode (Type-1)
SYS mode (Type-2)
OR
AND
AND
AND
39 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
BIST Details
BISTGenerator
InputLatch
BISTSelect
Encoding+ Serializer
TXP
TXN
RXP
RXN
Decoding+ Deserializer
Output Latch
BISTChecker
from PPI/RMMI
to PPI/RMMI
BIST_FLAG
• Comprehensive BIST functionality to o Ease production testing o Support standalone bring-up of the IP.
• The BIST modules can generate and check various patterns ranging from simple data ramps to complex jitter-inducing patterns.
40 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
• Option to – generate and check various patterns like PRBS, CRPAT, CJTPAT
etc. – run the BIST infinitely or in a burst mode. – control the burst length. – control the idle time between bursts, within limits of the MPHY
specification. – send patterns that repeat in every burst or differ in every burst. – inject a single-bit error at a programmable point in the data stream.
• Supports observable BIST status • BIST error signal is observable at the IP port if required • BIST error counters are readable as status registers
BIST Features
41 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
• Burn-in Mode: Stress testing by putting TX and RX in maximum power consumption modes with the help of external loopback.
• Loopback Mode: Provides a transparent bit-by-bit path from an M-RX serial input to an M-TX serial output.
BIST Modes
42 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
MPHY – Silicon Validation
• No certification or Sigfest
• Conformance Test suite (CTS) – Developed as part of the PHY Work group – Defines Test procedures – Tek presentation will have details of this
43 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
MPHY – Silicon Validation
• Tx Test setup requirements – 20GHz BW Oscilloscope – 20GHz Active Probe – Clock Source – Digital IO Source/Capture card – Power supplies & Multimeters
• Rx Test setup requirements – BERT (with Datarate of atleast 7.5Gbps)
– Rj & Sj Jitter injection capabilities – ISI channel
44 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
MPHY – Silicon Validation Key Tx Parameters
• Jitter Test
• Eye Mask Test – Channel de-embedding
• PWM signal Test
45 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
• Jitter separation is a time consuming process if Spectral method is followed to get the exact Jitter separation.
• Dual Dirac method can be used to get the Jitter split much faster and if lesser number of samples can be taken and extrapolate the RJ numbers to reduce the time much lower.
• HS default mode is terminated mode and this has to be a 100ohm differential termination across Dp and Dn. This has to be measure at the pin. This can be achieved only through probing directly on a 100ohm terminated very near to the Dp/Dn pin using an active probe.
• Active probes normally have a high noise floor which adds RJ to the measurement and this is reflected on the TX measurements
Jitter Test
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Eye Mask Test
G1 and G2 eye diagram G3 Eye Diagram
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Impact of active probe noise
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• Unterminated mode probing
• PWM data decoding
PWM Test Challenges
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MPHY – Silicon Validation Key Rx Parameters
• Jitter Calibration and Test
• PWM signal and PPM Offset Test
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RX calibration Setup
DUT RX
Oscilloscope
Physical Calibration Setup
Pattern Generator
+ De-emphasis
+ Jitter Sources
SMA Cables
Replica Channel
Active Probe
Block diagram taken from CTS discussion PPT
51 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Jitter Mask for G3A
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0.8 8 10 26 100 166.4
Tota
l Jitt
er(U
I)
SJ Frequency(MHz)
Spec TJ
52 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
• RX input should have following components – Low frequency Jitter component as shown in the Jitter Mask – Low frequency RJ – High Frequency RJ – High frequency SJ tone – ISI to meet the Spec defines channel loss
• No Channel defined- RX spec is defined at the Pin
Jitter Components
53 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
• For PWM test data need to be sourced from 10kHz to 576MHz
• This test cannot be done directly using a BERT • Sourcing can be done by creating the PWM patterns by
adding 1’s and 0’s. • BER cannot be measured using BERT for PWM and this
need to be done by an On Chip Error counter or need to be captured using FPGA and compare. Another option is to loopback to TX and compare using BER counter in oscilloscope.
• PPM offset cannot be measure in loopback mode because of data rate mismatch.
PWM test and PPM offset
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Questions???
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Thank You