lowest risk design with cadence mipi verification ip 04 mipi tech on tour... · 2. vip functional...

Ken Huang

Principal Solutions Engineer

April 2015

Lowest Risk Design with Cadence MIPI Verification IP

© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design

Systems, Inc. in the United States and other countries. ARM and AMBA are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or

elsewhere. All rights reserved. All other trademarks are the property of their respective owners.

2 © 2013 Cadence Design Systems, Inc. All rights reserved.

New Systems, New Applications, New Challenges


Optimization Achieved via Specialized SoC I/Fs

1993 2000 2002 2004 2006 2008 2010 20142012

SDRAM

DDR

DDR2

DDR3

LPDDR

DDR4

LPDDR2

LPDDR3

LPDDR4

Wide IO

Wide IO 2

HMC

HBM

GDDR2

GDDR3

GDDR4

GDDR5

Example: Expanding variety of DRAM interfaces

2015


Specifications evolve fast

2005 2010 20142012

PCIe

Gen 2

PCIe

Gen 3

M-PCIe

PCIe Gen 4

NVM Express

MIPI

M-PHY

USB 2.0

USB 3.0

SuperSpeed

SuperSpeed

Inter-Chip (SSIC)

USB Power Delivery

USB 3.1

SuperSpeed+

MIPI M-PHY

2008 2010 2012 2014

AM

BA

US

BP

CIe

APB

ATB

AXI 4 Stream

ACE-Lite

AXI4

ACE

AXI4-Lite

AMBA 4

CHIAMBA 5

AMBA 4

2015

D-PHY 1.0

CSI-2 1.0

CSI-2 2.0

CSI-2 1.3

CSI-2 1.2

MIP

I C

SI-

2CSI-2 1.0.1

D-PHY 1.1

C-PHY 1.0


Complexity growing dramatically

AMBA® 3

AXI™PCI Express

Gen1

DDR4 AMBA® 4

ACE™

PCI Express

Gen3

DDR1


Verification IP is a Critical Solution Component

• Interface VIP

•Memory Models

•Power Tools

• IP

•SoC

•Package

•PCB

•Memory

•Processors

• Interfaces

•Performance

•Footprint

•Power/Thermal

•Cost Systemanalysis

Design IP

VerificationIP

EDA


• Check protocol compliance as per protocol specification

• Verify host and device designs

• Include multiple state machine monitors relevant to both sides of interface

• Generates and drives test sequences

• Make vs. Buy:– average complexity protocol = man years of development

– use across many designs = robust and mature

How Does VIP Help?Automates verification for standard interfaces

OFF

ON

Initialization WriteReadRefresh Full Protocol

Inspection

Drive

Tests


• Configure VIP to match design– Dozens of protocol parameters to sift through

• Detecting and debug protocol violations

• Ensure protocol compliance – Create test suite

– Constrained random and directed tests

– Select tests that match the specific design application

– Collect and analyze functional coverage from multiple simulation runs

– Interpret results– What do all the covergroup combinations mean?

– Does the design really comply with the protocol specification?

Common Interface Verification challenges


• Configuration “wizard”

• Configures VIP to match design

• Prohibits selection of incompatible parameters

• Configurations saved in SOMA files

Cadence PureView VIP ConfiguratorEasy to use, built for verification engineers


• Configure VIP to match design– Dozens of protocol parameters to sift through

• Detecting and debug protocol violations

• Ensure protocol compliance – Create test suite

– Constrained random and directed tests

– Select tests that match the specific design application

– Collect and analyze functional coverage from multiple simulation runs

– Interpret results– What do all the covergroup combinations mean?

– Does the design really comply with the protocol specification?

Common Interface Verification challenges


TripleCheck – 3rd Generation Compliance Solution

Triple

Check

3. TC vPlan

• Protocol-meaningful verification objectives

• Linked to native SV/ecoverage database

• Automatically filtered to match DUT specific configuration

• Integrated with Incisive Verification Manager and others

• Easy to understand correlation of coverage results to protocol specification

2. VIP Functional Coverage

• Native SV and e coverage database

• Support for all simulators

• Reachable and tested

• Filtered automatically per user configuration

• Complete coverage of your configuration

1. TC Test Suite

• Ready to use, spec driven tests

• Optimized combination of Directed and Constrained-random sequences

• Reaching 100% of vPlan out of the box

• Filtered, customized automatically per customer’s configuration

• Runs on all simulators

• Early & Fast

verification

Triple Check delivers substantial “Protocol Verification Efficiency” by

providing a built-in Protocol Test Suite and a coverage mapped

Verification Plan through an automated use flow


MIPI VIP protocols support (March 2015)Supported Interfaces

Protocols Version Comments

MIPI CSI-2 v1.3

MIPI CSI-3 v1.0

MIPI DSI v1.2

MIPI DSI-2 ** Support DSI over C-PHY

and DSI 1.2

MIPI D-PHY v1.2

MIPI C-PHY v1.0

MIPI M-PHY v3.1

MIPI LLI v2.0

MIPI SLIMbus v1.1

MIPI SoundWire V1.0

MIPI UniPro v1.61

MIPI DigRF v4 v1.0

MIPI DBI v2.0

MIPI DPI v2.0

** This specification is rapidly evolving. The VIP is kept current with the latest specification updates.

lowest risk design with cadence mipi verification ip 04 mipi tech on tour... · 2. vip functional...

Documents